OV9620 OMNIVISION | Alldatasheet
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CAMERACHIP™ D ATASHEET CameraChip™ Datasheet Datasheet – OV9620/9120 © OmniVision Technologies Inc., 2002 OVT CameraChip OV9620/9120 Last Modified: 22 February 2002 Revised Version: 2.0 THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. *Third-party brands, names, and trademarks are the property of their respective owners. Note: The information contained in this document is considered proprietary to OmniVision Technologies Inc. This information may be distributed only to individuals or organizations authorized by OmniVision Technologies, Inc. to receive said information. Individuals and/or organizations are not allowed to re-distribute said information without consent of OmniVision Te chnologies Inc. authorized representative(s).
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 Doc #DS102 Tel: (408) 733-3030 Fax: (408) 733-3061 Version 2.0 Email: info@ovt.com Website: http://www.ovt.com Page 1 Table of Contents
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 Doc #DS102 Tel: (408) 733-3030 Fax: (408) 733-3061 Version 2.0 Email: info@ovt.com Website: http://www.ovt.com Page 2
Description
The OV9620 (color) and OV9120 (black and white) are high- performance 1.3 mega-pixel CameraChips for digital still image and video camera products. Both devices incorporate a 1280x1024(SXGA) image array and an on-chip 10-bit A/D conver ter capable of operating at up to 15 frames per second (FPS) with full resolution. Proprietary sensor technology utilizes advanced algorithms to cancel Fixed Pattern Noise (FPN), eliminate smearing, and drastically reduce blooming. T he control registers allow for flexible control of timing, polarity, and CameraChip operation, which in turn allow the engineer a great deal of freedom in product design. F e a t u r e s Optical Black Level Calibration Video or Snapshot Operations Programmable/Auto Exposure and Gain Control Programmable/Auto White Balance Control Horizontal & Vertical Sub-sampling (4:2 & 4:2) Programmable Image Windowing Variable Frame Rate Control On-Chip R/G/B Channel and Luminance Average Counter Internal/External Frame Synchronization SCCB Slave Interface Power on Reset and Power Down Mode Figure 1. OV9620/OV9120 Pin Diagram
48 LCC
30 FPS
Ordering Information
Product Package Description OV9620 48 LCC 0.560 in2 COLOR, SXGA, VGA, Digital, SCCB interface OV9120 48 LCC 0.560 in2 B/W, SXGA, VGA, Digital, SCCB interface
Table 1. Pin Description
05 DEGND P Ground for sensor array decoder
06 VrLow A Sensor low reference. Bypass to ground with a 0.1µF capacitor. 07 PWDN I (0) Power down mode enable, active high. 08 FREX I (0) Snapshot trigger, use to activate a snapshot sequence. 09 SRAMT I (0) SRAM interface trigger, use to activate SRAM interface. 10 RESET I (0) Chip reset, active high. 11 SCCB_E I (0) SCCB interface enable signal, active low.
12 EXPSTB I (0) Snapshot exposure start trigger, “1” – sensor stays in reset mode, “0” – sensor
starts exposure. Only effect in snap-shot mode. 13 VGA I (0) Sensor resolution selecti on.”1” – VGA. “0” – SXGA resolution. 14 FSIN I (0) Frame synchronization input. 15 VcCHG A Sensor reference. Bypa ss to ground with a 0.1µF capacitor. 16 AVDD P 3.3-volt supply for analog circuits. 17 AGND P Ground for analog circuits. 18 ASUB P Ground for analog circuit’s substrate. 19 VrAD2 A A/D converter reference. By pass to ground with a 0.1µF capacitor. 20 ADVDD P 3.3-volt supply for A/D converter. 21 ADGND P Ground for A/D converter. 22 DVDD P 2.5-volt supply for digital circuits. 23 DGND P Ground for digital circuits. 24 D0 O Bit 0 of video port output. 25 D1 O Bit 1 of video port output. 26 D2 O Bit 2 of video port output. 27 D3 O Bit 3 of video port output. 28 D4 O Bit 4 of video port output. 29 XCLK1 I Crystal clock input. 30 XCLK2 O Crystal clock output. 31 PCLK O Pixel clock output. 32 D5 O Bit 5 of video port output. 33 D6 O Bit 6 of video port output. 34 D7 O Bit 7 of video port output. 35 D8 O Bit 8 of video port output. 36 D9 O Bit 9 of video port output. 37 DOVDD P 3.3-volt supply for digital video port. 38 DOGND P Ground for digital video port. 39 HREF I/O Horizontal reference output. synchronization input when chip in slave mode. input when chip in slave mode.
42 NC - Not connected
43 NC - Not connected
44 NC - Not connected
45 SIO_D I/O SCCB slave interface data input and output.
46 SIO_C I SCCB slave interface clock input
48 SGND P Ground for pixel array.
Table 2. General Characteristics Table 3. DC Characteristics (0°C ≤ TA ≤ 85°C, Voltages referenced to GND) Table 4. AC Characteristics (TA=25°C, VDD=3V) Table 5. Timing Characteristics
Figure 2. OV9620/9120 Light Response
This section describes the functions of the OV9620/9120. Figure 3. OV9620/OV9120 Block Diagram shows the color filter layout. Figure 4. Sensor array region color filter layout
1024 Active Lines
level calibration and interpolation. synchronous pixel read-out scheme. (AGC). The gain adjustment range is 0-24db. automatic white balance controller (AWB).
OV9620/OV9120 supports frame exposure mode. Typically the frame exposure mode must work with the aid of an external shutter. show the detailed timing for this mode. When the FREX pin is set high, the sensor will reset each line and output one black reference frame. is read out and stored. Also the exposure time is from falling edge of EXPSTB to external shutter close. will be the array leakage. By subtracting the leakage data from previous image frame, the results will be a very high quality image. Figures 14 and 15 show the detailed timing for this mode. 3040tp (1600tp for VGA) after VSYNC falling edge. Table 6. Frame exposure Timing Specifications
- Clock prescaler*: By changing the system clock
- Line adjustment**: By adding dummy pixel timing in
leaving the pixel rate as is.
- Vertical sync adjustment: By adding Dummy line
frames. The frame divider does not alter the video data rate. Figure 8 illustrates the operation of the frame rate divider. Refer to register [16] for details on setting the divider. Figure 12. Frame Division Example
1 Frame
mode (The default is master mode).
- System clock MCLK to XCLK1 pin
- Horizontal sync MHSYNC to CHSYNC pin
- Vertical frame sync MVSYNC to VSYNC pin
detailed timing considerations. Figure 13. Slave Mode Connection Figure 14. Slave Mode Timing R/G/B channels along with frame-averaged luminance level. values are calculated from 128 pixels per line (64 in VGA). Figure 15. RAM Interface Diagram
Figure 16. RAM Interface Timing complete hardware reset when it is pulled high (VCC). be initiated through the SCCB interface. control and monitoring of OV9620/OV9120 operation.
slave addresses for the OV9620/OV9120 are 60 for write and 61 for read. Table 13. SCCB Registers
00 GAIN 00 RW AGC gain control
01 BLUE 80 RW Blue gain control MSB, 8 bits (LSB 2 bits is in register [03]). Note: This function is not available on the OV9120 CameraChip. 02 RED 80 RW Red gain control MSB, 8 bits (LSB 2 bits is in register [03]). Note: This function is not available on the OV9120 CameraChip.
03 COMA 40 RW Common Control A
COMA[7:4] – AWB update threshold. Note: This function is not available on the OV9120 CameraChip.
04 COMB 00 RW Common Control B
05 BAVG 00 RW B channel average register
06 GeAVG 00 RW G channel average register, picked G pixels in the same line with B pixels
07 GoAVG 00 RW G channel average register, picked G pixels in the same line with R pixels
08 RAVG 00 RW R channel average register
09 COMC 0C RW Common Control C
voltage, “0”= selects internal reference as precharge voltage.
OV9620/OV9120 Datasheet Doc #DS102 © OmniVision Technologies Inc., 2002, version 2.0 Page 16 Sub- address (hex) Register Default (hex) Read/ Write Descriptions 0D COME 00 RW Common Control E COME[7] – SRAM output timing: “1” = enabled, “0” = disabled COME[6] – Anti-blooming control: “1” = Anti-blooming off, “0” = Anti-blooming on COME[5:3] – Reserved COME[2] – Clock output power-down pin status: “1” = tri-state the VSYNC and CHSYNC pins upon power-down,”0” = maintain internal default states at power- down COME[1] – Reserved COME[0] – Digital port output: “1” = disable data port output, “0” = enable data port output 0E COMF 017 RW Common Control F COMF[7] – System clock selection. “1”=use 48MHz system clock. “0”= Use 24MHz system clock COMF[6:5] – Sensor sampling reset timing selection: “00” = normal reset time “01” = long reset “10” = longer reset “11” = longest reset COMF[3] – Single frame transfer trigger: “1” = initialize the transfer of a single frame of data, this bit will be reset after the frame of data is completely transferred. COMF[2] – Port output range selection: “1” = output data range is 000 to 3FF “0” = data output limited to between 001 and 3FE. COMF[1] – Reserved COMF[0] – AGC option: “1” = enable AGC to change with exposure. “0” = disable AGC 0F COMG 47 RW Common Control G COMG[7] – Optical black output selection: “1” = enabled “0” = disabled COMG[6] – Black level calibrate selection: “1” = use optical black pixels to calibrate “0” = use electrical black reference COMG[5:4] – Reserved COMG[3] – Channel offset adjustment: “1” = enable offset adjustment, B/Ge/Go/R channel offset levels stored in registers [27], [28], [29] and [2C], “0” = disable offset adjustment COMG[2] – Data range selection: “1” = full range, “0” = data range limited to 3F0 – 010 COMG[1] – ADC black level calibration bias selection: “0” = 040 “1” = 010 COMG[0] – ADC black level calibration enable: “0” = disabled “1” = enabled
10 AEC 43 RW Automatic exposure control most signifi cant 8 bits for AEC bits 10-3 (least significant
3 bits in register 04) AEC[10:0] - Exposure time TEX = tLINE × AEC[10:0] Note: Set COMI Bit 2 to 0 to disable AEC
11 CLKRC 00 RW Clock rate control
CLKRC[7] – Internal PLL on/off selection: “0” = PLL disabled, “1” = PLL enabled CLKRC[6] – Digital video port master/slave selection: “0” = master mode, sensor provides PCLK, “1” = slave mode, external PCLK input from XCLK1 pin CLKRC[5:0] – Clock divider CLK = XCLK1/(decimal value of CLKRC bits 5-0 + 1)
OV9620/OV9120 Datasheet Doc #DS102 © OmniVision Technologies Inc., 2002, version 2.0 Page 17 Sub- address (hex) Register Default (hex) Read/ Write Descriptions
12 COMH 20 RW Common control H
COMH[7] – SRST, “1” initiates soft reset. All registers are set to factory default values after which the chip resumes normal operation. COMH[6] – Resolution selection, “1” = VGA, “0” = SXGA COMH[5] – Average Luminance Value pixel counter, “1” = on, “0” = off COMH[4] – CHSYNC pin output selection: “1” =composite sync output, “0” = output only horizontal sync COMH[3] – Master/Slave selection: “1” = slave mode, “0” = master mode COMH[2] – Window output selection: “1” = output all pixels “0” = output only pixels defined by window registers COMH[1] – Color bar test pattern: “1” = on, “0” = off COMH[0] – ADC mode selection: “1” = 4 channel ADC, “0” = 2 channel ADC
13 COMI 07 RW Common control I
COMI[7] – AEC speed selection: “0” = normal, “1” = faster AEC correction COMI[6] – AEC speed/step selection: “0” = small steps, slow, “1” = big steps, fast COMI[5] – Banding filter “0” = off, “1” = on, set minimum exposure time to 1/120s. COMI[4] – Banding filter option. Set to 0 if the main clock is 48Mhz and the PLL is on. Set to 1 if the main clock is 24Mhz with the PLL on or the clock is 48Mhz with the PLL off. COMI[3] – Reserved COMI[2] – Exposure control: ”0” = manual, “1” = automatic COMI[1] – AWB auto/manual control selection: ”0” = manual, “1” = auto COMI[0] – AGC auto/manual control selection: ”0” = manual, “1” = auto
14 COMJ 76 RW Common control J
COMJ[7:6] – AGC gain ceiling: “11” or “10” = 8x, “01” = 4x, “00” = 2x COMJ[5] – AEC preset initial value for auto exposure mode: “1” = enabled, “0” = disabled COMJ[4] – AWB preset initial value for auto white balance: “1” = enable, “0” = disable COMJ[3] – Auto Banding filter: “1” = automatically disable the banding filter if light is low. “0” = banding filter is always on/off depending on COMI[5] setting. COMJ[2] – VSYNC drop option: “1” = VSYNC is dropped if frame data is dropped. “0” = VSYNC is always output. COMJ[1] – Frame data drop option. “1” = drop frame data if exposure not in tolerance. In AEC mode data is normally dropped when data is out of range. “0” = disable data drop. COMJ[0] – Freeze current Exposure and Gain values: “1” = freeze, “0” = normal
15 COMK 00 RW Common Control K
COMK[7] – CHSYNC pin output swap: “1” = HREF “0” = CHSYNC COMK[6] – HREF pin output swap: “1” = CHSYNC, “0” = HREF COMK[5] – PCLK output selection: “1” = PCLK output qualified by HREF. “0”= PLCK always output COMK[4] – PCLK edge selection: “1” = data valid on PCLK rising edge. “0” = data valid on PCLK falling edge. COMK[3] – HREF output polarity: “1” = output negative HREF, HREF negative for data valid. “0” = output positive HREF COMK[2] – Composite sync polarity: “1” = negative, “0” = positive COMK[1] – VSYNC polarity: “1” = negative, “0” = positive COMK[0] – HSYNC polarity:”1” = negative, “0” = positive
16 FSD 00 RW Frame slot division
FSD[7] – Frame rate divider: “1” = enabled, “0” = disabled FSD[6] – Frame division: “1” = drop pre-selected number of frames, “0” = output pre-selected frame count. Note: Frame count is set with bits 0-5 below. FSD[5:0] – Frame rate divider: [00] = select 0 frames, [01] = all frames, [02] = select every other frame, or divide by 2, [03] – divide by 3 …, [3F] = select 1 out of every 63 frames.
OV9620/OV9120 Datasheet Doc #DS102 © OmniVision Technologies Inc., 2002, version 2.0 Page 18 Sub- address (hex) Register Default (hex) Read/ Write Descriptions
17 HREFST 1D
(13 VGA) RW Horizontal Window start most significant 8 bi ts, least significant bits in register [32] HS[9:0] – select beginning of horizontal window, each LSB represents two pixels. Adjustment steps must be 2 pixels in 2-channel ADC mode and 4 pixels in 4- channel ADC mode. Note: HS [9:0] should be less than HE [9:0].
18 HREFEND BD
(63 VGA) RW Horizontal Window end most significant 8 bits , least significant bits in register [32] HE [9:0] – select the end of the horizontal window, each LSB represents two pixels. Adjustment step must be 2 pixels in 2-channel ADC mode and 4 pixels in 4-channel ADC mode. Note: HE[9:0] should be larger than HS[9:0].
19 VSTRT 01
(02 VGA) RW Vertical Window line start 8 MSB, LSB in register [32] VS[8:0] – selects the vertical window start, each LSB represents 4 scan lines in SXGA or 2 lines in VGA. Note: VS[8:0] should less than VE[8:0]. 1A VEND 81 (7A VGA) RW Vertical Window line end higher 8 bits , lowest 1 bit in register [32] VE[8:0] – selects the vertical window end, each LSB represents 4 scan lines in SXGA and 2 lines in VGA. Note: VE[8:0] should larger than VS[7:0]. The adjustment range for vertical the window size is from [01] to [122] in SXGA and [01] to [0F4] in VGA. 1B PSHFT 00 RW Pixel shift PS[7:0] – Pixel delay count. Provides a method to fine-tune the output timing of the pixel data relative to the HREF pulse, it physically shifts the video data output time in units of pixel clock counts. The largest delay count is “FF” and is equal to 255*PCLK. 1C MIDH 7F R Manufacture ID byte: High MIDH[7:0] – read only, always returns “7F” as manufacturer’s ID no. 1D MIDL A2 R Manufacture ID byte: Low MIDL[7:0] – read only, always returns “A2” as manufacturer’s ID no. 1E Reserve 00 RW Reserved 1F LAEC 00 RW Reserved
20 BOFF 00 RW B Channel offset adjustment, auto cont rolled by internal circuit if COMG[0] = 1
BOFF[7] – offset direction: “0” = add BOFF[6:0]; “1” = subtract BOFF[6:0]
21 GeOFF 80 RW Ge Channel offset adjustment, auto c ontrolled by internal circuit if COMG[0] = 1
GeOFF[7] – offset direction: “0” = add GeOFF[6:0]; “1” = subtract GeOFF[6:0]
22 GoOFF 80 RW Go Channel offset adjustment, auto c ontrolled by internal circuit if COMG[0] = 1
GoOFF[7] – offset direction: “0” = add GoOFF[6:0]; “1” = subtract GoOFF[6:0].
23 ROFF 80 RW R Channel offset adjustment, auto cont rolled by internal circuit if COMG[0] = 1
ROFF[7] – offset direction: “0” = add ROFF[6:0]; “1” = subtract ROFF[6:0]
24 AEW A0 RW Luminance Signal High range for AEC/AGC operation
AEC/AGC value is decrease in auto modes when average luminance is greater than AEW [7:0]
25 AEB 88 RW Luminance Signal Low range for AEC/AGC operation
AEC/AGC values will increase in auto mode when average luminance is less than AEB [7:0] 26 VV F4 RW Fast mode large step range thresholds . Effective only in AEC/AGC fast mode (COMI [7] = 1) VV [7:4] - high threshold. VV [3:0] – low threshold. AEC/AGC may change in larger steps when luminance average is >VV [7:4] or <VV [3:0]
27 BBIAS 80 RW B Channel offset manual adjustm ent value, effect only when COMG[3] = 1
BBIAS[7] – offset direction: “0” = add BBIAS[6:0]; “1” = subtract BBIAS[6:0]
28 GeBIAS 80 RW Ge Channel offset manual adjus tment value, effect only when COMG[3] = 1
GeBIAS [7] – offset direction: “0” = add GeBIAS[6:0]; “1” = subtract GeBIAS [6:0]
29 GoBIAS 80 RW Go Channel offset manual adjus tment value, effect only when COMG[3] = 1
GoBIAS[7] – offset direction: “0” = add GoBIAS [6:0]; “1” = subtract GoBIAS [6:0].
OV9620/OV9120 Datasheet Doc #DS102 © OmniVision Technologies Inc., 2002, version 2.0 Page 19 Sub- address (hex) Register Default (hex) Read/ Write Descriptions 2A COML 00 RW Common control L COML[7] – Line interval adjustment : “1” = enabled, “0” = disabled. Interval adjustment value in COM [6:5] and FRARL [7:0]. COML[6:5] – Line interval adjust value most significant 2 bits COML[4] – AGC preset initial value for auto gain control: “1” = enabled, “0” = disabled: Note: preset in register 00. COML[3:2] – HSYNC timing end point adjustment MSB 2 bits COML[1:0] – HSYNC timing start point adjustment MSB 2 bits 2B FRARL 00 RW Line interval adjustment value LSB 8 bits The frame rate will be adjusted by changing the line interval. Each LSB will add 2/1520 Tframe in SXGA mode and 2/800 Tframe in VGA mode to the frame period. 2C RBIAS 80 RW R Channel offset manual adjustm ent value, effective only when COMG[3] = 1 RBIAS[7] – offset direction: “0” = add RBIAS[6:0]; “1” = subtract RBIAS[6:0] 2D ADDVSL 00 RW VSYNC Pulse width LSB 8 bits ADDVSL[7:0] – line periods added to VSYNC width. Default VSYNC output width is 4 * tline. Each LSB count will add 1 * tline to the VSYNC active period. 2E ADDVSH 00 RW VSYNC Pulse width MSB 8 bits ADDVSH[7:0] – line periods added to VSYNC width. Default VSYNC output is 4 * tline. Each MSB count will add 256 * tline in VSYNC period 2F YAVG 00 RW Lumi nance average register This register will auto update when COMH [5] = 1; Average Luminance is calculated from R/Ge/Go/R channel average, it is equal to (Blue Avg [7:0] + GeAVG[7:0] + GoAVG[7:0] + RAVG[7:0])/4
30 HSDY 08 RW HSYNC position and width start point LSB 8 bits
This register and COML[1:0] define HSYNC start position, each LSB will shift HSYNC start point by 1 pixel period.
31 HEDY 30 RW HSYNC position and width end lower 8 bits
This register and COML[3:2] define HSYNC end position, each LSB will shift HSYNC end by 1 pixel period.
32 COMM 0A
(0F in VGA) RW Common control M COMM[7] – Pixel blanking period; “1” = set pixel blanking to 040 to each side of HREF. COMM[6] – Blank pixel value setting: “1” = set pixel blanking to 010 periods to each side of HREF. Default pixel blanking is 0 COMM[5] – Vertical window end position LSB COMM[4] – Vertical window start position LSB COMM[3:2] – Horizontal window end position LSBs COMM[1:0] – Horizontal window start position LSBs
33 CHLF 28 RW Current control
CHLF[7:6] – Sensor current control,”00”= minimum, “11”= maximum CHLF[5] – Sensor current range control: “0”= CHLF[7:6] current control at normal range, “1”= CHLF[7:6] current at half range CHLF[4] – Sensor Current double on/off: “0”= normal, “1”= double current CHLF[3] – Sensor buffer current control: “0”= normal, “1”= current half CHLF[2] – Column buffer current control: “0”= normal, “1”= current half CHLF[1] – Analog DSP current control: “0”= normal, “1”= current half CHLF[0] – ADC current control: “0”= normal, “1”= current half
34 VGAP 1B RW Reserved
35 VBLM 90 RW Reference voltage control
VBLM[7:5] – Column high reference control: “1xx”= column high reference connect to VDD, “000”= lowest voltage “011”= highest voltage VBLM[4:2] – Column low reference control: “1xx”= column low reference connect to GND, “000”= lowest “011”= highest VBLM[1:0] – Anti-blooming voltage control: “00”= lowest voltage, “11”= highest voltage, these 2 bits enabled/disabled by COME[6].
OV9620/OV9120 Datasheet Doc #DS102 © OmniVision Technologies Inc., 2002, version 2.0 Page 20 Sub- address (hex) Register Default (hex) Read/ Write Descriptions
36 VCHG 17 RW Sensor precharge voltage control
VCHG[7] – reserved VCHG[6:4] – Sensor precharge voltage control: “000”= lowest voltage “111”= highest voltage. VCHG[3:0] – Sensor array common reference control: “000”= lowest voltage “111”= highest voltage
37 ADC 04 RW ADC reference control
ADC[7:4] – reserved ADC[3] – ADC input signal range: “1”= input signal x0.7, “0”= input signal x1. ADC[2:0] – ADC range control. “000”= Minimum, “111”= Maximum.
38 ACOM 12 RW Analog Common Control
ACOM[7] – Analog gain control: “1”= Gain increase 1.5x, “0”= Normal ACOM[6] – Analog black level calibration control: “0”= Analog BLC on, “1”= Analog BLC off. ACOM[5:0] – reserved. ACOM[7] – Analog gain control: “1”= Gain increase 1.5x, “0”= Normal ACOM[6] – Analog black level calibration control: “0”= Analog BLC on, “1”= Analog BLC off. ACOM[5:0] – reserved.
Figure 23. OV9620/9120 Package Diagram
48 PLCS
4 CORNERS
0.002 TYP
0.006 MAX
0.036 MIN
Die shift (x,y)=0.15mm (6mils) max. Figure 24. OV9620/9120 Sensor array center location Picture is for reference only, not to scale. form, without the prior written consent of OmniVision Technologies, Inc. board with pin 1 (SVDD) down as shown.
OV9620/OV9120 Datasheet Doc #DS102 © OmniVision Technologies Inc., 2002, version 2.0 Page 23
Revision History
Effective Date Version Contents Issued By 01-04-02 1.0 Original Docum ent OVT Technical Writer 02-22-02 2.0 Reorganization of docum ent sections, standardization of terms, additional sub-sampling information and diagram, settling times added to AC Characteristics table, pin (39- 44) & register changes (04,0B,0D, 0E, 33, 35) to reflect removal of on-chip defect correction per Engineering. OVT Technical Writer