OV7640 ETC1 | Alldatasheet
Document overview
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Technical content
Features
- High sensitivity for low-light operation
- 2.5V operating voltage for embedded portable
applications
- Standard Serial Camera Control Bus (SCCB) interface
- VGA, QVGA (sub-sampled) and Windowed outputs with Raw RGB, RGB (GRB 4:2:2), YUV (4:2:2) and YCbCr (4:2:2) formats
- Automatic image control functions including: Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), Automatic Brightness Control (ABC), Automatic Band Filter (ABF) for 60Hz noise and Automatic Black-Level Calibration (ABLC)
- Image quality controls including color saturation, hue, gamma, sharpness (edge enhancement), anti-blooming and zero smearing
Ordering Information
OV7640 (Color) PLCC-28 OV7141 (B&W) PLCC-28
- Cellular and Picture Phones
- T o y s
- PC Multimedia Key Specifications Figure 1 OV7640/OV7141 Pin Diagram Array Size 640 x 480 (VGA) Power Supply Core 2.5VDC + 10% Analog 2.5VDC + 4% I/O 2.25V to 3.3V Power Requirements Active 40 mW (30 fps, including I/O power) Standby 30 μW Temperature Range Operation -10°C to 70°C Stable Image 0°C to 50°C Output Formats (8-bit)
- YUV/YCbCr 4:2:2
- RGB 4:2:2
- R a w R G B D a t a Lens Size 1/4" Maximum Image Transfer Rate VGA 30 fps QVGA 60 fps Sensitivity B&W 3.0 V/Lux-sec Color 1.12 V/Lux-sec S/N Ratio 46 dB Dynamic Range 62 dB Scan Mode Progressive/Interlaced Maximum Exposure Interval 523 x tROW Gamma Correction 0.45 Pixel Size 5.6 μm x 5.6 μm Dark Current 30 mV/s Well Capacity 60 Ke Fixed Pattern Noise < 0.03% of VPEAK-TO-PEAK Image Area 3.6 mm x 2.7 mm Package Dimensions 11.43 mm x 11.43 mm 25 Y0 24 Y1 23 Y2 22 Y3 21 Y4 20 Y5 19 Y6
27 SIO_D
26 SIO_C
1 VSS_A
2 VDD_A
12VDD_IO 13CLK 14NC 15RESET 16NC 17VSS_D 18Y7 5PWDN 6NC 7VREF 8VDD_C 9VSYNC 10HREF 11PCLK OV7640/OV7141
4 Proprietary to OmniVision Technologies Version 1.4, March 6, 2003 OV7640/OV7141 CMOS VGA (640 x 480) CAMERACHIP™ Omni ision Pin Description Table 1 Pin Description Pin Number Name Pin Type Function/Description
01 VSS_A Ground Analog ground
02 VDD_A V DD Analog VDD
03 NC — No connection
04 NC — No connection
05 PWDN Input Sets device to power down standby mode
06 NC — No connection
07 VREF V
REF Internal voltage reference (2.3V). Connect to ground through 1μF capacitor
08 VDD_C V DD Core VDD
09 VSYNC Output Vertical sync output
10 HREF Output HREF output
11 PCLK Output Pixel clock output
12 VDD_IO V DD I/O VDD
13 CLK Input External clock
14 NC — No connection
15 RESET Input Clears all registers and resets them to their default values.
16 NC — No connection
17 VSS_D Ground Digital ground
18 Y7 Output Digital video output bit[7]
19 Y6 Output Digital video output bit[6]
20 Y5 Output Digital video output bit[5]
21 Y4 Output Digital video output bit[4]
22 Y3 Output Digital video output bit[3]
23 Y2 Output Digital video output bit[2]
24 Y1 Output Digital video output bit[1]
25 Y0 Output Digital video output bit[0]
26 SIO_C Input SCCB serial interface clock
27 SIO_D I/O SCCB serial interface data I/O
28 NC — No connection
Electrical Characteristics
Version 1.4, March 6, 2003 Proprietary to OmniVision Technologies 5 Omni ision NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage. Table 2 Absolute Maximum Ratings Ambient Storage Temperature -40ºC to +125ºC Supply Voltages (with respect to Ground) VDD-A 3V VDD-C 3V VDD-IO 4V All Input/Output Voltages (with respect to Ground) -0.3V to VDD_IO+1V Lead Temperature, Surface-mount process +230ºC ESD Rating, Human Body model 2000V Table 3 DC Characteristics (0°C < T A < 70°C) Symbol Parameter Condition Min Typ Max Unit VDD-A DC supply voltage – Analog — 2.40 2.5 2.60 V VDD-C DC supply voltage – Core — 2.25 2.5 2.75 V VDD-IO DC supply voltage – I/O — 2.25 — 3.3 V IDDA Active (Operating) Current See Note a a. V DD-A = VDD-C = 2.5V, VDD-IO = 3.0V IDDA = ¦{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps, no I/O loading 15 mA IDDS-SCCB Standby Current See Note b b. V DD-A = VDD-C = 2.5V, VDD-IO = 3.0V IDDS:SCCB refers to a SCCB-initiated Standby, while IDDS:PWDN refers to a PWDN pin-initiated Standby 1m A IDDS-PWDN Standby Current 10 μA VIH Input voltage HIGH CMOS 0.7 x V DD-IO V VIL Input voltage LOW 0.3 x V DD-IO V VOH Output voltage HIGH CMOS (IOH / IOL) 0.9 x VDD-IO V VOL Output voltage LOW 0.1 x V DD-IO V IOH Output current HIGH See Note c c. Standard Output Loading = 25pF, 1.2K : to 3V 8m A IOL Output current LOW 15 mA IL Input/Output Leakage GND to V DD-IO ± 1 μA
6 Proprietary to OmniVision Technologies Version 1.4, March 6, 2003 OV7640/OV7141 CMOS VGA (640 x 480) CAMERACHIP™ Omni ision Table 4 Functional and AC Characteristics (0°C < TA < 70°C) Symbol Parameter Min Typ Max Unit Functional Characteristics A/D Differential Non-Linearity + 1/2 LSB A/D Integral Non-Linearity + 1L S B AGC Range 21 dB Red/Blue Adjustment Range 12 dB Inputs (PWDN, CLK, RESET) fCLK Input Clock Frequency 10 24 27 MHz tCLK Input Clock Period 100 42 37 ns tCLK:DC Clock Duty Cycle 45 50 55 % tS:RESET Setting time after software/hardware reset 1 ms tS:REG Settling time for register change (10 frames required) 300 ms SCCB (SIO_C and SIO_D - see Figure 4) fSIO_C Clock Frequency 400 KHz tLOW Clock Low Period 1.3 μs tHIGH Clock High Period 600 ns tAA SIO_C low to Data Out valid 100 900 ns tBUF Bus free time before new START 1.3 μs tHD:STA START condition Hold time 600 ns tSU:STA START condition Setup time 600 ns tHD:DAT Data-in Hold time 0 μs tSU:DAT Data-in Setup time 100 ns tSU:STO STOP condition Setup time 600 ns tR, tF SCCB Rise/Fall times 300 ns tDH Data-out Hold time 50 ns Outputs (VSYNC, HREF, PCLK, and Y[7:0] - see Figure 5, Figure 6, and Figure 7) tPDV PCLK[p] to Data-out Valid 5 ns tSU Y[7:0] Setup time 15 ns tHD Y[7:0] Hold time 8 ns tPHH PCLK[p] to HREF[n]0 5 n s tPHL PCLK[p] to HREF[p]0 5 n s AC Conditions: xVDD: VDD-A = VDD-C = 2.5V, VDD-IO = 3.3V xRise/Fall Times: I/O: 5ns, Maximum SCCB: 300ns, Maximum xInput Capacitance: 10pf xOutput Loading: 25pF, 1.2K: to 3V xfCLK: 24MHz
10 Proprietary to OmniVision Technologies Version 1.4, March 6, 2003 OV7640/OV7141 CMOS VGA (640 x 480) CAMERACHIP™ Omni ision Register Set Table 5 provides a list and description of the Device Control registers contained in the OV7640/OV7141. For all register Enable/Disable bits, ENABLE=1 and DISABLE=0. The device slave addresses for the OV7640/OV7141 are 42 for write and 43 for read. Table 5 SCCB Register List Address (Hex) Register Name Default (Hex) R/W Description
00 GAIN 00 RW AGC – Gain control gain setting
- Range: [00] to [FF]
01 BLUE 80 RW
AWB – Blue channel gain setting
- Range: [00] to [FF] Note: This function is not available on the B&W OV7141.
02 RED 80 RW
AWB – Red channel gain setting
- Range: [00] to [FF] Note: This function is not available on the B&W OV7141.
03 SAT 84 RW
Image Format – Color saturation value Bit[7:4]: Saturation value
- Range: [0] to [F] Bit[3:0]: Reserved Note: This function is not available on the B&W OV7141.
04 HUE 34 RW
Image Format – Color hue control Bit[7:6]: Reserved Bit[5]: Hue Enable Bit[4:0]: Hue setting Note: This function is not available on the B&W OV7141.
05 CWF 3E RW
AWB – Red/Blue Pre-Amplifier gain setting Bit[7:4]: Red channel pre-amplifier gain setting
- Range: [0] to [F] Bit[3:0]: Blue channel pre-amplifier gain setting
- Range: [0] to [F] Note: This function is not available on the B&W OV7141.
06 BRT 80 RW ABC – Brightness setting
- Range: [00] to [FF] 07-09 RSVD XX – Reserved 0A PID 76 R Product ID number (Read only) 0B VER 48 R Product version number (Read only) 0C-0F RSVD XX – Reserved
10 AECH 41 RW Exposure Value
Version 1.4, March 6, 2003 Proprietary to OmniVision Technologies 11 Omni ision
11 CLKRC 00 RW
Data Format and Internal Clock Bit[7:6]: Data Format – HSYNC/VSYNC Polarity 00: HSYNC = NEG VSYNC = POS 01: HSYNC = NEG VSYNC = NEG 10: HSYNC = POS VSYNC = POS 11: HSYNC = POS VSYNC = POS Bit[5:0]: Internal Clock Pre-Scalar
- Range: [0 0000] to [F FFFF]
12 COMA 14 RW
Bit[7]: SCCB – Register Reset 0: No change 1: Reset all registers to default values Bit[6]: Output Format – Mirror Image Enable Bit[5]: Reserved Bit[4]: Data Format – YUV formatting 0: Y U Y V Y U Y V 1: U Y V Y U Y V Y (default) Bit[3]: Output Format – Output Channel Select A 0: YUV/YCbCr 1: RGB/Raw RGB Bit[2]: AWB – Enable Bit[1:0]: Reserved Note: This function is not available on the B&W OV7141.
13 COMB A3 RW
Bit[7:5]: Reserved Bit[4]: Data Format – ITU-656 Format Enable Bit[3]: Reserved Bit[2]: SCCB – Tri-State Enable – Y[7:0] Bit[1]: AGC – Enable Bit[0]: AEC – Enable Table 5 SCCB Register List Address (Hex) Register Name Default (Hex) R/W Description POS NEG
12 Proprietary to OmniVision Technologies Version 1.4, March 6, 2003 OV7640/OV7141 CMOS VGA (640 x 480) CAMERACHIP™ Omni ision
14 COMC 04 RW
Bit[7:6]: Reserved Bit[5]: Output Format – Resolution 0: VGA (640x480) 1: QVGA (320x240) Bit[4]: Reserved Bit[3]: Data Format – HREF Polarity 0: HREF Positive 1: HREF Negative Bit[2:0]: Reserved
15 COMD 00 RW
Bit[7]: Data Format – Output Flag Bit Disable 0: Frame = 254 data bits (00/FF = Reserved flag bits) 1: Frame = 256 data bits Bit[6]: Data Format – Y[7:0]-PCLK Reference Edge 0: Y[7:0] data out on PCLK falling edge 1: Y[7:0] data out on PCLK rising edge Bit[5:1]: Reserved Bit[0]: Data Format – UV Sequence Exchange 0: V Y U Y V Y U Y 1: U Y V Y U Y V Y Note: Bit[0] is not programmable on the B&W OV7141.
16 RSVD XX – Reserved
17 HSTART 1A RW Output Format – Horizontal Frame (HREF Column) Start
18 HSTOP BA RW Output Format – Horiz ontal Frame (HREF Column) Stop
19 VSTRT 03 RW Output Format – Vertical Frame (Row) Start
1A VSTOP F3 RW Output Format – Vertical Frame (Row) Stop 1B PSHFT 00 RW Data Format – Pixel Delay Select (Delays timing of the Y[7:0] data relative to HREF in pixel units)
- Range: [00] (No delay) to [FF] (256 pixel delay) 1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F) 1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2) 1E RSVD XX – Reserved Table 5 SCCB Register List Address (Hex) Register Name Default (Hex) R/W Description POS NEG
Version 1.4, March 6, 2003 Proprietary to OmniVision Technologies 13 Omni ision 1F FACT 01 RW Output Format – Format Control Bit[7:5]: Reserved Bit[4]: Output Format – RGB:565 Enable Note: Bit[4] is not programmable on the B&W OV7141. Bit[3]: Reserved Bit[2]: Output Format – RGB:555 Enable Note: Bit[2] is not programmable on the B&W OV7141. Bit[1:0]: Reserved
20 COME C0 RW
Bit[7]: Reserved Bit[6]: AEC – Digital Averaging Enable Bit[5]: Reserved Bit[4]: Image Quality – Edge Enhancement Enable Bit[3:1]: Reserved Bit[0]: Y[7:0] 2X I OL / IOH Enable 21-23 RSVD XX – Reserved
24 AEW 10 RW AGC/AEC – Stable Operating Region – Upper Limit
25 AEB 8A RW AGC/AEC – Stable Operating Region – Lower Limit
26 COMF A2 RW
Bit[7:3]: Reserved Bit[2]: Data Format – Output Data MSB/LSB Swap Enable (LSB o MSB (Y[7]) and MSB o LSB (Y[0]) Bit[1:0]: Reserved
27 COMG E2 RW
Bit[7:5]: Reserved Bit[4]: Color Matrix – RGB Crosstalk Compensation Enable (Used to increase each color filter’s efficiency) Note: Bit[4] is not programmable on the B&W OV7141. Bit[3:2]: Reserved Bit[1]: Data Format – Output Full Range Enable 0: Output Range = [10] to [F0] (224 bits) 1: Output Range = [01] to [FE] (254/256 bits) Bit[0]: Reserved
28 COMH 20 RW
Bit[7]: Output Format – RGB Output Select 0: RGB 1: Raw RGB Bit[6]: Device Select 0: OV7640 1: OV7141 Bit[5]: Output Format – Scan Select 0: Interlaced 1: Progressive Bit[4:0]: Reserved Table 5 SCCB Register List Address (Hex) Register Name Default (Hex) R/W Description
14 Proprietary to OmniVision Technologies Version 1.4, March 6, 2003 OV7640/OV7141 CMOS VGA (640 x 480) CAMERACHIP™ Omni ision
29 COMI 00 R
Bit[7:2]: Reserved Bit[1:0]: Device Version (Read-only) 2A FRARH 00 RW Output Format – Frame Rate Adjust High Bit[7]: Data Format – Frame Rate Adjust Enable Bit[6:5]: Data Format – Frame Rate Adjust Setting MSB FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0] Bit[4]: A/D – UV Channel ‘2 Pixel Delay’ Enable Note: Bit[4] is not programmable on the B&W OV7141. Bit[3:0]: Reserved 2B FRARL 00 RW Data Format – Frame Rate Adjust Setting LSB FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0] 2C RSVD XX – Reserved 2D COMJ 81 RW Common Control J Bit[7:3]: Reserved Bit[2]: AEC – Band Filter Enable Bit[1:0]: Reserved 2E-5F RSVD XX – Reserved
60 SPCB 06 RW
Bit[7]: AGC – 1.5x Multiplier (Pre-amplifier) Enable Bit[6:0]: Reserved 61-6B RSVD XX – Reserved 6C RMCO 11 RW Color Matrix – RGB Crosstalk Compensation – R Channel Note: This function is not available on the B&W OV7141. 6D GMCO 01 RW Color Matrix – RGB Crosstalk Compensation – G Channel Note: This function is not available on the B&W OV7141. 6E BMCO 06 RW Color Matrix – RGB Crosstalk Compensation– B Channel Note: This function is not available on the B&W OV7141. 6F-70 RSVD XX – Reserved
71 COML 00 RW
Bit[7]: Reserved Bit[6]: Data Format – PCLK output gated by HREF Enable Bit[5]: Data Format – Output HSYNC on HREF Pin Enable Bit[4]: Reserved Bit[3:2]: Data Format – HSYNC Rising Edge Delay MSB Bit[1:0]: Data Format – HSYNC Falling Edge Delay MSB
72 HSDYR 10 RW
Data Format – HSYNC Rising Edge Delay LSB HSYNCR[9:0] = MSB + LSB = COML[3:2] + HSDYR[7:0]
- Range 000 to 762 pixel delays Table 5 SCCB Register List Address (Hex) Register Name Default (Hex) R/W Description
Version 1.4, March 6, 2003 Proprietary to OmniVision Technologies 15 Omni ision
73 HSDYF 50 RW
Data Format – HSYNC Falling Edge Delay LSB HSYNCF[9:0] = MSB + LSB = COML[1:0] + HSDYF[7:0]
- Range 000 to 762 pixel delays
74 COMM 20 RW
Bit[7]: Reserved Bit[6:5]: AGC – Maximum Gain Select 00: +6 dB 01: +12 dB 10: +6 dB 11: +18 dB Bit[4:0]: Reserved
75 COMN 02 RW
Bit[7]: Output Format – Vertical Flip Enable Bit[6:0]: Reserved
76 COMO 00 RW
Bit[7:6]: Reserved Bit[5]: Standby Mode Enable Bit[4:3]: Reserved Bit[2]: SCCB – Tri-State Enable – VSYNC, HREF and PCLK Bit[1:0]: Reserved 77-7D RSVD XX – Reserved 7E AVGY 00 RW AEC – Digital Y/G Channel Average (Automatically updated by AGC/AEC, user can only read the values) 7F AVGR 00 RW AEC – Digital R/V Channel Average (Automatically updated by AGC/AEC, user can only read the values) Note: This function is not available on the B&W OV7141.
80 AVGB 00 RW
AEC – Digital B/U Channel Average (Automatically updated by AGC/AEC, user can only read the values) Note: This function is not available on the B&W OV7141. NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings. Table 5 SCCB Register List Address (Hex) Register Name Default (Hex) R/W Description
16 Proprietary to OmniVision Technologies Version 1.4, March 6, 2003 OV7640/OV7141 CMOS VGA (640 x 480) CAMERACHIP™ Omni ision Package Specifications The OV7640/OV7141 uses a 28-pin plastic package. Refer to Figure 10 for package information, Table 6 for package dimensions, and Figure 11 for the array center on the chip. Figure 10 OV7640OV7141 Plastic Package Specifications Table 6 OV7640/OV7141 Pla stic Package Dimensions Dimensions Millimeters (mm) Inches (in.) Package Size 11.43 + 0.10 SQ .450 + .004 SQ Package Height 2.35 + 0.1 .093 + .004 Substrate Height 0.70 + 0.05 .028 + .002 Cavity Size 7.00 + 0.10 SQ .275 + .004 SQ Castellation Height 1.07 + 0.05 .042 + .002 Pin #1 Pad Size 0.64 x 2.16 .025 x .085 Pad Size 0.64 x 1.27 .025 x .050 Pad Pitch 1.27 + 0.10 .050 + .004 Package Edge to First Lead Center 1.90 + 0.10 .075 + .004 End-to-End Pad Center-Center 7.62 + 0.10 .300 + .004 Glass Size 10.30 + 0.10 SQ .406 + .004 SQ Glass Height 0.55 + 0.05 .022 + .002 .042 ± .002 .028 ± .002 .050 ± .004 1925 .035 MIN. .025 ± .003 TYP 4 5 .075 ± .004 .093 ± .004 .022 ± .002 .001 to .005 TYP Pin 1 Index .300 ± .004 .050 TYP .085 TYP .009 R REF TYP .406 ± .004 .028 ± .002 (Metallized) o Chamfer Pin 1 Index 1 1 2221 2519 .275 SQ ± .004 .350 SQ ± .006 .450 SQ ± .004 .012 x 45 o .010 x 45
Version 1.4, March 6, 2003 Proprietary to OmniVision Technologies 17 Omni ision Sensor Array Center Figure 11 OV7640/OV7141 Sensor Array Center OV7640/OV7141 Die Image Array Die Y-Centerline Die X-Centerline Array Center (0.2273, 0.1222) Pin 1 3.6512 mm 2.7328 mm NOTES: Due to the lens inversion, in order for the image to be right-side up, the OV7640/OV7140 must be mounted Pin 1 down. Picture is for reference only, not to scale. Die shift (x,y) = 0.15 mm (6 mils) max. Die tilt = 1 degrees max. Die rotation = 3 degrees max. Positional T olerances
18 Proprietary to OmniVision Technologies Version 1.4, March 6, 2003 OV7640/OV7141 CMOS VGA (640 x 480) CAMERACHIP™ Omni ision IR Reflow Ramp Rate Requirements Figure 12 IR Reflow Ramp Rate Requirements Note: All temperatures = ± 10 oC All times show the fastest allowable ramp rate 60S 25oC 120S 180S 240S Ramp Rate: 50o/minute Ramp Rate: 10o/minute Typical Dwell Time = 10Sec Maximum Dwell Time > 215o = 30Sec 150oC 140oC 130oC 160oC 200oC 190oC 180oC 170oC 210oC 220oC 230oC
Version 1.4, March 6, 2003 Proprietary to OmniVision Technologies 19 Omni ision Note:
- All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation.
- OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders).
- Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced.
- This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein.
- ‘OmniVision’, ‘CameraChip’ are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners. For further information, please feel free to contact OmniVision at info@ovt.com OmniVision Technologies, Inc. Sunnyvale, CA USA (408) 733-3030
20 Proprietary to OmniVision Technologies Version 1.4, March 6, 2003 OV7640/OV7141 CMOS VGA (640 x 480) CAMERACHIP™ Omni ision