OV6620 ETC | Alldatasheet
Document overview
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Technical content
Features
n 101,376 pixels, 1/4” lens, CIF/QCIF format n Progressive scan read out n Data format - YCrCb 4:2:2, GRB 4:2:2, RGB Raw Data n 8/16 bit video data: CCIR601, CCIR656, ZV port n Wide dynamic range, anti-blooming, zero smearing n Electronic exposure / Gain / white balance control n Image enhancement - brightness, contrast, gamma, saturation, sharpness, window, etc. n Internal/external synchronization n Frame exposure/line exposure option n 5-Volt operation, low power dissipation –< 80 mW active power –< 10 µA in power-save mode n Gamma correction (0.45/0.55/1.00) n I2 C programmable (400 kb/s): – color saturation, brightness, contrast, white balance, exposure time, gain
Table 1. Pin Description
01 SVDD V in Array power (+5VDC)
02 RESET Function
03 AGCEN Function
04 FREX Function
05 VRCAP2 V ref (2.5V) Array reference. Connect to ground through 0.1 uF capacitor.
06 ASUB V in Analog substrate voltage
07 AGND V in Analog ground
08 AVDD V in Analog power supply (+5VDC)
09 PWDN Function
10 VrCAP1 N/C Internal voltage reference. Connect to ground through 0.1 µF capacitor. 11 VrCAP3 Internal voltage reference. Connect to ground through 1 µF capacitor.
12 IICB Function
13 VTO O Luminance Composite Signal Output
14 ADVDD V in Analog power supply (+5VDC)
15 ADGND V in Analog signal ground
16 VSYNC/CSYS I/O Vertical sync output. At power up, read as CSYS.
17 FODD/CLK I/O Field ID FODD output or main clock output
19 UV7/B8 I/O Bit 7 of U video component output. At power up, sampled as B8. 20 UV6/ABKEN I/O Bit 6 of U video component output. At power up, sampled as ABKEN. 21 UV5/MIR I/O Bit 5 of U video component output. At power up, sampled as MIR. 22 UV4 I/O Bit 4of U video component output. 23 UV3 I/O Bit 3 of U video component output. O M N IV I S IO N T E C H N O L O G I E S , Inc.
O M N IV I S IO N T E C H N O L O G I E S , Inc. 24 UV2/QCIF I/O Bit 2 of U video component output. At power up, sampled as QCIF. 25 UV1/CC656 I/O Bit 1 of U video component output. At power up, sampled as CC656. 26 UV0/GAMMA I/O Bit 0 of U video component output. At power up, sampled as GAMMA.
27 XCLK1 I Crystal clock input
28 XCLK2 O Crystal clock output
29 DVDD V in Digital power supply (+5VDC)
30 DGND V in Digital ground
31 DOGND V in Digital interface output buffer ground
32 DOVDD V in Digital interface output buffer power supply (+5VDC)
33 PCLK/PWDB I/O PCLK output. At power up sampled as PWDB. 34 Y7/CS0 I/O Bit 7 of Y video component output. At power up, sampled as CS0. 35 Y6/CS2 I/O Bit 6 of Y video component output. At power up, sampled as CS2. 36 Y5/SHARP I/O Bit 5 of Y video component. At power up, sampled as SHARP. 38 Y3/RGB I/O Bit 3 of Y video component output. At power up, sampled as RGB. 39 Y2/G2X I/O Bit 2 of Y video component output. At power up, sampled as G2X. 40 Y1 I/O Bit 1 of Y video component output. 41 Y0/CBAR I/O Bit 0 of Y video component output. At power up, sampled as CBAR. 42 CHSYNC/BW I/O CHSYNC output. At power up, sampled as BW. 43 DEGND V in Decoder ground.
44 DEVDD V in Decoder power supply (+5VDC)
45 SCL I I2 C serial interface clock input
46 SDA I/O I2 C serial interface data input and output.
47 MULT Function
48 SGND V in Array ground
O M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 1. OV6620/OV6120 CMOS Image Sensor Block Diagram
1.1 Overview
ray arranged in line-alternating fashion.
14 May 1999 Version 1.11 5 OV6620/OV6120 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary
1.2 Analog Processor Circuits
1.2.1 Overview
The image is captured by the 356 x 592 pixel image ar- ray and routed to the analog processing section where the majority of signal processing occurs. This block con- tains the circuitry which performs color separation, ma- trixing, Automatic Gain Control (AGC), gamma correction, color correction, color balance, black level calibration, “knee” smoothing, aperture correction, and controls for picture luminance, chrominance, and anti- alias filtering. The analog video signals are based on the following formula: Y = 0.59G + 0.31R + 0.11B U = R-Y V = B-Y where R,G,B are the equivalent color components in each pixel. A YCrCb format is also supported, based on the formula below: Y = 0.59G + 0.31R + 0.11B Cr = 0.713 x (R - Y) Cb = 0.564 x (B - Y) The YCrCb/RGB Raw Data signal from the analog pro- cessing section is fed to two on-chip 8-bit Analog-to- Digital (A-to-D) converters: one for the Y/RG channel and one shared by the CrCb/BG channels. The A-to-D converted data stream is further conditioned in the digi- tal formatter. The processed signal is delivered to the digital video port through the video multiplexer which routes the user-selected 16-, 8-, or 4-bit video data the correct output pins. The on-chip 8-bit A-to-D converters operate at up to 9 MHz, fully synchronous to the pixel rate. Actual conver- sion rate is set as a function of the frame rate. A-to-D black-level calibration circuitry ensures the following: –the black level of Y/RGB is normalized to a value of 16 –the peak white level is limited to 240 –CrCb black level is 128 –Peak/Bottom is 240/16 –RGB raw data output range is 16/240 (Note: Values 0 and 255 are reserved for sync flag)
1.2.2 Image Processing
The algorithm used for the electronic exposure control is based on the brightness of the full image. The expo- sure is optimized for a “normal” scene which assumes the subject is well lit relative to the background. In situ- ations where the image is not well lit, the Automatic Ex- posure Control (AEC) White/Black ratio may be adjusted to suit the needs of the application. Additional on-chip functions include Automatic Gain Control (AGC) which provides a gain boost of up to 24dB. White balance control enables setting of proper color temperature and can be programmed for automat- ic or manual operation. Separate saturation, brightness, contrast, and sharpness adjustments allow for further fine tuning of the picture quality and characteristics. The OV6620 image sensor also provides control over the White Balance ratio for increasing/decreasing the im- age field Red/Blue component ratio. The sensor pro- vides a default setting which may be sufficient for many applications.
1.2.3 Windowing
The windowing feature of the OV6620/OV6120 image sensors allows user-definable window sizing as re- quired by the application. Window size setting (in pixels) ranges from 2 x 2 to 356 x 292, and can be positioned anywhere inside the 356 x 292 boundary. Note that modifying window size and/or position does not change frame or data rate. The OV6620/OV6120 imager alters the assertion of the HREF signal to be consistent with the programmed horizontal and vertical region. The de- fault output window is 352 x 288.
1.2.4 Zoom Video Port (ZV)
The OV6620/OV6120 image sensor includes a Zoom Video (ZV) function that supports standard ZV Port in- terface timing. Signals available include VSYNC, CHSYNC, PCLK and 16-bit data bus: Y[7:0] and UV[7:0]. The rising edge of PCLK clocks data into the ZV port. See Figure 2, Zoom Video Port Timing below.
O M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 2. Zoom Video Port Timing
- Zoom Video Port format output signal includes:
HREF: Horizontal valid data output window. 17.73MHz as system clock. Rising edge of PCLK is used to clock the 16 Bit data. Y[7:0]: 8 Bit luminance data bus. UV[7:0]: 8 Bit chrominance data bus.
- All timing parameters are provided in Table 13. Zoom Video Port AC Parameters
1 LineT vs T ve
O M N IV I S IO N T E C H N O L O G I E S , Inc.
1.2.5 QCIF Format
- QCIF Digital Output Format (YUV, beginning of line)
ta, Beginning of Line) for further information.
1.2.6 Video Output
options to suit many different application requirements. Table 2. Digital Output Formats, below, indicates the Table 4. 4:2:2 8 -b it Format below) the OV6620 Color Filter Pattern (See Section Figure 4. equivalent to operating in 16-bit mode.
- Y0 default sequence sets Y7 as MSB and Y0 as LSB.
O M N IV I S IO N T E C H N O L O G I E S , Inc.
- When in RGB CCIR656 format, output is 8 bits. SAV and EAV are inserted at the beginning and ending of
(without VSYNC and CHSYNC) may be used.
- In RGB format, U/V swap means neighbor row B R output sequence swap. Refer to
Table 2. Digital Output Formats
O M N IV I S IO N T E C H N O L O G I E S , Inc. Table 3. 4:2:2 16-bit Format Table 4. 4:2:2 8 -b it Format
O M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 3. Pixel Data Bus (YUV Output)
O M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 4. Pixel Data Bus (RGB Output)
10 G G 10
O M N IV I S IO N T E C H N O L O G I E S , Inc. Y channel output Y2 Y3 Y6 Y7 Y10 Y11 ... –UV channel output U2 V3 U6 V7 U10 V11 ... Table 5. Default Output Sequence Table 6. Swapped MSB/LSB Output Sequence Table 7. QCIF Digital Output Format (YUV, beginning of line) Table 8. QCIF Digital Output Format (RGB Raw Data, Beginning of Line)
- Default RGB two line output mode:
–Y channel output G0 R1 G4 R5 G8 R9 ... –UV channel output B0 G1 B4 G5 B8 G9 ... line(144 line) data in one frame will be output. –Y channel output G0 R1 G4 R5 G8 R9 ... –UV channel output B0 G1 B4 G5 B8 G9 ... (144 line) data in one frame will be output.
- QCIF Resolution Digital Output Format
–Y channel output Y2 Y3 Y6 Y7 Y10 Y11 ... –UV channel output U2 V3 U6 V7 U10 V11 ... 144 line) in one frame will be output.
O M N IV I S IO N T E C H N O L O G I E S , Inc. –1st HREF Y channel output unstable data, UV output B 11 G 12 B 13 G 14 .... –Every line of data is output twice. –1st HREF Y and UV output unstable data. –Every line data output twice. –1st HREF Y channel output unstable data. –2nd HREF Y channel output B11 G21 R22 G12 ... –3rd HREF Y channel output B31 G21 R22 G32 ..., etc. –PCLK timing is double and PCLK rising edge latch data bus. UV channel tri-state. Every line data output twice. –Uses higher 4 bits of Y port (Y[7:4]) as output port. –Supports YCrCb/RGB data, CCIR601/CCIR656 timing, Color/B&W. data. In color mode, sensor must be set to 8-bit mode, and the nibble timing, clock divided by 2. –Output sequence: U0h U0l Y0h Y0l V0h V0l Y1h Y1l ... Table 9. RGB Raw Data Format
1 B 11 G 12 B 13 G 14 B G B G
2 G 21 R 22 G 23 R 24 G R G R
3 B 31 G 32 B 33 G 34 B G B G
4 G 41 R 42 G 43 R 44 G R G R
5 B 51 G 52 B 53 G 54 B G B G
289 B G B G B G B G
290 G R G R G R G R
291 B G B G B G B G
292 G R G R G R G R
14 Version 1.11 14 May 1999 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary
1.2.7 Slave Mode Operation
The OV6620/OV6120 sensors can be programmable to operate in slave mode configuration (COMI[6] = 1, de- fault is master mode). HSYNC and VSYNC output sig- nals are provided. When used as a slave device, the external master must provide the OV6620/OV6120 imager with the following: 1. System clock CLK to XCLK1 pin; 2. Horizontal sync, Hsync, to CHSYNC pin, positive assertion; 3. Vertical frame sync, Vsync, to VSYNC pin, positive assertion When in slave mode, the OV6620/OV6120 tri-states CHSYNC (pin 42) and VSYNC (pin 16) output pins, which may then be used as input pins. To synchronize multiple devices, the OV6620/OV6120 image sensors use external system clock, CLK, to synchronize external horizontal sync, HSYNC, which is then used to synchro- nize external vertical frame sync, Vsync. See Figure 5, Slave Mode External Sync Timing for timing consider- ations.
1.2.8 Frame Exposure Mode
The OV6620/OV6120 sensors support frame exposure mode when programmed for Progressive Scan. FREX (pin 4) is asserted by an external master device to set exposure time. When FREX = 1, the OV6620/OV6120 pixel array will be quickly precharged. Based on the ex- ternal master’s assertion of FREX, the OV6620/OV6120 devices capture the image. When the master de-asserts FREX (FREX = 0), the video output data stream is deliv- ered to the OV6620/OV6120 output port in a line-by-line manner. It should be noted that FREX must active long enough to ensure the complete image array has been pre- charged. When data is being output from the OV6620/OV6120 image sensor, care must be taken so as not to expose the image array to light. This may affect the integrity of the image data captured. A mechanical shutter synchro- nized with the frame exposure rate can be used to min- imize this situation. Frame exposure mode timing is shown in Section Figure 6. Frame Exposure Timing be- low.
1.2.9 Reset
The OV6620/OV6120 image sensor includes a RESET pin (pin 2) which forces a complete hardware reset when pulled high (Vcc). When a hardware reset occurs, the OV6620/OV6120 sensor clears all registers or sets them to their default values. Reset may also be initiated through the I 2 C interface.
1.2.10 Power Down Mode
Two methods are available for placing the OV6620/ OV6120 devices into power-down mode: hardware pow- er down and I 2 C/software power down. To initiate hardware power down the PWDN pin (pin 9) must be tied to high (+5VDC). When this occurs, the OV6620/OV6120 internal device clock is halted and all internal registers (except I 2 C registers) are reset. In this mode, current draw is less than 10uA. Executing a software power down through the I 2 C inter- face suspends internal circuit activity, but does halt the device clock. In this mode, current requirements drop to less than 1mA.
1.2.11 Configuring the OV6620/OV6120 Image
Two methods are provided for configuring the OV6620/ OV6120 IC for specific application requirements. At power up, the OV6620/OV6120 sensor reads the sta- tus of certain pins to determine what, if any, power up default settings are requested. Once the reading of the external pins is completed, the device configures its in- ternal registers according to the specified pins. Not all device functions are available for configuration through external pin. A more flexible and comprehensive method for configur- ing the OV6620/OV6120 IC is to use its on-chip I 2 C reg- ister programming capability. The I 2 C interface provides access to all of the device’s programmable internal reg- isters. See Section 3.1 I2 C Bus Protocol Format for fur- ther details about using the I 2 C interface on the OV6620/OV6120 camera device.
O M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 5. Slave Mode External Sync Timing
- Vsync period is 625 * 472 * CLK
- OV6620 will be stable after 1 frame. (2nd Vsync).
O M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 6. Frame Exposure Timing
1 Frame (292 line)
T ex is array exposure time which is decided by external master device. T set = T in + T pr + T ex . T set > T pr + T in . Because T in is uncertain, so exposure time setting resolution is T hs (one line).
14 May 1999 Version 1.11 17 OV6620/OV6120 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary
O M N IV I S IO N T E C H N O L O G I E S , Inc.
- Electrical Characteristics
Table 10. DC Characteristics ( 0 o C < TA < 85 o C, Voltages referenced to GND)
O M N IV I S IO N T E C H N O L O G I E S , Inc. Table 11. AC Characteristics (T A =25 o C; Vdd=5V) Table 12. Timing Characteristics
O M N IV I S IO N T E C H N O L O G I E S , Inc.
- In Interlaced Mode, there are Even/Odd field different (t8). When In Progressive Scan Mode, only frame timing same as
- After VSYNC falling edge, OV6620 will output black reference level, the line number is T vs , which is the line number be-
- When in default setting, T vs = 14 * T line , which is changed with register VS[7:0]. VS[7:0] step equal to 1 line.
- When in default setting, T ve = 4 * T line for Odd Field, T ve = 3 * T line for Even Field, which is changed with register VE[7:0].
VE[7:0] step equal to 1 line. Table 13. Zoom Video Port AC Parameters
14 May 1999 Version 1.11 21 OV6620/OV6120 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary 18 7 +0.0100.060 -0.005 TYP. 0.040 ±0.007 TYP. 0.440 ±0.005 0.040 ±0.003 0.085 ±0.010 0.020 ±0.003 TYP. R 0.0075
48 PLCS
R 0.0075
4 CORNERS
0.003 0.002 0.020 ±0.002 0.015 ±0.002 0.030 0.003 0.065 ±0.007 ±0.003 Bottom View Top View Side View 6 19 0.006 MAX. 0.002 TYP. 0.350 SQ. ±0.005 0.430 SQ. ±0.005 0.560 SQ. -0.005 +0.012 0 . 0 3 6 M IN .
O M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 7. OV6620/OV6120 Package Outline Table 14. Ordering Information form, without the prior written consent of OmniVision Technologies, Inc.
O M N IV I S IO N T E C H N O L O G I E S , Inc. 7-bit address/data transfer protocol . Figure 8. I 2 C Bus Protocol Format
O M N IV I S IO N T E C H N O L O G I E S , Inc.
3.1 I2 C Bus Protocol Format
Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. dress. in the write cycle, but not in the read cycle. Figure 9. Bit Transfer on the I 2 C Bus Figure 10. Data Transfer on the I 2 C Bus
O M N IV I S IO N T E C H N O L O G I E S , Inc. Table 15. Slave ID Addresses pins 35, 37, 34, respectively). reads. MULT is internally defaulted to a low condition. ter. Writing to unimplemented subaddress is ignored. unimplemented subaddress returns unknown.
3.2 Register Set
Table 16. I2 C Registers
00 Gain[6:0] 00 RW
GC[7:6] - unimplemented bit, returns ‘X’ when read. GC[5:0] – Storage for the current AGC Gain setting. gain value in this register. IF AGC is not enabled, a “00” is stored in this register.
01 Blue[7:0] 80 RW
BLU[7] – “0” decrease gain, “1” increase gain. BLU[6:0] – blue channel gain balance value.
02 Red[7:0] 80 RW
RED[7] – “0” decrease gain, “1” increase gain. RED[6:0] – red channel balance value.
03 Sat 80 RW Saturation Control
04 Rsvd04 XX - reserved
05 Cnt 48 RW Contrast Control
06 Brt 80 RW Brightness Control
07 Sharpness C6 RW
08 Rsvd08 XX - reserved
09 Rsvd09 XX - reserved
26 Version 1.11 14 May 1999 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary 0C AWB - Blue 20 R/W White Balance Background: Blue Channel ABLU[7:6] - rsvd ABLU[5] - Sign bit. “0” - decrease background blue component “1” - increase background blue component ABLU[4:0] - White balance blue ratio adjustment 0D AWB - Red 20 R/W White Balance Background: Red Channel ARED[7:6] - rsvd ARED[5] - Sign bit. “0” - decrease background red component “1” - increase background red component ABLU[4:0] - White balance red ratio adjustment 0E COMR 0D RW Common Control R COMR[7] - Analog signal 2x gain control bit. “1” - Additional 2x gain, “0” - normal COMR[6:0] - Reserved 0F COMS 05 RW Common Control S COMS[7:6] - Reserved COMS[5:4] - Black expanding level COMS[3:2] - Set high threshold level COMS[1:0] - Set low threshold level
10 AEC 9A R
Automatic Exposure Control AEC[7:0] - Set exposure time Interlaced: T ex = T line x AEC[7:0] Progressive: T ex = T line x AEC[7:0] x 2
11 CLKRC 00 R
CLKRC[7:5] – Sync output polarity selection “00” - HSYNC=Neg, CHSYNC=Neg, VSYNC=Pos “01” - HSYNC=Neg, CHSYNC=Neg, VSYNC=Neg “10” - HSYNC=Pos, CHSYNC=Neg, VSYNC=Pos “11” - HSYNC=Pos, CHSYNC=Pos, VSYNC=Pos CLKRC[5:0] – Clock prescaler CLK = (CLK_main / ((CLKRC[5:0] + 1) x 2)) / 2
12 COMA 24 RW
COMA[7] - SRST, “1” initiates soft reset. Initiate soft reset. All registers are set to default val- ues and chip is reset to known state and resumes normal operation. This bit is automatically cleared after reset. COMA[6] - MIRR, “1” selects mirror image COMA[5] - VSFR, “1” enables AGC, COMA[4] - Digital output format, “1” selects 8-bit: Y U Y V Y U Y V COMA[3] - Select video data output: “1” - select RGB, “0” - select YCrCb COMA[2] - Auto White Balance “1” - Enable AWB, “0” - Disable AWB COMA[1] - Color Bar Test Pattern: “1” - Enable color bar test pattern COMA[0] - reserved
13 COMB 01 RW
COMB[7] - reserved COMB[6] - reserved COMB[5] - Select data format. “1” - Select 8-bit format, Y/CrCb and RGB is multiplexed to 8-bit Y bus, UV bus is tri-stated, “0” - Select 16-bit format COMB[4] - “1” - enable digital output in CCIR656 format COMB[3] - CHSYNC output: “1” - Horizontal sync, “0” - composite sync COMB[2] - “1” - Tristate Y and UV busses. “0” - enable both busses COMB[1] - “1” - Initiate single frame transfer COMB[0] - “1” - Enable auto adjust mode
14 COMC 00 RW
COMC[7] - reserved COMC[6] - reserved COMC[5] - QCIF digital output format selection. 1 - 176x144; 0 - 352x288. COMC[4] - Field/Frame vertical sync output in VSYNC port selection: 1 - frame sync, only ODD field vertical sync; 0 - field vertical sync, effect in Interlaced mode COMC[3] - HREF polarity selection: 0 - HREF positive effective, 1 - HREF negative. COMC[2] - gamma selection: 1 - RGB Gamma on ; 0 - gamma is 1. COMC[1] - reserved COMC[0] - reserved Subad- dress (hex) Register Default (hex) Read/ Write Descriptions
14 May 1999 Version 1.11 27 OV6620/OV6120 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary
15 COMD 01 RW
COMD[7] - reserved bit. COMD[6] - PCLK polarity selection. “0” OV6620 output data at PCLK falling edge and data bus will be stable at PCLK rising edge; “1” rising edge output data and stable at PCLK falling edge. When OV6620 work as CCIR656 format, COMB4=1, this bit is disable and should use PCLK rising edge latch data bus. COMD[5:1] - reserved bit.
16 FSD 03 RW
FSD[7:2] - Field interval selection. Odd Even mode defined by FD[1:0] 000000 - disable digital data output, only output black reference level. 000001 - divide to 2 slots, HREF is active one in every 2 field/frame 000010 - divide to 4 slots, HREF is active one in every 4 field/frame 000100 - divide to 8 slots, HREF is active one in every 8 field/frame 001000 - divide to 16 slots, HREF is active one in every16 field/frame 010000 - divide to 32 slots, HREF is active one in every 32 field/frame 100000 - divide to 64 slots, HREF is active one in every 64field/frame FSD[1:0]- field mode selection. Each frame consists of two fields: Odd & Even, these bits defines the assertion of HREF in relation to the two fields. 00 - OFF mode; HREF is not asserted in both fields, one exception is the single frame transfer operation (see the description for the register 13) 01 - ODD mode; HREF is asserted in odd field only. 10 - EVEN mode; HREF is asserted in even field only. 11 - FRAME mode; HREF is asserted in both odd field and even field. FD[7:2] useless.
17 HREFST 38 RW
HS[7:0] - selects the starting point of HREF window, each LSB represents two pixels for CIF resolution mode, one pixels for QCIF resolution mode, this value is set based on an internal column counter, the default value corresponds to 352 horizontal window. Maximum window size is 356. see window description below. HS[7:0] programmable range is [38]- [EB], and should less than HE[7:0]. HS[7:0] should be programmable to value larger than or equal to [38]. Value larger than [EC] is invalid. See window description below.
18 HREFEND EA RW
HE[7:0] - selects the ending point of HREF window, each LSB represents two pixels for full resolution and one pixels for QCIF resolution, this value is set based on an internal column counter, the default value corresponds to the last available pixel. The HE[7:0] programmable range is [39] - [EC]. HE[7:0] should be larger than HS[7:0] and less than or equal to [EC]. Value larger than [EC] is invalid. See window description below.
19 VSTRT 03 RW
VS[7:0] - selects the starting row of vertical window, in full resolution mode, each LSB represents 1 scan line in one frame. see window description below. Min. is [03], max. is [93] and should less than VE[7:0]. 1A VEND 92 RW Vertical Line End VE[7:0]- selects the ending row of vertical window, in full resolution mode, each LSB represents 1 scan line in one frame, see window description below. Min. is [04], max. is [94] and should larger than VS[7:0]. 1B PSHFT 00 RW Pixel Shift PS[7:0] - to provide a way to fine tune the output timing of the pixel data relative to that of HREF , it physically shifts the video data output time late in unit of pixel clock as shown in the figure below. This function is different from changing the size of the window as is defined by HS[7:0] & HE[7:0] in register 17&18. Higher than default number shifts the pixel in delay(right) direction, the highest number is “FF”. so maximum shift number is: Late: 256 pixels. 1C MIDH 7F R Manufacture ID Byte: High MIDH[7:0] - read only, always returns “7F” as manufacturer’s ID no. 1D MIDL A2 R Manufacture ID Byte: Low MIDL[7:0] - read only, always returns “A2” as manufacturer’s ID no. 1E Rsvrd1E C4 R reserved 1F Rsvrd1F 04 R reserved Subad- dress (hex) Register Default (hex) Read/ Write Descriptions
28 Version 1.11 14 May 1999 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary
20 COME 00 RW
COME[7] - HREF pixel number selection. “1” - HREF include 704 PCLK, every data output twice. COME[6] - reserved. COME[5] - “1” First stage aperture correction enable. Correction strength will be decided by register [07]. “0” disable first stage aperture correction. COME[4] - “1” Second stage aperture correction enable. Correction strength and threshold value will be decided by COMF[7] ~ COMF[4]. COME[3] - AWB smart mode enable. 1 - Drop out pixel when compare pixel red, blue and green component level to change register [01] and [02], which luminance level is higher than presetting level and lower than presetting level, this two level is set by register [0F]. 0 - calculate all pixels to get AWB result. Valid only when COMB[0]=1 and COMA[2]=1 COME[2] - AWB stop when field/frame image average luminance level is lower than a presetting level enable. 1 - enable stop AWB when image luminance level is low. 0 - AWB is independent with field/frame luminance level. Valid only when COMB0=1 and COMA[2]=1. Average compare level is set by GAM[7:5]. COME[1] - AWB fast/slow mode selection. “1” - AWB is always fast mode, that is register [01] and [02] is changed every field/frame. “0” AWB is slow mode, [01] and [02] change every 16/ 64 field/frame decided by COMK[1]. When AWB enable, COMA[2]=1, AWB is working as fast mode at first 1024 field/frame, than as slow mode later. COME[0] - Digital output driver capability increase selection: “1” Double digital output driver current; “0” low output driver current status.
21 YOFF 80 RW
Y Channel Offset Adjustment YOFF[7] - Offset adjustment direction 0 - Add Y[6:0]; 1 -Substrate Y[6:0]. Y OFF[6:0] -Y channel digital output offset adjustment. Range: +127mV ~ -127mV. If COMG[2]=0, this register will be updated by internal auto A/D BLC circuit, and write a value to this register with I 2 C has no effect. If COMG[2]=1, Y channel offset adjustment will use the register stored value which can be changed by I 2 C. If COMF[1]=0, this register has no adjustment effect to A/D output data. If output RGB raw data, this register will adjust R/G/B data.
22 UOFF 80 RW
U Channel Offset Adjustment UOFF[7]: - Offset adjustment direction: 0 - Add U[6:0]; 1 -Substrate U[6:0]. UOFF[ 6:0] - U channel digital output offset adjustment. Range: +128mV ~ -128mV. If COMG[2]=0, this register will be updated by internal auto A/D BLC circuit, and write a value to this register with I 2 C has no effect. If COMG[2]=1, U channel offset adjustment will use the register stored value which can be changed by I 2 C. If COMF[1]=1, this register has no effect to A/D output data. If output RGB raw data, this register will adjust R/G/B data.
23 REFC 04 RW
REFC[7:6] - Select different crystal circuit power level (11 = minimum). REFC[5:4] - reserved
24 AEW 33 RW
Automatic Exposure Control: Bright Pixel Ratio Adjustment AEW[7:0] - Used as calculate bright pixel ratio. OV6620 AEC algorithm is count whole field/ frame bright pixel (its luminance level is higher than a fixed level) and black pixel (its luminance level is lower than a fixed level) number. When bright/black pixel ratio is same as the ratio defined by register [25] and [26], image stable. This register is used to define bright pixel ratio, default is 25%, each LSB represent step: 1.3% Change range is: [01] ~ [CA]; Increase AEW[7:0] will increase bright pixel ratio. For same light condition, the image brightness will increase if AEW[7:0] increase. Note: AEW[7:0] must combine with register [26] AEB[7:0]. The relation must be as follows:AEW[7:0] + AEB[7:0] > [CA].
25 AEB 97 RW
Automatic Exposure Control: Black Pixel Ration Adjustment AEB[7:0] - used as calculate black pixel ratio. OV6620 AEC algorithm is count whole field/ frame bright pixel (its luminance level is higher than a fixed level) and black pixel (its luminance level is lower than a fixed level) number. When bright/black pixel ratio is same as the ratio defined by register [25] and [26], image stable. This register is used to define black pixel ratio, default is 75%, each LSB represent step: 1.3%; Change range is: [01] ~ [CA]; Increase AEB[7:0] will increase black pixel ratio. For same light condition, the image brightness will decrease if AEB[7:0] increase. Note: AEB[7:0] must e combined with register [25] AEW[7:0]. The relation must be as follows: EW[7:0] + AEB[7:0] > [CA]. Subad- dress (hex) Register Default (hex) Read/ Write Descriptions
14 May 1999 Version 1.11 29 OV6620/OV6120 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary
26 COMF B0 RW
COMF[7:6] - Second aperture correction threshold selection. [00] - Difference of neighbor pixel luminance is larger than 8 mV, correction on. [01] - 16 mV. [10] - 32 mV. [11] - 64 mV. COMF[5:4] - Second aperture correction strength selection. [00] and [01] - Strength is 50% of difference of neighbor pixel luminance. [10] - 100%. [11] - 200%. COMF[3] - UV BLC swap. “1” swap; “0” no swap. COMF[2] - Digital data MSB/LSB swap. “1” LSB->Bit7, MSB->Bit0; “0” normal. COMF[1] - “1” A/D Black level calibration enable. “0” Disable A/D BLC. COMF[0] - “1” Output first 4 line black level before valid data output. HREF number will increase 4 relatively. “0” no black level output.
27 COMG A0 RW
COMG[7] - reserved COMG[6] - reserved. COMG[5] - Select CKOUT pin output V flag. 1 - CKOUT output V flag signal. CKOUT=1, means related UV channel output V component (or Red component), CKOUT=0 pointed to U component (or Blue component). 0 - CKOUT output buffered XCLK2 COMG[4] - reserved. COMG[3] - reserved COMG[2] - “1” A/D offset adjustment manually mode enable: 1 - A/D data will be add/substrate a value defined by register [21] and [22], which content is written by I 2 C. 0 - A/D data will be added/substrate a value defined by register [21] and [22], which is updated by internal circuit. COMG[1] - Digital output full range selection. OV6620 output data value range is [10] - [F0], if COMG[1] -1, range change to [01] - [FE] with signal overshoot and undershoot level. COMG[0] - reserved.
28 COMH 01 RW
COMH[7]: - “1” selects One-Line RGB raw data output format, “0” selects normal two-line RGB raw data output, effective only in Progressive Scan mode. COMH[6]: - “1” enable Black/White mode. When OV6620 working as BW camera, its vertical resolution will be higher than color mode. At this mode, can’t set OV6620 working at 8 bit output mode. OV6620 output data YUV/RGB from Y port. UV port will be tri-state. COMB[5] and COMB[4] will be set to “0”. “0” normal color mode. COMH[5]: - reserved. COMH[4]: - Freeze AEC/AGC value, effective only when COMB0=1. “1” - register [00] and [10] will not be updated and hold latest value. “0” - AEC/AGC normal working status. COMH[3]: - AGC disable. 1 - when COMB[0]=1 and COMA[5]=1, internal circuit will not update register [00], register [00] will kept latest updated value before COMH[3]=1. 0 - when COMB0=1 and COMA[5]=1, register [00] will be updated by internal algorithm. COMH[2]: - RGB raw data output YG format: 1 - Y channel G, UV channel B R; 0 - Y channel: COMH[1]: - Gain control bit. “1” Double PreAmp gain to 12dB. “0” PreAmp gain is 6dB. COMH[0]: - High gain mode. “1” - AGC maximum gain is 24dB. AGC step is 1/8. “0” AGE maximum gain is 18dB, AGC step is 1/16. Only effective when COMB[0]=1, COMA[5]=1 and COMH[3]=0.
29 COMI 00 RW
COMI[7]: - AEC disable. “1” If COMB[0]=1, AEC stop and register [10] value will be held at last AEC value and not be updated by internal circuit. “0” - if COMB[0]=1, register [10] value will be updated by internal circuit COMI[6]: - Slave mode selection. “1” slave mode, use external Sync and Vsync; “0” master mode COMI[5]: - reserved COMI[4]: - reserved COMI[3]: - Central 1/4 image area rather whole image used to calculate AEC/AGC. “0” use whole image area to calculate AEC/AGC. COMI[2]: - reserved COMI[1:0] - Version flag. For Version A, value is [00], these two bits can only be read. 2A FRARH 84 RW Frame Rate Adjust High FRARH[7] - Frame Rate adjustment enable bit. “1” Enable. FRARH[6] - reserved FRARH[5] - Highest 1bit of frame rate adjust control byte. see explanation below. FRARH[4] - reserved FRARH[3] - Y channel brightness adjustment enable. When COMF[2]=1 active. FRARH[2] - reserved FRARH[1] - “1” When in Frame exposure mode, only One frame data output. FRARH[0] - reserved Subad- dress (hex) Register Default (hex) Read/ Write Descriptions
30 Version 1.11 14 May 1999 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary 2B FRARL 5E RW Frame Rate Adjust Low FRARL[7:0] - Lowest 8 bit of frame rate adjust control byte. Frame rate adjustment resolution 0.21% - 109%. IF frame rate adjustment enable, COME7 must set to “0”. 2C Rsvd2C 88 RW reserved 2D COMJ 03 RW Common Control J COMJ[7:5] - reserved COMJ[4] - Enable auto black expanding mode. COMJ[3] - “1” = White Balance update when AGC/AEC stable. “0” = White Balance register update independent with AEC/AGC. COMJ[2] - Band filter enable. After adjust frame rate to match indoor light frequency, this bit enable a different exposure algorithm to cut light band induced by fluorescent light. COMJ[1] - reserved COMJ[0] - A/D U and V BLC separate mode. “1” = U and V offset cancelled by different register. “0” = U V offset cancelled by one common register [2E]. 2E VCOFF 80 RW V Channel Offset Adjustment VCOFF[7]: Offset adjustment direction: “0” = Add V[6:0]; “1” = Substrate V[6:0]. VCOFF[6: 0] - V channel digital output offset adjustment. Range: +128mV ~ -128mV. If COMG[2]=0, this register will be updated by internal auto A/D BLC circuit, and write a value to this register with I 2 C has no effect. If COMG[2] =1, V channel offset adjustment will use the register stored value which can be changed by I 2 C. If COMF[1] =1, this register has no effect to A/D output data. If output RGB raw data, this register will adjust R/G/B data. 2F-32 Rsvd2F-Rsvd32 xx - Reserved
33 CPP 00 RW
Color Processing Parameter Control CPP[7:6] - reserved CPP[5] - Luminance gamma on/off. “1” - luminance gamma on; “0” - luminance gamma is 1. CPP[4:0] - reserved
34 BIAS A2 RW
BIAS[7:6] - A/D reference level adjustment. [00] - 110% internal full signal range; [01] - 120%, BIAS[5:0] - reserved
35 Rsvd35 80 RW reserved
36 Rsvd36 48 RW reserved
37 Rsvd37 41 RW reserved
38 COMK 81 RW
COMK[7] - HREF edge latched by PCLK falling edge (When COMD[6] = 0). “0” HREF edge is 10 ns after PCLK rising edge. COMK[6] - Output port drive current additional 2x control bit. COMK[5] - reserved. COMK[4] - ZV port Vertical timing selection. “1” VSYNC output ZV port vertical sync signal. “0” = normal TV vertical sync signal. COMK[3] - Quick stable mode when camera mode change. After relative control bit set, the first VS will be the stable image with suitable AEC/AWB setting. “0” - slow mode, after mode change need more field/frame to get stable AEC/AWB setting image. COMK[2] - reserved COMK[1] - AWB stable time selection when in slow mode. “1” - 4 times less time needed to get stable AWB setting when in slow AWB mode. COMK[0] -reserved.
39 COML 00 RW
COML[7] - reserved COML[6] - PCLK output timing selection. 1 -- PCLK valid only when HREF is high; 0 -- PCLK is free running. COML[5] - Vertical sync selection, 1 -- Same period between 1st HREF and VS falling edge in two field; 0 - Different timing period between 1st HREF and VS falling edge COML[4] - “1” select CHSYNC output from HREF port. “0” normal COML[3] - “1” select HREF output from CHSYNC port. “0” normal COML[2] - Tristate all control signal output (FODD, CHSYNC, HREF, PCLK) COML[1] - Highest 1 bit of horizontal sync starting position, combined with register [3A] COML[0] - Highest 1 bit of horizontal sync ending position, combined with register [3B] 3A HSST 0F RW Horizontal Sync Start Position HSST[7:0] - lower 8 bit of horizontal sync starting position, combined with register bit of COML[1], total 9 bit control. range: [00] -- [FF]. HSEND[8:0] must less than HSST[8:0] 3B HSEND 3C RW Horizontal Sync End Position HEND[7:0] - lower 8 bit of horizontal sync ending position, combined with register bit of COML[0], total 9 bit control. range: [00] -- [FF]. HSEND[8:0] must be larger than HSST[8:0] Subad- dress (hex) Register Default (hex) Read/ Write Descriptions
14 May 1999 Version 1.11 31 OV6620/OV6120 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS O M N IV I S IO N T E C H N O L O G I E S , Inc. Advanced Information Preliminary 3C COMM 21 RW Common Control M COMM[7:5] - Select minimum AEC number if Banding filter enable. [000] -- 1 field, [001] -- 1/2; COMM[4] - AEC/AGC change mode selection COMM[3] - AEC/AGC change mode selection COMM[2] - AEC/AGC change fastest mode COMM[1] - AEC/AGC change fast mode COMM[0] - AEC/AGC change slowest mode 3D COMN 08 RW Common Control N COMN[7] - Enable one frame drop when AEC change to keep data valid when Banding filter mode enable. COMN[6:4] - reserved COMN[3] - Enable 50 Hz PAL video timing, so VTO analog signal can be displayed on TV COMN[2:0] - reserved 3E COMO 80 RW Common Control O COMO[7] - Input main clock divided by 2 or 4 selection. 1 -- 2; 0 -- 4 COMO[6:5] - reserved COMO[4] - Select 4 bit nibble mode output COMO[3] - reserved COMO[2] - Enable Minimum exposure time is 4 line. Default is 1 line COMO[1] - reserved COMO[0] - reserved 3F COMP 02 RW Common Control P COMP[7] - reserved COMP[6] - Output main clock output from FODD port COMP[5] - reserved COMP[4] - Software whole chip power down enable, can be waked up by disable this bit COMP[3:2] - reserved COMP[1] - CCIR656 output control COMP[0] - Reset internal timing circuit without reset AEC/AGC/AWB value
40 Rsvd40 - Rsvd4C XX - reserved
YUV Matrix Control (Main) YMXA[7:5] - reserved YMXA[4:3] - YUV/YCrCB selection: [00] U = u, V = v YMXA[2:0] - Reserved 4E Rsvd4E XX - reserved 4F YMXB 00 RW YUV Matrix Control (Secondary) YMXB[7:6] - Y channel delay selection: 0 ~ 3 tp YMXB[5:4] - UV delay selection: 0 ~ 6 tp YMXB[3:2] - Select UV average mode. [00] & [10]: U0/V0 (no delay); [01] -- 3 point average; [11] -- 5 point average mode YMXB[1:0] - Color killer control: [00]:2.4v;[01]:2.6v;[10]:2.8v;[11]:3.0v
50 Rsvd50 - Rsvd53 XX - reserved
(hex) Register Default (hex) Read/ Write Descriptions