OV5017 ETC | Alldatasheet
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Technical content
Features
n Single chip 1/4” video image sensor n Progressive scan n Built-in analog-to-digital (A/D) 8-bit pixel resolution n Programmable f eatures n Fr ame rate of 50 ~ 0.5 frames per second (fps) n Ex posure setting: 1 frame ~ 1/100 frame n Im age size: 4.2 mm x 3.2 mm n AGC (auto gain control): 0 ~ 18 dB n Gamma correction: 0.45/1.0 n Pixel elements - 384 x 288 n Pixel dimension of 11 um x 11 um n External frame sync capabilit y n S ignal-to-noise (S/N) ratio > 42 dB n Minimum illumination of 0.5 lux at f1.4 at 50 fps n Single 5-volt supply operation for analog and 5/3.3 volts for digital n Power consumption — Active: less than 100 mW at 50 fps — Standby: less than 100 µA n 4 8-pin package Overview The OV5017 is a black and white digital camera chip that uses OmniVision’s CMOS image core technology. Combining the CMOS sensor technol- ogy and an easy to use digital interface, the OV5017 offers a low cost solution for high - quality video image applications. The digital video port supplies a continuous byte- wide image data. On-chip programmable features include variable frame rate, exposure setting, and image size. All the camera features are register based , accessing the video data and configuring the chip is as easy as read/write of a static mem- ory. OV5017 PIN ASSIGNMENTS AGND VRCR FSI AVDD SVDD SGND AVO VVDD AO DEVDD DEGND ZGND AGND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C A3 31 OGND OVDD ZVDD VR2 OEB WEB CSB X CLKI X C LKO H REF P CLK V S YNC D VDD D GND OV5017
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. chronized with the actual pixel rate. ing this bit before the new frame cancels the assertion of HREF. Table 1. Pin Descriptions 1 Bias SGND Sensor ground. Connect to supply common. 2 Bias SVDD Sensor power (+5V) connection. 3 Bias AVDD Analog power (+5V) connection. 4 I-0 FSI External frame sync input. A rising edge on FSI sets the chip vertical sync timing. rate. Internally pulled down with a 100k resistor. Leave open or ground if unused. 5 Bias VrCR Internal reference voltage. Requires a 0.1uF external capacitor to AGND. 6 Bias AGND Analog ground. Connect to supply common. 7 Bias AGND Analog ground. Connect to supply common. 8-17 FT N/C Factory test. Leave open. I A3-A0 Address inputs for internal the registers. Requires CSB = 0 to access the registers. 21 I OEB Output enable for the eight bit data bus. OEB = 0 enables the data bus drivers. OEB = 1 puts the data bus in tristate.
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. external data is latched into the registers with the rising edge of WEB. 23 I CSB Chip select for the device. CSB = 0 selects the device. connect an external clock to XCLKI , leave XCLKO open. status(1), are identical valid pixel timing information. at the falling edge of PCLK. 29 Bias DVDD Digital power (+5V) connection. 40 Bias OVDD Digital output power (+5V/+3.3V) connection. 41 Bias ZVDD Analog power (+5V) connection. 42 Bias VR2 Internal reference voltage. Requires a 0.1uF external capacitor to AGND. 43 Bias ZGND Analog ground. Connect to supply common. 44 Bias DEGND Decoder ground. Connect to supply common. 45 Bias DEVDD Decoder power (+5V) connection. 47 Bias VVDD Video output power (+5V) connection. 48 Q AVO Composite video output. It is capable of driving 150 Ω load, Vp-p is 2.0 V. Table 1. Pin Descriptions (Continued)
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 1. Video Data Timing Showing Continuous Pixel Reading highest is ‘hff’, no reserved code for blanking or sync. can be latched at the falling edge of PCLK . address are asserted as shown in Figure 1. ister bit RDY and OV allows host to perform polling and error detection.
1.1 Register Control
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. Note: Unimplemented bits in all the R/W registers return “0” in the read cycle, no effect in the write cycle.
2.1 Detailed Register Descriptions
Table 2. Register Sets
0000 STATUS R TO2,TO1, , ,OV,
0010 EXCTL R/W AUTO, EX [6 :0 ] Au to or m anual e xposure
0011 GCTL R/W GN [2 :0 ] Ga in value xxxx x 000
0100 FRCTL R/W FDIV [5 :0 ] Fr ame rate divider x x 000000
0101 MCTL R/W GAM M A, MIR, DN,
0110 HWCTL R/W HWS[3:0], HWE [3 :0 ] Wi ndow control 00000000
0111 VWCTL R/W VWS[3:0], VWE [3 :0 ] Wi ndow control 00000000
1110 TST W TST [7 :0 ] Re served for test xxxxx xxx
1111 TOPT W TOPT[7:0] Re served for test xxxxxxxx
Table 3. Bit descriptions is updated as new pixel signals are converted. STATUS TO2 STA7 Reserved bit.
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. STA0 has been set already. Reading of this register clears the bit. VSYNC STA2 This bit duplicates the signal at pin VSYNC. HREF STA1 This bit duplicates the signal at pin HREF. is being read while pixel data is updating. the end of the new frame so that it can be set again. asserted only for the first frame immediately after setting the FCTL [7 ]. mode. However, frame BLC provides better image stability. takes about two frames for the chip to become stable. Table 3. Bit descriptions (Continued)
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. select manual exposure mode, clear this bit. ( 50 *128*2)s. This register is used in manual exposure mode only. frames for the chip to become stable. MCTL GAMA MCTL[7] Set this bit to select g amma = 0.45, a nd clear this bit for g amma = 1. MIR MCTL[6] Set this bit to se lect m irror image. NSR MCTL[5] Set this bit to tu rn o n indoor mode, and clear for outdoor mode . BKL MCTL[4] Set this bit to tu rn o n backlight compensation. sure mode ; it has n o effect in manual exposure mode . PCKI MCTL[1] Set this bit to inverse the polarity of PCLK . BPSHP MCTL[0] Set this bit to disable sharpness function. HWS HWCTL[7:4] Selects the start of the horizontal window. HWE HWCTL[3:0] Selects the end of the horizontal window. VWS VWCTL[7:4] Selects the start of the vertical window. VWE VWCTL[3:0] Selects the end of the vertical window.
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. shown in Figure 1.1. each block is H2 4 xV1 8 pixels. region, use HWCTL=4 cH ,VWCTL=4 4H . Figure 4. Windowing
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc.
- Electrical Specifications
This section provides the electrical parameters descriptions and timing diagrams.
3.1 Electrical Parameters
Table 4. Electrical parameters (0 o C < TA < 85 o C, voltages referenced to GND)
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. Table 4. Electrical parameters (0 o C < TA < 85 o C, voltages referenced to GND) (Continued)
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc.
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc.
3.2 Timing diagram s
Figure 5. Video Data Ti ming (3 84 x 2 88) , PCLK = 1/4 XC LK i
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 6. Video Port Timing (192 x 144), PCLK = 1/2 X CLKi
October 20, 1997 Version 1.6 15 OV5017 Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. X C L K I P C L K H R E F D A T A [ 7 : 0 ] V S Y N C ( A ) H O R I Z O N T A L T IM IN G ( B ) V E R T I C A L T IM IN G H R E F Y 0 Y 1H 0 0 Y 3 8 3Y 3 8 2 H 0 0 2 8 8 1 2 3 2 8 8 1 22 8 7 2 8 7 0 0 0H 0 00D A T A [ 7 : 0 ] 0 0 0 H 0 0 0 I N T E R N A L 2 8 8 1 2 3 2 8 8 1 22 8 7 2 8 7 H - S Y N C
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 9. Register R/W Timing
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 10. OV5017 Sensor Array Location Dimensions (in inches)
Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. Figure 11. OV5017 Package Outline Dimensions
48 PLCS
4 CORNERS
20 Version 1.6 October 20, 1997 Confidential P reliminary Product SpecificationO M N IV I S IO N T E C H N O L O G I E S , Inc. ERRATA 11/20/97 1. In default mode, the video data changes on the falling edge of PCLK instead of on the rising edge. We recommand inverting the PCLK pin polarity by setting MCTL(1) so the video data can still be latched on the falling edge of PCLK. All the pclk timing parameters is applied to inverted PCLK. 2. OV5017 default active HREF window width has one extra pixel, 385 instead of 384, the back porch blanking is one less, that is: tHACT = 385, t HB = 32. 2/14/98 3. A glitch ( width 1/2 ~ 10 PCLKS) in HREF appears between VSYNC and the first valid HREF if pro- grammed FRCTL(5:0) >= 9. 4. Intensity of lines (32,33,256,257) may be different from the rest of image if programmed FRCTL(5:0)=