OV2640

OV2640_V01 OMNIVISION | Alldatasheet

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Technical content

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 1 Advanced Information Preliminary Datasheet OV2640 Color CMOS UXGA (2.0 MegaPixel) CAMERACHIPTM Omni ision® with OmniPixel2TM Technology General Description The OV2640 C AMERACHIPTM is a low voltage CMOS image sensor that provides the full functionality of a single-chip UXGA (1632x1232) camera and image processor in a small footprint package. The OV2640 provides full-frame, sub-sampled, scaled or windowed 8-bit/10-bit images in a wide range of formats, controlled through the Serial Camera Control Bus (SCCB) interface. This product has an image array capable of operating at up to 15 frames per second (fps) in UXGA resolution with complete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control, white pixel canceling, noise canceling, and more, are also programmable through the SCCB interface. The OV2640 also includes a compression engine for increased processing power. In addition, OmniVision C AMERACHIPS use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable color image.Features

• High sensitivity for low-light operation
• Low operating voltage for embedded portable apps
• Standard SCCB interface
• Output support for Raw RGB, RGB (RGB565/555), GRB422, YUV (422/420) and YCbCr (4:2:2) formats
• Supports image sizes: UXGA, SXGA, SVGA, and any size scaling down from SXGA to 40x30
• V a r i o P i x e l ® method for sub-sampling
• Automatic image control functions including Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), Automatic Band Filter (ABF), and Automatic Black-Level Calibration (ABLC)
• Image quality controls including color saturation, gamma, sharpness (edge enhancement), lens correction, white pixel canceling, noise canceling, and 50/60 Hz luminance detection
• Line optical black level output capability
• Video or snapshot operation
• Zooming, panning, and windowing functions
• Internal/external frame synchronization
• Variable frame rate control
• Supports LED and flash strobe mode
• Supports scaling
• Supports compression
• Embedded microcontroller

Ordering Information

Note: The OV2640 uses a lead-free package. Product Package OV02640-VL9A (Color, lead-free) 38-pin CSP2

Applications

• Cellular and Camera Phones
• T o y s
• PC Multimedia
• Digital Still Cameras Key Specifications Figure 1 OV2640 Pin Diagram (Top View) Array Size UXGA 1600 x 1200 Power Supply Core 1.2VDC + 5% Analog 2.5 ~ 3.0VDC I/O 1.7V to 3.3V Power Requirements Active 125 mW (for 15 fps, UXGA YUV mode) 140 mW (for 15 fps, UXGA compressed mode) Standby 600 µA Temperature Range Operation -30°C to 70°C Stable Image 0°C to 50°C Output Formats (8-bit)
• YUV(422/420)/YCbCr422
• RGB565/555
• 8-bit compressed data
• 8-/10-bit Raw RGB data Lens Size 1/4" Chief Ray Angle 25° non-linear Maximum Image Transfer Rate UXGA/SXGA 15 fps SVGA 30 fps CIF 60 fps Sensitivity 0.6 V/Lux-sec S/N Ratio 40 dB Dynamic Range 50 dB Scan Mode Progressive Maximum Exposure Interval 1247 x t ROW Gamma Correction Programmable Pixel Size 2.2 µm x 2.2 µm Dark Current 15 mV/s at 60°C Well Capacity 12 Ke Fixed Pattern Noise <1% of VPEAK-TO-PEAK Image Area 3590 µm x 2684 µm Package Dimensions 5725 µm x 6285 µm OV2640 AGND SGND VREFN STROBE A1 A2 A4 A3 A5 A6 B1 B2 B4 B3 B5 B6 C1 C2 C4 C3 C5 C6 D2 D6 E1 E2 E4 E3 E5 E6 F1 F2 F4 F3 F5 F6 G1 G2 G4 G3 G5 G6 DOGND EXPST_B AVDD SVDD SVDD PWDNDOVDD FREX HREF XVCLK VREFH RESETBSIO_D SIO_C NCVSYNC PCLK EGND Y6 DGNDY1 Y0 Y2 Y4 Y8 DVDDEVDD DVDD Y3 Y5 Y7 Y9EVDD DGND

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 3 Omni ision Image Sensor Array The OV2640 sensor has an image array of 1632 columns by 1232 rows (2,010,624 pixels). Figure 3 shows a cross-section of the image sensor array. Figure 3 Sensor Array Region Color Filter Layout The color filters are arranged in a Bayer pattern. The primary color BG/GR array is arranged in line-alternating fashion. Of the 2,010,624 pi xels, 1,991,040 (1632x1220) are active. The other pixels are used for black level calibration and interpolation. The sensor array design is ba sed on a field integration read-out system with line-by-line transfer and an electronic shutter with a synchronous pixel read-out scheme. Analog Amplifier When the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. Gain Control The amplifier gain can either be programmed by the user or controlled by the internal automatic gain control circuit (AGC). RG RG RG RG RG RG GB GB GB GB GB GB RG RG RG GB GB GB RG RG RG RG RG RG GB GB GB GB GB GB RG RG RG GB GB GB RG RG RG GB GB GB RG RG RG GB GB GB 1626 1627 1628 1629 1630 1631 Column Dummy Dummy Dummy Dummy Dummy Dummy Optical Black Dummy Dummy RG RG RG GB GB GB 1207 1206 1231 1208 RG RG RG GB GB GB RG RG RG RG RG RG GB GB GB GB GB GB RG RG RG RG RG RG GB GB GB GB GB GB 1220 Active Lines R o w 10-Bit A/D Converters After the analog amplifier, the bayer pattern Raw signal is fed to two 10-bit analog-to-digital (A/D) converters, one for G channel and one shared by the BR channels. These A/D converters operate at speeds up to 20 MHz and are fully synchronous to the pixel rate (actual conversion rate is related to the frame rate). Channel Balance The amplified signals are then balanced with a channel balance block. In this block, the Red/Blue channel gain is increased or decreased to match Green channel luminance level. Balance Control Channel Balance can be done manually by the user or by the internal automatic white balance (AWB) controller. Black Level Compensation After the pixel data has been digitized, black level calibration can be applied before the data is output. The black level calibration block subtracts the average signal level of optical black pixels to compensate for the dark current in the pixel output. The user can disable black level calibration. Windowing The OV2640 allows the user to define window size or region of interest (ROI), as required by the application. Window size setting (in pixels) ranges from 2 x 4 to 1632 x 1220 (UXGA) or 2 x 2 to 818 x 610 (SVGA), and 408 x 304 (CIF), and can be anywhere inside the 1632 x 1220 boundary. Note that modifying window size or window position does not alter the frame or pixel rate. The windowing control merely alters the assertion of the HREF signal to be consistent with the programmed horizontal and vertical ROI. The default window size is 1600 x 1200. Refer to Figure 4 and registers HREFST, HREFEND, REG32, VSTRT, VEND, and COM1 for details.

8 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision Pin Description Table 3 Pin Description Pin Location Name Pin Type Function/Description A1 DOGND Ground Ground for digital video port A2 EXPST_B Input Snapshot Exposure Start Trigger 0: Sensor starts exposure (only effective in snapshot mode) 1: Sensor stays in reset mode Note: There is no internal pull-up/pull-down resistor. A3 AGND Ground Ground for analog circuit A4 SGND Ground Ground for sensor array A5 VREFN Reference Internal analog reference - c onnect to ground using a 0.1 µF capacitor A6 STROBE I/O Flash control output Default: Input Note: There is no internal pull-up/pull-down resistor. B1 DOVDD Power Power for digital video port B2 FREX Input Snapshot trigger - use to activate a snapshot sequence Note: There is no internal pull-up/pull-down resistor. B3 AVDD Power Power for analog circuit B4 SVDD Power Power for sensor array B5 SVDD Power Power for sensor array B6 PWDN Input Power-down mode enable, active high Note: There is an internal pull-down resistor. C1 SIO_D I/O SCCB serial interface data I/O C2 SIO_C Input SCCB serial interface clock input Note: There is no internal pull-up/pull-down resistor. C3 HREF I/O Horizontal reference output Default: Input Note: There is no internal pull-up/pull-down resistor. C4 XVCLK Input System clock input Note: There is no internal pull-up/pull-down resistor. C5 VREFH Reference Internal analog reference - c onnect to ground using a 0.1 µF capacitor C6 RESETB Input Reset mode, active low Note: There is an internal pull-up resistor. D2 VSYNC I/O Vertical synchronization output Default: Input Note: There is no internal pull-up/pull-down resistor. D6 NC – No connection E1 Y1 I/O Video port output bit[1] Default: Input Note: There is no internal pull-up/pull-down resistor.

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 9 Omni ision E2 Y0 I/O Video port output bit[0] Default: Input Note: There is no internal pull-up/pull-down resistor. E3 PCLK I/O Pixel clock output Default: Input Note: There is no internal pull-up/pull-down resistor. E4 EGND Ground Ground for internal regulator E5 Y6 I/O Video port output bit[6] Default: Input Note: There is no internal pull-up/pull-down resistor. E6 DGND Ground Ground for digital core F1 EVDD Power Power for internal regulator F2 DVDD Power Sensor digital power (Core) F3 Y2 I/O Video port output bit[2] Default: Input Note: There is no internal pull-up/pull-down resistor. F4 Y4 I/O Video port output bit[4] Default: Input Note: There is no internal pull-up/pull-down resistor. F5 Y8 I/O Video port output bit[8] Default: Input Note: There is no internal pull-up/pull-down resistor. F6 DVDD Power Sensor digital power (Core) G1 EVDD Power Power for internal regulator G2 DGND Ground Ground for digital core G3 Y3 I/O Video port output bit[3] Default: Input Note: There is no internal pull-up/pull-down resistor. G4 Y5 I/O Video port output bit[5] Default: Input Note: There is no internal pull-up/pull-down resistor. G5 Y7 I/O Video port output bit[7] Default: Input Note: There is no internal pull-up/pull-down resistor. G6 Y9 I/O Video port output bit[9] Default: Input Note: There is no internal pull-up/pull-down resistor. Table 3 Pin Description Pin Location Name Pin Type Function/Description

10 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision Figure 12 Pinout Diagram Table 4 Ball Matrix 1 2 3 4 5 6 A DOGND EXPST_B AGND SGND VREFN STROBE B DOVDD FREX AVDD SVDD SVDD PWDN C SIO_D SIO_C HREF XVCLK VREFN RESETB D VSYNC NC E Y1 Y0 PCLK EGND Y6 DGND F EVDD DVDD Y2 Y4 Y8 DVDD G EVDD DGND Y3 75 Y7 Y9 OV2640 AGND SGND VREFN STROBE A1 A2 A4 A3 A5 A6 B1 B2 B4 B3 B5 B6 C1 C2 C4 C3 C5 C6 D2 D6 E1 E2 E4 E3 E5 E6 F1 F2 F4 F3 F5 F6 G1 G2 G4 G3 G5 G6 DOGND EXPST_B AVDD SVDD SVDD PWDNDOVDD FREX HREF XVCLK VREFH RESETBSIO_D SIO_C NCVSYNC PCLK EGND Y6 DGNDY1 Y0 Y2 Y4 Y8 DVDDEVDD DVDD Y3 Y5 Y7 Y9EVDD DGND

Electrical Characteristics

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 11 Omni ision NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage. Table 5 Absolute Maximum Ratings Ambient Storage Temperature -40ºC to +95ºC Supply Voltages (with respect to Ground) VDD-A 4.5V VDD-C 3V VDD-IO 4.5V All Input/Output Voltages (with respect to Ground) -0.3V to VDD-IO+1V Lead-free Temperature, Surface-mount process 245ºC ESD Rating, Human Body model 2000V Table 6 DC Characteristics (-30°C < T A < 70°C) Symbol Parameter Min Typ Max Unit Supply VDD-A Supply voltage 2.5 2.8 3.0 V VDD-D Supply voltage 1.14 1.2 1.26 V VDD-IO Supply voltagea a. 1.8V I/O is supported. Contact your local OmniVision FAE for further details. 1.71 2.8 3.3 V IDDA-A Active (Operating) Currentb b. V DD-A = 2.8V, VDD-D = 1.2V, and VDD-IO = 1.8V for 15 fps in UXGA mode IDDS-SCCB refers to SCCB-initiated Standby, while IDDS-PWDN refers to PWDN pad-initiated Standby 30 40 mA IDDA-D Active (Operating) Currentb 25 (YUV) 35 (Compressed) 35 (YUV) 50 (Compressed) mA IDDA-IO Active (Operating) Currentb 61 0 m A IDDS-SCCB Standby Currentb 12 m A IDDS-PWDN 600 1200 µA Digital Inputs VIL Input voltage LOW 0.54 V VIH Input voltage HIGH 1.26 V CIN Input capacitor 10 pF Digital Outputs (standard loading 25 pF) VOH Output voltage HIGH 1.62 V VOL Output voltage LOW 0.18 V Serial Interface Inputs V IL SIO_C and SIO_D -0.5 0 0.54 V VIH SIO_C and SIO_D 1.26 1.8 2.3 V

12 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision Table 7 AC Characteristics (T A = 25°C, VDD-A = 2.8V) Symbol Parameter Min Typ Max Unit ADC Parameters B Analog bandwidth 20 MHz DLE DC differential linearity error 0.5 LSB ILE DC integral linearity error 1 LSB Settling time for hardware reset <1 ms Settling time for software reset <1 ms Settling time for UXGA/SVGA mode change <1 ms Settling time for register setting <300 ms Table 8 Timing Characteristics Symbol Parameter Min Typ Max Unit Oscillator and Clock Input fOSC Frequency (XVCLK) 6 24 MHz tr, tf Clock input rise/fall time 5 ns Clock input duty cycle 45 50 55 %

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 13 Omni ision Timing Specifications Figure 13 SCCB Interface Timing Diagram Table 9 SCCB InterfaceTiming Specifications Symbol Parameter Min Typ Max Unit fSIO_C Clock Frequency 400 KHz tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 600 ns tAA SIOC low to Data Out valid 100 900 ns tBUF Bus free time before new START 1.3 µs tHD:STA START condition Hold time 600 ns tSU:STA START condition Setup time 600 ns tHD:DAT Data-in Hold time 0 µs tSU:DAT Data-in Setup time 100 ns tSU:STO STOP condition Setup time 600 ns tR, tF SCCB Rise/Fall times 300 ns tDH Data-out Hold time 50 ns SIOC tSU:STA tHD:STA SIOD IN SIOD OUT tF tLOW tHIGH tR tHD:DAT tSU:DAT tAA tDH tBUF tSU:STO

14 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing Table 10 Pixel Timing Specifications Symbol Parameter Min Typ Max Unit tp PCLK period 27.78 ns tpr PCLK rising time 3.5 ns tpf PCLK falling time 2.2 ns tdphr PCLK negative edge to HREF rising edge 0 5 ns tdphf PCLK negative edge to HREF negative edge 0 5 ns tdpd PCLK negative edge to data output delay 0 5 ns tsu Data bus setup time 15 ns thd Data bus hold time 8 ns PCLK or MCLK D[9:0] P0 thdtsu tdpd HREF tdphftdphr tp P1599/799/399 Invalid Data P1 P2 P1598/798/398 P1599/799/399 tpr tpf

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 17 Omni ision OV2640 Light Response Figure 20 OV2640 Light Response OV-9620spectrum response 100 120 140 160 180 200 300nm 380nm 420nm 460nm 500nm 540nm 580nm 620nm 660nm 700nm 740nm 780nm 820nm 860nm 900nm 940nm 980nm 1020nm 1060nm 1100nm 1180nm Wavelength Sensitivity R G B OV2640 Spectrum Response

18 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision Register Set Table 12 and Table 13 provides a list and description of the Device Control registers contained in the OV2640. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 60 for write and 61 for read. There are two different sets of register banks. Register 0xFF controls which se t is accessible. When register 0xFF=00, Table 12 is effective. When register 0xFF=01, Table 13 is effective. Table 12 Device Control Register List (when 0xFF = 00) (Sheet 1 of 4) Address (Hex) Register Name Default (Hex) R/W Description 00-04 RSVD XX – Reserved

05 R_BYPASS 0x1 RW

Bit[7:1]: Reserved Bit[0]: Bypass DSP select 0: DSP 1: Bypass DSP, sensor out directly 06-43 RSVD XX – Reserved

44 Qs 0C RW Quantization Scale Factor

45-4F RSVD XX – Reserved

50 CTRLl[7:0] 00 RW

Bit[7]: LP_DP Bit[6]: Round Bit[5:3]: V_DIVIDER Bit[2:0]: H_DIVIDER

51 HSIZE[7:0] 40 RW H_SIZE[7:0] (real/4)

52 VSIZE[7:0] F0 RW V_SIZE[7:0] (real/4)

53 XOFFL[7:0] 00 RW OFFSET_X[7:0]

54 YOFFL[7:0] 00 RW OFFSET_Y[7:0]

55 VHYX[7:0] 08 RW

Bit[7]: V_SIZE[8] Bit[6:4]: OFFSET_Y[10:8] Bit[3]: H_SIZE[8] Bit[2:0]: OFFSET_X[10:8]

56 DPRP[7:0] 00 RW Bit[7:4]: DP_SELY

Bit[3:0]: DP_SELX

57 TEST[3:0] 00 RW Bit[7]: H_SIZE[9]

Bit[6:0]: Reserved 5A ZMOW[7:0] 58 RW OUTW[7:0] (real/4) 5B ZMOH[7:0] 48 RW OUTH[7:0] (real/4) 5C ZMHH[1:0] 00 RW Bit[7:4]: ZMSPD (zoom speed) Bit[2]: OUTH[8] Bit[1:0]: OUTW[9:8] 5D-7B RSVD XX – Reserved 7C BPADDR[3:0] 00 RW SDE Indirect Register Access: Address

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 19 Omni ision 7D BPDATA[7:0] 00 RW SDE Indire ct Register Access: Data 7E-85 RSVD XX – Reserved

86 CTRL2 0D RW

Bit[7:6]: Reserved Bit[5]: DCW Bit[4]: SDE Bit[3]: UV_ADJ Bit[2]: UV_AVG Bit[1]: Reserved Bit[0]: CMX

87 CTRL3 50 RW

Bit[7]: BPC Bit[6]: WPC Bit[5:0]: Reserved 88-8B RSVD XX – Reserved 8C SIZEL[5:0] 00 RW {HSIZE[11] , HSIZE[2:0], VSIZE[2:0]} 8D-BF RSVD XX – Reserved C0 HSIZE8[7:0] 80 RW Image Hori zontal Size HSIZE[10:3] C1 VSIZE8[7:0] 60 RW Image Ve rtical Size VSIZE[10:3] C2 CTRL0 0C RW Module Enable Bit[7]: AEC_EN Bit[6]: AEC_SEL Bit[5]: STAT_SEL Bit[4]: VFIRST Bit[3]: YUV422 Bit[2]: YUV_EN Bit[1]: RGB_EN Bit[0]: RAW_EN C3 CTRL1 FF RW Module Enable Bit[7]: CIP Bit[6]: DMY Bit[5]: RAW_GMA Bit[4]: DG Bit[3]: AWB Bit[2]: AWB_GAIN Bit[1]: LENC Bit[0]: PRE C4-D2 RSVD XX – Reserved Table 12 Device Control Register List (when 0xFF = 00) (Sheet 2 of 4) Address (Hex) Register Name Default (Hex) R/W Description

20 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision D3 R_DVP_SP 82 RW Bit[7]: Auto mode Bit[6:0]: DVP output speed control DVP PCLK = sysclk (48)/[6:0] (YUV0); = sysclk (48)/(2*[6:0]) (RAW) D4-D9 RSVD XX – Reserved DA IMAGE_MODE 00 Image Output Format Select Bit[7]: Reserved Bit[6]: Y8 enable for DVP Bit[5]: Reserved Bit[4]: JPEG output enable 0: Non-compressed 1: JPEG output Bit[3:2]: DVP output format 00: YUV422 01: RAW10 (DVP) 10: RGB565 11: Reserved Bit[1]: HREF timing select in DVP JPEG output mode 0: HREF is same as sensor 1: HREF = VSYNC Bit[0]: Byte swap enable for DVP 0: High byte first YUYV (C2[4]=0) YVYU (C2[4] = 1) 1: Low byte first UYVY (C2[4] =0) VYUY (C2[4] =1) DB-DF RSVD XX – Reserved E0 RESET 04 RW Reset Bit[7]: Reserved Bit[6]: Microcontroller Bit[5]: SCCB Bit[4]: JPEG Bit[3]: Reserved Bit[2]: DVP Bit[1]: IPU Bit[0]: CIF E1-EF RSVD XX – Reserved F0 MS_SP 04 RW SCCB Master Speed F1-F6 RSVD XX – Reserved F7 SS_ID RW SCCB Slave ID Table 12 Device Control Register List (when 0xFF = 00) (Sheet 3 of 4) Address (Hex) Register Name Default (Hex) R/W Description

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 21 Omni ision F8 SS_CTRL 01 RW SCCB Slave Control Bit[7:6]: Reserved Bit[5]: Address auto-increase enable Bit[4]: Reserved Bit[3]: SCCB enable Bit[2]: Delay SCCB master clock Bit[1]: Enable SCCB master access Bit[0]: Enable sensor pass through access F9 MC_BIST RW Bit[7]: Microcontroller Reset Bit[6]: Boot ROM select Bit[5]: R/W 1 error for 12K-byte memory Bit[4]: R/W 0 error for 12K-byte memory Bit[3]: R/W 1 error for 512-byte memory Bit[2]: R/W 0 error for 512-byte memory Bit[1]: BIST busy bit for read; One-shot reset of microcontroller for write Bit[0]: Launch BIST FA MC_AL RW Program Memory Pointer Address Low Byte FB MC_AH RW Program Memory Pointer Address High Byte FC MC_D 80 RW Program Memory Pointer Access Address Boundary of register address to separate DSP and sensor register FD P_CMD 00 RW SCCB Protocol Command Register FE P_STATUS 00 RW SCCB Prot ocol Status Register FF RA_DLMT 7F RW Register Bank Select Bit[7:1]: Reserved Bit[0]: Register bank select 0: DSP address 1: Sensor address NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings. Table 12 Device Control Register List (when 0xFF = 00) (Sheet 4 of 4) Address (Hex) Register Name Default (Hex) R/W Description

22 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision Table 13 Device Control Register List (when 0xFF = 01) (Sheet 1 of 7) Address (Hex) Register Name Default (Hex) R/W Description

00 GAIN 00 RW

Bit[7:0]: Gain setting

• Range: 1x to 32x Gain =(Bit[7]+1) x (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16) Note: Set COM8[2] = 0 to disable AGC. 01-02 RSVD XX – Reserved

03 COM1

0F (UXGA) 0A (SVGA), 06 (CIF) RW Common Control 1 Bit[7:6]: Dummy frame control 00: Reserved 01: Allow 1 dummy frame 10: Allow 3 dummy frames 11: Allow 7 dummy frames Bit[5:4]: Reserved Bit[3:2]: Vertical window end line control 2 LSBs (8 MSBs in VEND[7:0] (0x1A)) Bit[1:0]: Vertical window start line control 2 LSBs (8 MSBs in VSTRT[7:0] (0x19))

04 REG04 20 RW

Bit[7]: Horizontal mirror Bit[6]: Vertical flip Bit[4]: VREF bit[0] Bit[3]: HREF bit[0] Bit[2]: Reserved Bit[1:0]: AEC[1:0] (AEC[15:10] is in register REG45[5:0] (0x45), AEC[9:2] is in register AEC[7:0] (0x10)) 05-07 RSVD XX – Reserved

08 REG08 40 RW Frame Exposure One-pin Control Pre-charge Row Number

09 COM2 00 RW

Bit[7:5]: Reserved Bit[4]: Standby mode enable 0: Normal mode 1: Standby mode Bit[3]: Reserved Bit[2]: Pin PWDN/RESETB used as SLVS/SLHS Bit[1:0]: Output drive select 00: 1x capability 01: 3x capability 10: 2x capability 11: 4x capability 0A PIDH 26 R Product ID Number MSB (Read only) 0B PIDL 41 R Product ID Number LSB (Read only)

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 23 Omni ision 0C COM3 38 RW Common Control 3 Bit[7:3]: Reserved Bit[2]: Set banding manually 0: 60 Hz 1: 50 Hz Bit[1]: Auto set banding Bit[0]: Snapshot option 0: Enable live video output after snapshot sequence 1: Output single frame only 0D COM4 07 RW Common Control 4 Bit[7:3]: Reserved Bit[2]: Clock output power-down pin status 0: Tri-state data output pin upon power-down 1: Data output pin hold at last state before power-down Bit[1:0]: Reserved 0E-0F RSVD XX – Reserved

10 AEC 33 RW

Automatic Exposure Control 8 bits for AEC[9:2] (AEC[15:10] is in register REG45[5:0] (0x45), AEC[1:0] is in register REG04[1:0] (0x04)) AEC[15:0]: Exposure time TEX = tLINE x AEC[15:0] Note: The maximum exposure time is 1 frame period even if TEX is longer than 1 frame period.

11 CLKRC 00 RW

Bit[7]: Internal frequency doublers ON/OFF selection 0: OFF 1: ON Bit[6]: Reserved Bit[5:0]: Clock divider CLK = XVCLK/(decimal value of CLKRC[5:0] + 1) Table 13 Device Control Register List (when 0xFF = 01) (Sheet 2 of 7) Address (Hex) Register Name Default (Hex) R/W Description

24 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision

12 COM7 00 RW

Bit[7]: SRST 1: Initiates system reset. All registers are set to factory default values after which the chip resumes normal operation Bit[6:4]: Resolution selection 000: UXGA (full size) mode 001: CIF mode 100: SVGA mode Bit[3]: Reserved Bit[2]: Zoom mode Bit[1]: Color bar test pattern 0: OFF 1: ON Bit[0]: Reserved

13 COM8 C7 RW

Bit[7:6]: Reserved Bit[5]: Banding filter selection 0: OFF 1: ON, set minimum exposure time to 1/120s Bit[4:3]: Reserved Bit[2]: AGC auto/manual control selection 0: Manual 1: Auto Bit[1]: Reserved Bit[0]: Exposure control 0: Manual 1: Auto

14 COM9 50 RW

Bit[7:5]: AGC gain ceiling, GH[2:0] 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 11x: 128x Bit[4:0]: Reserved Table 13 Device Control Register List (when 0xFF = 01) (Sheet 3 of 7) Address (Hex) Register Name Default (Hex) R/W Description

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 25 Omni ision

15 COM10 00 RW

Common Control 10 (if Bypass DSP is selected) Bit[7]: CHSYNC pin output swap 0: CHSYNC 1: HREF Bit[6]: HREF pin output swap 0: HREF 1: CHSYNC Bit[5]: PCLK output selection 0: PCLK always output 1: PCLK output qualified by HREF Bit[4]: PCLK edge selection 0: Data is updated at the falling edge of PCLK (user can latch data at the next rising edge of PCLK) 1: Data is updated at the rising edge of PCLK (user can latch data at the next falling edge of PCLK) Bit[3]: HREF output polarity 0: Output positive HREF 1: Output negative HREF, HREF negative for data valid Bit[2]: Reserved Bit[1]: VSYNC polarity 0: Positive 1: Negative Bit[0]: HSYNC polarity 0: Positive 1: Negative

16 RSVD XX – Reserved

17 HREFST 11 RW

Horizontal Window Start MSB 8 bits (3 LSBs in REG32[2:0] (0x32)) Bit[10:0]: Selects the start of the horizontal window, each LSB represents two pixels

18 HREFEND

75 (UXGA), 43 (SVGA, CIF) RW Horizontal Window End MSB 8 bits (3 LSBs in REG32[5:3] (0x32)) Bit[10:0]: Selects the end of the horizontal window, each LSB represents two pixels

19 VSTRT

01 (UXGA), 00 (SVGA, CIF) RW Vertical Window Line Start MSB 8 bits (2 LSBs in COM1[1:0] (0x03)) Bit[9:0]: Selects the start of the vertical window, each LSB represents two scan lines. 1A VEND 97 RW Vertical Window Line End MSB 8 bits (2 LSBs in COM1[3:2] (0x03)) Bit[9:0]: Selects the end of the vertical window, each LSB represents two scan lines. 1B RSVD XX – Reserved 1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F) 1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2) 1E-23 RSVD XX – Reserved Table 13 Device Control Register List (when 0xFF = 01) (Sheet 4 of 7) Address (Hex) Register Name Default (Hex) R/W Description

26 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision

24 AEW 78 RW

Luminance Signal High Range for AEC/AGC Operation AEC/AGC values will decrease in auto mode when average luminance is greater than AEW[7:0]

25 AEB 68 RW

Luminance Signal Low Range for AEC/AGC Operation AEC/AGC values will increase in auto mode when average luminance is less than AEB[7:0]

26 VV D4 RW

Fast Mode Large Step Range Threshold - effective only in AEC/AGC fast mode (COM8[7] = 1) Bit[7:4]: High threshold Bit[3:0]:Low threshold Note: AEC/AGC may change in larger steps when luminance average is greater than VV[7:4] or less than VV[3:0]. 27-29 RSVD XX – Reserved 2A REG2A 00 RW Register 2A Bit[7:4]: Line interval adjust value 4 MSBs (LSBs in FRARL[7:0] (0x2B)) Bit[3:2]: HSYNC timing end point adjustment MSB 2 bits (LSBs in register HEDY[7:0] (0x31)) Bit[1:0]: HSYNC timing start point adjustment MSB 2 bits (LSBs in register HSDY[7:0] (0x30)) 2B FRARL 00 RW Line Interval Adjustment Value LSB 8 bits (MSBs in REG2A[7:4] (0x2A)) The frame rate will be adjusted by changing the line interval. Each LSB will add 1/1922 Tframe in UXGA and 1/1190 Tframe in SVGA mode to te frame period. 2C RSVD XX – Reserved 2D ADDVSL 00 RW VSYNC Pulse Width LSB 8 bits Bit[7:0]: Line periods added to VSYNC width. Default VSYNC output width is 4 x tline. Each LSB count will add 1 x tline to the VSYNC active period. 2E ADDVSH 00 RW VSYNC Pulse Width MSB 8 bits Bit[7:0]: Line periods added to VSYNC width. Default VSYNC output width is 4 x tline. Each MSB count will add 256 x tline to the VSYNC active period. 2F YAVG 00 RW Luminance Average (this register will auto update) Average Luminance is calculated from the B/Gb/Gr/R channel average as follows: B/Gb/Gr/R channel average = (BAVG[7:0] + (2 x GbAVG[7:0]) + RAVG[7:0]) x 0.25

30 HSDY 08 RW

HSYNC Position and Width, Start Point LSB 8 bits This register and REG2A[1:0] (0x2A) define HSYNC start position, each LSB will shift HSYNC start by 2 pixel period Table 13 Device Control Register List (when 0xFF = 01) (Sheet 5 of 7) Address (Hex) Register Name Default (Hex) R/W Description

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 27 Omni ision

31 HEDY 30 RW

HSYNC Position and Width, End Point LSB 8 bits This register and REG2A[3:2] (0x2A) define HSYNC end position, each LSB will shift HSYNC end by 2 pixel period

32 REG32

36 (UXGA), 09 (SVGA, CIF) RW Common Control 32 Bit[7:6]: Pixel clock divide option 00: No effect on PCLK 01: No effect on PCLK 10: PCLK frequency divide by 2 11: PCLK frequency divide by 4 Bit[5:3]: Horizontal window end position 3 LSBs (8 MSBs in register HREFEND[7:0] (0x18)) Bit[2:0]: Horizontal window start position 3 LSBs (8 MSBs in register HREFST[7:0] (0x17))

33 RSVD XX – Reserved

34 ARCOM2 20 RW

Bit[7:3]: Reserved Bit[2]: Zoom window horizontal start point Bit[1:0]: Reserved 35-44 RSVD XX – Reserved

45 REG45 00 RW

Bit[7:6]: AGC[9:8], AGC highest gain control Bit[5:0]: AEC[15: 10], AEC MSBs

46 FLL 00 RW Frame Length Adjustment LSBs

Each bit will add 1 horizontal line timing in frame

47 FLH 00 RW Frame Length Adjustment MSBs

Each bit will add 256 horizontal lines timing in frame

48 COM19 00 RW

Bit[7:2]: Reserved Bit[1:0]: Zoom mode vertical window start point 2 LSBs

49 ZOOMS 00 RW Zoom Mode Vertical Window Start Point 8 MSBs

4A RSVD XX – Reserved 4B COM22 20 RW Common Control 22 Bit[7:0]: Flash light control 4C-4D RSVD XX – Reserved 4E COM25 00 RW Common Control 25 - reserved for banding Bit[7:6]: 50Hz Banding AEC 2 MSBs Bit[5:4]: 60HZ Banding AEC 2 MSBs Bit[3:0]: Reserved 4F BD50 CA RW 50Hz Banding AEC 8 LSBs

50 BD60 A8 RW 60Hz Banding AEC 8 LSBs

51-5C RSVD XX – Reserved Table 13 Device Control Register List (when 0xFF = 01) (Sheet 6 of 7) Address (Hex) Register Name Default (Hex) R/W Description

28 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision 5D REG5D 00 RW Register 5D Bit[7:0]: AVGsel[7:0], 16-zone average weight option 5E REG5E 00 RW Register 5E Bit[7:0]: AVGsel[15:8], 16-z one average weight option 5F REG5F 00 RW Register 5F Bit[7:0]: AVGsel[23:16], 16-zone average weight option

60 REG60 00 RW Register 60

Bit[7:0]: AVGsel[31:24], 16-zone average weight option

61 HISTO_LOW 80 RW Histogram Algorithm Low Level

62 HISTO_HIGH 90 RW Histogram Algorithm High Level

63-7E RSVD XX – Reserved NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings. Table 13 Device Control Register List (when 0xFF = 01) (Sheet 7 of 7) Address (Hex) Register Name Default (Hex) R/W Description

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 29 Omni ision Package Specifications The OV2640 uses a 38-ball Chip Scale Package 2 (CSP2). Refer to Figure 11 for package information, Table 9 for package dimensions and Figure 12 for the array center on the chip. Figure 21 OV2640 Package Specifications Note: For OVT devices that are lead-free, all part marking letters are lower case. Underlining the last digit of the lot number indicates CSP2 is used. Table 14 OV2640 Package Dimensions Parameter Symbol Minimum Nominal Maximum Unit Package Body Dimension X A 5700 5725 5750 µm Package Body Dimension Y B 6260 6285 6310 µm Package Height C 845 905 965 µm Ball Height C1 150 180 210 µm Package Body Thickness C2 680 725 770 µm Cover Glass Thickness C3 375 400 425 µm Airgap Between Cover Glass and Sensor C4 30 45 60 µm Ball Diameter D 320 350 380 µm Total Pin Count N 38 (1 NC) Pin Count X-axis N1 6 Pin Count Y-axis N2 7 Pins Pitch X-axis J1 800 µm Pins Pitch Y-axis J2 800 µm Edge-to-Pin Center Distance Analog X S1 833 863 893 µm Edge-to-Pin Center Distance Analog Y S2 713 743 773 µm Center of BGA (die) = Center of the package Top View (Bumps Down) C4Side View Die Glass B A D C E F S1 J1 A B 15 6 234 Bottom View (Bumps Up) Part Marking Code: w x y z abcd OVT Product Version Year the part is assembled Month the part is assembled Wafer number Last four digits of lot number 62 1 543 C G B A D C E F G abcd wxyz

30 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision Sensor Array Center Figure 22 OV2640 Sensor Array Center 2684 μm Array Cent er (469.6 μm, 145 μm) Se n so r Array Top View A1 A6 A5A4A3A2 Packag e Ce n t e r (0, 0) OV2640 NOTES: 1. Th i s d r aw i n g i s n o t t o scal e an d i s f o r r ef er en ce o n l y . 2. As mos t optica l a s s emblies invert a nd mirror the ima ge, the chip is typica lly mounted wit h pins A1 t o A6 orient ed down on t he P C B. 3590.4 μm

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 31 Omni ision IR Reflow Ramp Rate Requirements OV2640 Lead-Free Packaged Devices Figure 23 IR Reflow Ramp Rate Requirements Note: For OVT devices that are lead-free, all part marking letters are lower case Table 15 Reflow Conditions Condition Exposure Average Ramp-up Rate (30°C to 217°C) Less than 3°C per second > 100°C Between 330 - 600 seconds > 150°C At least 210 seconds > 217°C At least 30 seconds (30 ~ 120 seconds) Peak Temperature 245°C Cool-down Rate (Peak to 50°C) Less than 6°C per second Time from 30°C to 245°C No greater than 390 seconds -22 -2 18 38 58 78 98 118 138 158 178 198 218 238 258 278 298 318 36 9338 358 20.0 40.0 60.0 80.0 100.0 120.0 140.0 160.0 180.0 200.0 220.0 240.0 260.0 280.0 300.0 Temperature ( C) Time (sec) endZ7Z6Z5Z4Z3Z2Z1

32 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006 OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Omni ision Note:

• All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation.
• OmniVision Technologies, Inc. reserves the ri ght to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders).
• Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced.
• This document is provided with no warrant ies whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein.
• ‘OmniVision’, ‘VarioPixel’, and ’OmniPixel2’ are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners. For further information, please feel free to contact OmniVision at info@ovt.com. OmniVision Technologies, Inc.

1341 Orleans Drive

Sunnyvale, CA USA (408) 542-3000

Document Title: OV2640 Datasheet Version: 1.0 DESCRIPTION OF CHANGES Initial Release

Document Title: OV2640 Datasheet Version: 1.01 DESCRIPTION OF CHANGES The following changes were made to version 1.0:

• Under Key Specifications on page 1, changed specification for Core Power Supply from “1.2VDC + 10%” to “1.2VDC + 5%”
• Under Key Specifications on page 1, change d specification for Analog Power Supply from “2.8VDC + 10%” to “2.5 ~ 3.0VDC”
• Under Key Specifications on page 1, changed specification for I/O Power Supply from “1.8V to 3.3V” to “1.7V to 3.3V”
• On pages 17 to 20, changed title of Table 12 from “Device Control Register (for 0x00 ~ 0xFF at 0xF8 = 00 and 0xFF = 00)” to “Device Control Register (when 0xFF = 00)”
• On pages 21 to 27, changed title of Table 13 from “Device Control Register (for 0x00 ~ 0x7E at 0xF8 = 01 and 0xFF = 7F)” to “Device Control Register (when 0xFF = 01)”
• In Table 12 on pages 18, changed descript ion of register CTRL3 (0x87) from: Module Enable Bit[7:6]: Reserved Bit[5]: DCW Bit[4]: SDE Bit[3]: UV_ADJ Bit[2]: UV_AVG Bit[1]: Reserved Bit[0]: CMX to Module Enable Bit[7]: BPC Bit[6]: WPC Bit[5:0]: Reserved
• In Table 15 on page 30, changed specification for Peak Temperature from “Greater than 245°C” to “245°C”

Document Title: OV2640 Datasheet Version: 1.1 DESCRIPTION OF CHANGES The following changes were made to version 1.01:

• Under Features on page 1, changed bullete d item from “Supports image sizes: UXGA, SVGA, and any size scaling down from SVGA to 40x30” to “Supports image sizes: UXGA, SXGA, SVGA, and any size scaling down from SXGA to 40x30”
• Under Key Specifications on pa ge 1, deleted specifications for SVGA and CIF Array Size
• Under Key Specifications on page 1, change d Standby Power Requirements specification to “TBD”
• Under Key Specifications on page 1, changed specification for Chief Ray Angle from “TBD” to “25° non-linear”
• Under Key Specifications on page 1, changed specification for Well Capacity from “TBD” to “12 Ke”
• Under Electrical Characteristics on page 10, changed title of Table 6 from “DC Characteristics (-20°C < TA < 70°C)” to “DC Characteristics (-30°C < TA < 70°C)”
• In Table 6 on page 10, changed specificati on for Typ Standby Current from “10” to “TBD”
• In Table 6 on page 10, changed specifi cation for Max Input voltage LOW (VIL) from “0.8” to “0.54”
• In Table 6 on page 10, changed specific ation for Min Input voltage HIGH (VIH) from “2” to “1.26”
• In Table 6 on page 10, changed subtitle “Dig ital Outputs (standard loading 25 pF, 1.2 KΩ to 2.8V)” to “Digital Outputs (standard loading 25 pF)”
• In Table 6 on page 10, changed specificat ion for Min Output voltage HIGH (VOH) from “2.2” to “1.62”
• In Table 6 on page 10, changed specifi cation for Max Output voltage LOW (VOL) from “0.6” to “0.18”
• In Table 6 on page 10, changed specification for Serial Interface Inputs Max SIO_C and SIO_D (VIL) from “1” to “0.54”
• In Table 6 on page 10, changed specification for Serial Interface Inputs Min, Typ, and respectively
• In Table 6 on page 10, change d table footnote b from “...VDD-IO = 2.8V” to “...VDD-IO = 1.8V”

DESCRIPTION OF CHANGES (CONTINUED)

• In Figure 21 on page 28, changed callout C3 to measure from thickness of glass and added callout C4 to measure airgap from glass to die.
• In Table 14 on page 28, changed C3 parameter na me from “Thickness of Glass Surface to Wafer” to “Cover Glass Thickness”
• In Table 14 on page 28, changed C3 Minimu m, Nominal, and Maximum specifications from “425, 445, and 465” to “375, 400, and 425”
• In Table 14 on page 28, added C4 parameter, Airgap Between Cover Glass and Sensor, and Minimum, Nominal, and Maximum specifications “30, 45, and 60”, respectively

Document Title: OV2640 Datasheet Version: 1.2 DESCRIPTION OF CHANGES The following changes were made to version 1.1:

• Under Key Specifications on pa ge 1, changed Active Power Requirements specification to “TBD” to “125 mW (for 15 fps, UXGA YUV mode)” and “140 mW (for 15 fps, UXGA compressed mode)”
• Under Key Specifications on page 1, change d Standby Power Requirements specification to “TBD” to “600 µA”
• Under Key Specifications on page 1, dele ted Preview (CIF) Power Requirements specification
• In Table 6 on page 10, changed specificati on for Typ Active (Operating) Current (IDDA-A) from “TBD” to “30”
• In Table 6 on page 10, changed specificati on for Typ Active (Operating) Current (IDDA-D) from “TBD” to “25 (YUV)” and “35 (Compressed)”
• In Table 6 on page 10, changed specificati on for Typ Active (Operating) Current (IDDA- IO) from “TBD” to “6”
• IIn Table 6 on page 10, cha nged specification for Typ Standby Current from “10” to “600”
• In Table 6 on page 10, change d table footnote b from “...VDD-IO = 1.8V” to “...VDD-IO = 1.8V for 15 fps in UXGA mode”

Document Title: OV2640 Datasheet Version: 1.21 DESCRIPTION OF CHANGES The following changes were made to version 1.2:

• In Figure 1 on page 21, correc ted the bottom view of the package by correcting the column numbers corresponding to the ball locations from (left to right) “1”, “2”, “3”, “4”, “5”, and “6” to (left to right) “6”, “5”, “4”, “3”, “2”, and “1”, respectively

Document Title: OV2640 Datasheet Version: 1.3 DESCRIPTION OF CHANGES The following changes were made to version 1.21:

• In Table 1 on page 8, made the following changes/corrections: – Corrected pin type of pin A1 from Power to Ground – Corrected pin type of pin A2 from I/O to Input and added “Note: There is no internal pull-up/pull-down resistor” – Corrected pin type of pin A3 from Power to Ground – Corrected pin type of pin A4 from Power to Ground – Corrected pin type of pin A5 from I/O to Reference – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pin A6 – Corrected pin type of pin B2 from Powe r to Input and added “Note: There is no internal pull-up/pull-down resistor” – Corrected pin type of pin B3 from Input to Power – Corrected pin type of pin B4 from I/O to Power – Corrected pin type of pin B5 from Input to Power – Corrected pin type of pin B6 from I/O to Input and “Note: There is an internal pull- down resistor” – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pin C3 – Added “Note: There is no inte rnal pull-up/pull-down resistor” to description of pin C4 – Added “Note: There is an internal pul l-up resistor” to description of pin C6 – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pin D2 – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pin E1 – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pin E2 – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pin E3 – Corrected pin type of pi n E4 from Power to Ground – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pin E5 – Corrected pin type of pi n E6 from Power to Ground

DESCRIPTION OF CHANGES (CONTINUED)

• In Table 1 on page 8, made the following changes/corrections: – Corrected pin type of pin F2 from An alog to Power and changed description to “Sensor digital power (Core)” – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pins F3, F4, and F5 – Corrected pin type of pin F6 from Analog to Power and changed description to be the same as pin F2 – Corrected pin type of pin G2 from Power to Ground – Added “Default: Input” and “Not e: There is no internal pull-up/pull-down resistor” to description of pins G3, G4, G5, and G6

Document Title: OV2640 Datasheet Version: 1.4 DESCRIPTION OF CHANGES The following changes were made to version 1.3:

• In Table 6 on page 11, made the following changes: – Added “40 mA” for Maximu m specification of IDDA-A – Added “35 mA (YUV)” and “50 mA (Compr essed)” for Maximum specification of IDDA-D – Added “10 mA” for Maximu m specification of IDDA-IO – Added “2 mA” for Maximum specification of I DDS-SCCB – Added “1200 µA” for Maximum specification of I DDS-PWDN

Document Title: OV2640 Datasheet Version: 1.5 DESCRIPTION OF CHANGES The following changes were made to version 1.4:

• Under Register Set section on page 18, changed the second paragraph from “There are two different sets for register address from 0x00 to 0x7E. Both register 0xF8 and register 0xFF control which set is accessible. When 0xF8=00 and 0xFF=00, Table 12 is effective. When 0xF8=01, 0xFF=7F, Table 13 is effective.” to “There are two different sets of register banks. Register 0xFF controls which set is accessible. When register 0xFF=00, Table 12 is effective. When register 0xFF=01, Table 13 is effective.”

Document Title: OV2640 Datasheet Version: 1.6 DESCRIPTION OF CHANGES The following changes were made to version 1.5:

• In Table 12 on page 18, changed name, defau lt, R/W, and description of register 0x44 from “RSVD”, “XX”, “–”, and “Reserved” to “Qs”, “0C”, “RW”, and “Quantization Scale Factor”
• In Table 12 on page 21, changed descript ion of register RA_DLMT (0xFF) from: Sensor/Device Register Address Delimiter <(value of register 0xFF): Sensor address (value of register 0xFF): DSP address to: Register Bank Select Bit[7:1]: Reserved Bit[0]: Register bank select 0: DSP address 1: Sensor address
• In Table 13 on page 22, changed defau lt value for register REG08 (0x08) from “00” to “40”
• In Table 13 on page 22, changed descripti on of register bits COM2[1:0] (0x09) from: 00: Weakest 01: Double capability 10: Double capability 11: Triple drive capability to: 00: 1x capability 01: 3x capability 10: 2x capability 11: 4x capability
• In Table 13 on page 22, changed defau lt value for register PIDL (0x0B) from “40” to “41”
• In Table 13 on page 23, changed descripti on of register bit CLKRC[6] (0x11) to “Reserved”
• In Table 13 on page 25, added “(if Bypass DSP is selected)” to description of register COM10 (0x15)