OPT9221

Time-of-Flight Controller (Rev. A)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SBAS703,A]
• PDF pages: 104

Technical content

I2C Master, Slave Controller Output Interface Module Data, Clock DVP, SSI VD_IN GPOs Slave I2C Flow Control Master I2C Configuration TIC_MS (4 Lines) OPT9221 Temperature Compensation SYSCLK_IN VD, CLK, Reset, I2C Control Temperature Compensation From Illumination To OPT8241 From OPT8241 To DDR To Optional EEPROM To Optional Temperature Sensor To Host IOVDD 1.8 V, 2.5 V, 3.3 V VCCINT 1.2 V VCCD_PLL 1.2 V VCCA 2.5 V Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community OPT9221 SBAS703A – JUNE 2015– REVISED JUNE 2015 OPT9221Time-of-FlightController

1 Features 2 Applications

1• QVGA 3D ToF Controller: Up to 120 FPS • 3D Imaging:

• Depth Data: – Location and Proximity Sensing – 12-Bit Phase – 3D Scanning and 3D Machine Vision – Up to 12-Bit Amplitude – Security and Surveillance – Up to 4-Bit Ambient – Gesture Controls – Saturation Detection

3 Description• Chipset Interface:

The time-of-flight controller (TFC) is a high-– Compatible with TI ToF Sensor (OPT8241) performance, 3D time-of-flight (ToF) sensor

• Output (CMOS, 8-Lane Data, 8 Control Signals, companion device that computes the depth data from and Clock): the digitized sensor data. Depth data are output via a programmable complementary metal-oxide-– Digital Video Protocol (DVP)-Compatible: semiconductor (CMOS) parallel interface.– Data, VD, HD, Clock In addition to depth data, the TFC provides auxiliary– Synchronous Serial Interface (SSI)-Compatible information consisting of amplitude, ambient, and• Depth Engine: flags for each pixel. This information can be used to – Pixel Binning implement filters and masks and to dynamically control the system configuration for the intended– Region of Interest (ROI) performance.– De-Aliasing The TFC supports a wide range of binning and ROI– Non-linearity Correction options that help optimize the data throughput that– Temperature Compensation must be handled. – High Dynamic Range Operation The 9-mm × 9-mm NFBGA package enables small– Spatial Filter form-factor, 3D, ToF systems that can be embedded
• Timing Coordinator: into a variety of end equipment. – Sensor Control Device Information(1) – Master and Slave Sync Operation PART NUMBER PACKAGE BODY SIZE (NOM)
• I2C Slave Interface OPT9221 NFBGA (256) 9.00 mm × 9.00 mm
• Power Supply: 1.2-V Core, 1.8-V I/O, 3.3-V I/O (1) For all available packages, see the orderable addendum at2.5-V Analog the end of the datasheet.
• Package: 256-Pin, 9-mm × 9-mm NFBGA
• Operating Temperature: 0°C to 85°C Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com Table of Contents

4 Revision History

Changes from Original (June 2015) to Revision A Page

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E F G H J K L M N P R T VCCIO8 GPO_3 GPO_2 GPO_0 TIC_DATA_7 RSVD VD_IN RSVD_IN RSVD_IN VD_QD HD_QD VD_SF VD_FR SENSOR_DEMOD _CLK VSYNC_OUT VCCIO7 SLEEP GND GPO_1 RSVD RSVD RSVD TIC_DATA_4 RSVD_IN RSVD_IN RSVD RSVD RSVD RSVD SENSOR_CLK GND ILLUM_FB TIC_DATA_1/A SDO RESETZ RSVD VCCIO8 GND RSVD VCCIO8 I2C_MAS_SDA I2C_SDA_SENS OR VCCIO7 RSVD GND VCCIO7 RSVD ILLUM_SW_2 ILLUM_SW_1 DEBUG TIC_CSOZ RSVD VCCD_PLL3 RSVD RSVD GND I2C_MAS_SCL I2C_SCL_SENS OR GND RSVD RSVD VCCD_PLL2 SENSOR_RSTZ RSVD RSVD SYSCLK_IN GND VCCIO1 GND GNDA3 TIC_DATA_6 TIC_DATA_5 TIC_DATA_2 GPI_1 RSVD RSVD GNDA2 GND VCCIO6 ILLUM_MOD_FB COMP_MOD_FB I2C_SLV_SCL I2C_SLV_SDA RSVD TIC_STATUSZ VCCA3 GND VCCINT TIC_DATA_3 GPI_0 GND VCCINT VCCA2 ILLUM_REF RSVD IO_MOD_REF COMP_MOD_REF RSVD INT_OUT VCCIO1 GND INT_PMIC VCCINT VCCINT VCCINT VCCINT VCCINT RSVD BOOT_2 GND VCCIO6 RSVD TIC_INIT_DON E TIC_CLK TIC_DATA_0 TIC_C TIC_I TIC_CONFIGZ VCCINT GND GND GND GND VCCINT BOOT_1 BOOT_0 TIC_CONF_DON E GND GND RSVD HD/BD TIC_CEZ TIC_O TIC_S VCCINT GND GND GND GND GND RSVD RSVD RSVD CAP_DATA_SUM CAP_DATA_SUM VD PHASE_AUX VCCIO2 GND OP_CLK OP_CS VCCINT GND DDR2_ADDR_3 DDR2_ADDR_2 VCCINT RSVD GND VCCIO5 CAP_DATA_DIF F_1P CAP_DATA_DIF F_1M OP_DATA_5 OP_DATA_6 OVERFLOW OP_DATA_7 VCCA1 FE DDR2_DQ_0 DDR2_DQ_7 DDR2_ADDR_1 DDR2_ADDR_6 DDR2_ADDR_0 VCCA4 RSVD RSVD_IN RSVD_IN RSVD READY RSVD_IN VCCIO2 GND GNDA1 RSVD DDR2_DQS_0 DDR2_DM_1 DDR2_ADDR_5 DDR2_ADDR_11 DDR2_ADDR_4 GNDA4 GND VCCIO5 CAP_BIT_CLKP CAP_BIT_CLKM OP_DATA_3 OP_DATA_4 DDR2_ADDR_10 VCCD_PLL1 DDR2_DQ_1 DDR2_DQ_3 GND DDR2_DQ_14 DDR2_DQ_9 GND DDR2_ADDR_8 DDR2_REF_3 VCCD_PLL4 RSVD CAP_DATA_DIF F_0P CAP_DATA_DIF F_0M OP_DATA_1 OP_DATA_2 DDR2_DM_0 VCCIO3 GND DDR2_REF_1 VCCIO3 DDR2_DQ_12 DDR2_ADDR_9 VCCIO4 DDR2_REF_2 GND VCCIO4 DDR2_CLKz_0 RSVD CAP_FRM_CLKM OP_DATA_0 GND DDR2_DQ_6 DDR2_BA_0 DDR2_DQ_4 DDR2_DQ_2 DDR2_DQ_5 RSVD_IN RSVD_IN DDR2_DQ_11 DDR2_DQ_10 DDR2_DQ_8 DDR2_CSZ DDR2_CLK_0 GND CAP_FRM_CLKP VCCIO3 DDR2_CKE DDR2_REF_0 DDR2_BA_1 DDR2_ADDR_12 DDR2_ADDR_7 DDR2_DQS_1 RSVD_IN RSVD_IN DDR2_WEZ DDR2_CASZ DDR2_RASZ DDR2_DQ_15 DDR2_DQ_13 DDR2_ODT_0 VCCIO4 OPT9221 www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015

5 Pin Configuration and Functions

PIN I/OI/O I/O BANK DESCRIPTIONSTANDARDNAME NO. BOOT_0 H13 Input 2.5 V – Boot configuration pin 0. Tie to VCC or to GND. BOOT_1 H12 Input 2.5 V – Boot configuration pin 1. Tie to VCC or to GND. BOOT_2 G12 Input 2.5 V – Boot configuration pin 2. Tie to VCC or to GND. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: OPT9221

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN I/OI/O I/O BANK DESCRIPTIONSTANDARDNAME NO. CAP_BIT_CLKM M16 Input LVDS VCCIO5 Sensor data bit clk CAP_BIT_CLKP M15 Input LVDS VCCIO5 Sensor data bit clk CAP_DATA_DIFF_0M N16 Input LVDS VCCIO5 Sensor differential data ch 0 CAP_DATA_DIFF_0P N15 Input LVDS VCCIO5 Sensor differential data ch 0 CAP_DATA_DIFF_1M K16 Input LVDS VCCIO5 Sensor differential data ch 1 CAP_DATA_DIFF_1P K15 Input LVDS VCCIO5 Sensor differential data ch 1 CAP_DATA_SUM_M J16 Input LVDS VCCIO5 Sensor common mode data CAP_DATA_SUM_P J15 Input LVDS VCCIO5 Sensor common mode data CAP_FRM_CLKM P16 Input LVDS VCCIO5 Sensor sample clk CAP_FRM_CLKP R16 Input LVDS VCCIO5 Sensor sample clk Feedback signal from the external illumination modulationCOMP_MOD_FB E16 Input 3.3 V VCCIO6 feedback comparator. Reference modulation signal for measuring externalCOMP_MOD_REF F16 Output 3.3 V VCCIO6 illumination modulation feedback comparator delay. SSTL-18DDR2_ADDR_0 L11 Output VCCIO4 DDR address signal 0Class I SSTL-18DDR2_ADDR_1 L9 Output VCCIO4 DDR address signal 1Class I SSTL-18DDR2_ADDR_2 K10 Output VCCIO4 DDR address signal 2Class I SSTL-18DDR2_ADDR_3 K9 Output VCCIO4 DDR address signal 3Class I SSTL-18DDR2_ADDR_4 M11 Output VCCIO4 DDR address signal 4Class I SSTL-18DDR2_ADDR_5 M9 Output VCCIO4 DDR address signal 5Class I SSTL-18DDR2_ADDR_6 L10 Output VCCIO4 DDR address signal 6Class I SSTL-18DDR2_ADDR_7 T6 Output VCCIO3 DDR address signal 7Class I SSTL-18DDR2_ADDR_8 N11 Output VCCIO4 DDR address signal 8Class I SSTL-18DDR2_ADDR_9 P9 Output VCCIO4 DDR address signal 9Class I SSTL-18DDR2_ADDR_10 N3 Output VCCIO3 DDR address signal 10Class I SSTL-18DDR2_ADDR_11 M10 Output VCCIO4 DDR address signal 11Class I SSTL-18DDR2_ADDR_12 T5 Output VCCIO3 DDR address signal 12Class I SSTL-18DDR2_BA_0 R4 Output VCCIO3 DDR bank signalClass I SSTL-18DDR2_BA_1 T4 Output VCCIO3 DDR bank signalClass I SSTL-18DDR2_CASZ T11 Output VCCIO4 DDR CASClass I SSTL-18DDR2_CKE T2 Output VCCIO3 DDR clock enableClass I SSTL-18DDR2_CLK_0 R14 Output VCCIO4 DDR clockClass I SSTL-18DDR2_CLKz_0 P14 Output VCCIO4 DDR clockClass I

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www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015 Pin Functions (continued) PIN I/OI/O I/O BANK DESCRIPTIONSTANDARDNAME NO. SSTL-18DDR2_CSZ R13 Output VCCIO4 DDR chip selectClass I SSTL-18DDR2_DM_0 P3 Output VCCIO3 DDR data mask 0Class I SSTL-18DDR2_DM_1 M8 Output VCCIO3 DDR data mask 1Class I SSTL-18DDR2_DQ_0 L7 Bidir VCCIO3 DDR data 15Class I SSTL-18DDR2_DQ_1 N5 Bidir VCCIO3 DDR data 14Class I SSTL-18DDR2_DQ_2 R6 Bidir VCCIO3 DDR data 13Class I SSTL-18DDR2_DQ_3 N6 Bidir VCCIO3 DDR data 12Class I SSTL-18DDR2_DQ_4 R5 Bidir VCCIO3 DDR data 11Class I SSTL-18DDR2_DQ_5 R7 Bidir VCCIO3 DDR data 10Class I SSTL-18DDR2_DQ_6 R3 Bidir VCCIO3 DDR data 9Class I SSTL-18DDR2_DQ_7 L8 Bidir VCCIO3 DDR data 8Class I SSTL-18DDR2_DQ_8 R12 Bidir VCCIO4 DDR data 7Class I SSTL-18DDR2_DQ_9 N9 Bidir VCCIO4 DDR data 6Class I SSTL-18DDR2_DQ_10 R11 Bidir VCCIO4 DDR data 5Class I SSTL-18DDR2_DQ_11 R10 Bidir VCCIO4 DDR data 4Class I SSTL-18DDR2_DQ_12 P8 Bidir VCCIO3 DDR data 3Class I SSTL-18DDR2_DQ_13 T14 Bidir VCCIO4 DDR data 2Class I SSTL-18DDR2_DQ_14 N8 Bidir VCCIO3 DDR data 1Class I SSTL-18DDR2_DQ_15 T13 Bidir VCCIO4 DDR data 0Class I SSTL-18DDR2_DQS_0 M7 Output VCCIO3 DDR data strobeClass I SSTL-18DDR2_DQS_1 T7 Output VCCIO3 DDR data strobeClass I SSTL-18DDR2_ODT_0 T15 Bidir VCCIO4 DDR on die terminationClass I SSTL-18DDR2_RASZ T12 Output VCCIO4 DDR RASClass I DDR2_REF_0 T3 Input Analog – DDR reference, tie to 0.9 V DDR2_REF_1 P6 Input Analog – DDR reference, tie to 0.9 V DDR2_REF_2 P11 Input Analog – DDR reference, tie to 0.9 V DDR2_REF_3 N12 Input Analog – DDR reference, tie to 0.9 V SSTL-18DDR2_WEZ T10 Output VCCIO4 DDR write enableClass I DEBUG D1 Bidir 1.8 V VCCIO1 TI proprietary debug port. Pullup by 10 kΩ. FE L6 Output 1.8 V VCCIO2 Marks the end of a frame Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: OPT9221

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN I/OI/O I/O BANK DESCRIPTIONSTANDARDNAME NO. GND B2 Power – – Digital ground GND B15 Power – – Digital ground GND C5 Power – – Digital ground GND C12 Power – – Digital ground GND D7 Power – – Digital ground GND D10 Power – – Digital ground GND E2 Power – – Digital ground GND E4 Power – – Digital ground GND E13 Power – – Digital ground GND F6 Power – – Digital ground GND F10 Power – – Digital ground GND G4 Power – – Digital ground GND G13 Power – – Digital ground GND H7 Power – – Digital ground GND H8 Power – – Digital ground GND H9 Power – – Digital ground GND H10 Power – – Digital ground GND H15 Power – – Digital ground GND H16 Power – – Digital ground GND J7 Power – – Digital ground GND J8 Power – – Digital ground GND J9 Power – – Digital ground GND J10 Power – – Digital ground GND J11 Power – – Digital ground GND K4 Power – – Digital ground GND K8 Power – – Digital ground GND K13 Power – – Digital ground GND M4 Power – – Digital ground GND M13 Power – – Digital ground GND N7 Power – – Digital ground GND N10 Power – – Digital ground GND P5 Power – – Digital ground GND P12 Power – – Digital ground GND R2 Power – – Digital ground GND R15 Power – – Digital ground GNDA1 M5 Power – – Analog ground GNDA2 E12 Power – – Analog ground GNDA3 E5 Power – – Analog ground GNDA4 M12 Power – – Analog ground GPI_0 F9 Input 1.8 V VCCIO7 Sensor general purpose pin GPI_1 E9 Input 1.8 V VCCIO7 Sensor general purpose pin GPO_1 B3 Output 1.8 V VCCIO8 General purpose output GPO_2 A3 Output 1.8 V VCCIO8 General purpose output GPO_3 A2 Output 1.8 V VCCIO8 General purpose output GPO_0 A4 Output 1.8 V VCCIO8 General purpose output HD/BD J2 Output 1.8 V VCCIO2 Indicates the row boundary or block boundary

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www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015 Pin Functions (continued) PIN I/OI/O I/O BANK DESCRIPTIONSTANDARDNAME NO. HD_QD A11 Input 1.8 V VCCIO7 Sensor HD ILLUM_FB B16 Input 3.3 V VCCIO6 Comparator output feedback to TFC Illumination modulation signal input. Connect toILLUM_MOD_FB E15 Input 3.3 V VCCIO6 ILLUM_P/M of the OPT8241 sensor. ILLUM_REF F13 Output 3.3 V VCCIO6 Comparator reference signal ILLUM_SW_1 C16 Output 3.3 V VCCIO6 DCDC control signal 1 ILLUM_SW_2 C15 Output 3.3 V VCCIO6 DCDC control signal 2 INT_OUT G2 Output 1.8 V VCCIO1 Interrupt to external host INT_PMIC G5 Input 1.8 V VCCIO1 Interrupt from PMIC Reference modulation signal from the TFC for measuringIO_MOD_REF F15 Output 3.3 V VCCIO6 TFC I/O delay I2C_MAS_SCL D8 Output 1.8 V VCCIO8 I2C master clk I2C_MAS_SDA C8 Bidir 1.8 V VCCIO8 I2C master data I2C_SCL_SENSOR D9 Output 1.8 V VCCIO7 Dedicated I2C for sensor - clock I2C_SDA_SENSOR C9 Bidir 1.8 V VCCIO7 Dedicated I2C for sensor - data I2C_SLV_SCL F1 Input 1.8 V VCCIO1 I2C slave clk I2C_SLV_SDA F2 Bidir 1.8 V VCCIO1 I2C slave data OP_CLK K5 Output 1.8 V VCCIO2 Output data clock Indicates the validity of the data output. Useful for SPIOP_CS K6 Output 1.8 V VCCIO2 mode. OP_DATA_0 R1 Output 1.8 V VCCIO2 Output data bit 0 OP_DATA_1 P1 Output 1.8 V VCCIO2 Output data bit 1 OP_DATA_2 P2 Output 1.8 V VCCIO2 Output data bit 2 OP_DATA_3 N1 Output 1.8 V VCCIO2 Output data bit 3 OP_DATA_4 N2 Output 1.8 V VCCIO2 Output data bit 4 OP_DATA_5 L1 Output 1.8 V VCCIO2 Output data bit 5 OP_DATA_6 L2 Output 1.8 V VCCIO2 Output data bit 6 OP_DATA_7 L4 Output 1.8 V VCCIO2 Output data bit 7 OVERFLOW L3 Input 1.8 V VCCIO2 Used to indicate failure in flow control. PHASE_AUX K2 Output 1.8 V VCCIO2 Indicates the type of data on the output bus. READY M1 Input 1.8 V VCCIO2 Used to achieve flow control of the output data. RESETZ C2 Input 1.8 V VCCIO1 Global reset for the TFC RSVD A6 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected. RSVD B4 Bidir 3.3 V VCCIO6 Leave unconnected RSVD B5 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected. RSVD B6 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected. RSVD B10 Bidir 1.8 V VCCIO7 Leave unconnected RSVD B11 Bidir 1.8 V VCCIO7 Leave unconnected RSVD B12 Bidir 1.8 V VCCIO7 Leave unconnected RSVD B13 Bidir 1.8 V VCCIO7 Leave unconnected RSVD C3 Bidir 1.8 V VCCIO8 Leave unconnected RSVD C6 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected. RSVD C11 Bidir 1.8 V VCCIO7 Leave unconnected RSVD C14 Bidir 1.8 V VCCIO7 Leave unconnected RSVD D3 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected. RSVD D5 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected. RSVD D6 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: OPT9221

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN I/OI/O I/O BANK DESCRIPTIONSTANDARDNAME NO. RSVD D11 Bidir 1.8 V VCCIO7 Leave unconnected RSVD D12 Bidir 1.8 V VCCIO7 Leave unconnected RSVD D15 Bidir 3.3 V VCCIO6 Leave unconnected RSVD D16 Bidir 3.3 V VCCIO6 Leave unconnected RSVD E10 Bidir 1.8 V VCCIO7 Leave unconnected RSVD E11 Bidir 1.8 V VCCIO7 Leave unconnected RSVD F3 Bidir 1.8 V VCCIO1 Leave unconnected RSVD F14 Bidir 3.3 V VCCIO6 Leave unconnected RSVD G1 Bidir 1.8 V VCCIO1 Leave unconnected RSVD G11 Bidir 3.3 V VCCIO6 Leave unconnected RSVD G15 Bidir 3.3 V VCCIO6 Leave unconnected RSVD J1 Output 1.8 V VCCIO2 Reserved RSVD J12 Bidir 2.5 V VCCIO5 Leave unconnected RSVD J13 Bidir 2.5 V VCCIO5 Leave unconnected RSVD J14 Bidir 2.5 V VCCIO5 Leave unconnected RSVD K12 Bidir 2.5 V VCCIO5 Leave unconnected RSVD L13 Bidir 2.5 V VCCIO5 Leave unconnected RSVD L16 Bidir 2.5 V VCCIO5 Leave unconnected RSVD M6 Bidir 1.8 V VCCIO3 Leave unconnected RSVD N14 Bidir 2.5 V VCCIO5 Leave unconnected RSVD P15 Bidir 2.5 V VCCIO5 Leave unconnected RSVD_IN A8 Input 1.8 V VCCIO8 Tie to GND RSVD_IN A9 Input 1.8 V VCCIO7 Tie to GND RSVD_IN B8 Input 1.8 V VCCIO8 Tie to GND RSVD_IN B9 Input 1.8 V VCCIO7 Tie to GND RSVD_IN L14 Input Analog VCCIO5 Tie to 2.5 V RSVD_IN L15 Input Analog VCCIO5 Tie to 2.5 V RSVD_IN M2 Input 1.8 V VCCIO2 Tie to GND RSVD_IN R8 Input 1.8 V VCCIO3 Tie to GND RSVD_IN R9 Input 1.8 V VCCIO4 Tie to GND RSVD_IN T8 Input 1.8 V VCCIO3 Tie to GND RSVD_IN T9 Input 1.8 V VCCIO4 Tie to GND SENSOR_CLK B14 Output 1.8 V VCCIO7 Sensor main clock SENSOR_DEMOD_CL A14 Output 1.8 V VCCIO7 Demod clock for testK SENSOR_RSTZ D14 Output 1.8 V VCCIO7 Sensor reset SLEEP B1 Input 1.8 V VCCIO1 Puts the TFC in standby mode when enabled SYSCLK_IN E1 Input 1.8 V VCCIO1 Main system clock input TIC_C H3 Input 2.5 V – Reserved. Needs external pull-down resistor of 10 kΩ If high, TFC releases the control of configuration pins. InTIC_CEZ J3 Input 1.8 V VCCIO1 slave boot modes, tie to ground. TIC_CLK H1 Input 1.8 V VCCIO1 Configuration data clock TIC_CONFIGZ H5 Input 1.8 V VCCIO1 Used to start firmware load operation TIC_CONF_DONE H14 Output Open Drain VCCIO6 Used to indicate end of firmware load operation In master serial boot mode, Used by TFC to loadTIC_CSOZ D2 Output 1.8 V VCCIO1 firmware from EEPROM as chip select pin. TIC_DATA_0 H2 Input 1.8 V VCCIO1 Configuration data pin 0

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www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015 Pin Functions (continued) PIN I/OI/O I/O BANK DESCRIPTIONSTANDARDNAME NO. Used as output in master serial boot mode to TIC_DATA_1/ASDO C1 Bidir 1.8 V VCCIO1 communicate to firmware EEPROM as data-out pin. Input in passive parallel boot mode. Used only in Passive Parallel Boot mode. Tie to GNDTIC_DATA_2 E8 Input 1.8 V VCCIO8 otherwise. Used only in Passive Parallel Boot mode. Tie to GNDTIC_DATA_3 F8 Input 1.8 V VCCIO8 otherwise. Used only in Passive Parallel Boot mode. Tie to GNDTIC_DATA_4 B7 Input 1.8 V VCCIO8 otherwise. Used only in Passive Parallel Boot mode. Tie to GNDTIC_DATA_5 E7 Input 1.8 V VCCIO8 otherwise. Used only in Passive Parallel Boot mode. Tie to GNDTIC_DATA_6 E6 Input 1.8 V VCCIO8 otherwise. Used only in Passive Parallel Boot mode. Tie to GNDTIC_DATA_7 A5 Input 1.8 V VCCIO8 otherwise. Reserved. Needs external pull-up resistor of 10 kΩ to 2.5TIC_I H4 Input 2.5 V – V TIC_INIT_DONE G16 Output Open Drain VCCIO1 Used to indicate end of TFC initialization. TIC_O J4 Output 2.5 V – Reserved. Leave unconnected. Reserved. Needs external pull-up resistor of 10 kΩ to 2.5TIC_S J5 Input 2.5 V – V TIC_STATUSZ F4 Output Open Drain VCCIO1 Used to indicate status of firmware load operation VCCA1 L5 Power – – 2.5-V supply VCCA2 F12 Power – – 2.5-V supply VCCA3 F5 Power – – 2.5-V supply VCCA4 L12 Power – – 2.5-V supply VCCD_PLL1 N4 Power – – 1.2-V supply VCCD_PLL2 D13 Power – – 1.2-V supply VCCD_PLL3 D4 Power – – 1.2-V supply VCCD_PLL4 N13 Power – – 1.2-V supply VCCINT F7 Power – – 1.2-V supply VCCINT F11 Power – – 1.2-V supply VCCINT G6 Power – – 1.2-V supply VCCINT G7 Power – – 1.2-V supply VCCINT G8 Power – – 1.2-V supply VCCINT G9 Power – – 1.2-V supply VCCINT G10 Power – – 1.2-V supply VCCINT H6 Power – – 1.2-V supply VCCINT H11 Power – – 1.2-V supply VCCINT J6 Power – – 1.2-V supply VCCINT K7 Power – – 1.2-V supply VCCINT K11 Power – – 1.2-V supply VCCIO1 E3 Power – – 1.8-V supply VCCIO1 G3 Power – – 1.8-V supply VCCIO2 K3 Power – – 1.8-V supply VCCIO2 M3 Power – – 1.8-V supply VCCIO3 P4 Power – – 1.8-V supply VCCIO3 P7 Power – – 1.8-V supply VCCIO3 T1 Power – – 1.8-V supply Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: OPT9221

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN I/OI/O I/O BANK DESCRIPTIONSTANDARDNAME NO. VCCIO4 P10 Power – – 1.8-V supply VCCIO4 P13 Power – – 1.8-V supply VCCIO4 T16 Power – – 1.8-V supply VCCIO5 K14 Power – – 2.5-V supply VCCIO5 M14 Power – – 2.5-V supply VCCIO6 E14 Power – – 3.3-V supply VCCIO6 G14 Power – – 3.3-V supply VCCIO7 A16 Power – – 1.8-V supply VCCIO7 C10 Power – – 1.8-V supply VCCIO7 C13 Power – – 1.8-V supply VCCIO8 A1 Power – – 1.8-V supply VCCIO8 C4 Power – – 1.8-V supply VCCIO8 C7 Power – – 1.8-V supply VD K1 Output 1.8 V VCCIO2 Indicates the frame boundary VD_FR A13 Input 1.8 V VCCIO7 Sensor Frame VD VD_IN A7 Input 1.8 V VCCIO1 External Sync input VD_QD A10 Input 1.8 V VCCIO7 Sensor Quad VD VD_SF A12 Input 1.8 V VCCIO7 Sensor Sub-Frame VD VSYNC_OUT A15 Output 1.8 V VCCIO7 Sensor Sync input

6 Specifications

6.1 Absolute Maximum Ratings

at GND = 0 V and all voltages related to ground (unless otherwise noted)(1) (2) MIN MAX UNIT Core voltage VCCINT –0.5 1.8 V I/O voltage VCCIO –0.5 3.75 V PLL digital supply VCCD_PLL –0.5 4.5 V PLL Analog supply VCCA –0.5 3.75 V Input voltage at input pins, VI –0.5 4.2 V Output current from output pins, IOUT –25 40 mA Operating junction temperature, TJ –40 125 °C Storage temperature range, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the device ground.

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2000pins(1) V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification 500JESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

at GND = 0 V and all voltages related to ground (unless otherwise noted) MIN NOM MAX UNIT VCCINT Core voltage 1.15 1.2 1.25 V 1.8-V operation 1.71 1.8 1.89 V VCCIO I/O voltage 2.5-V operation 2.375 2.5 2.625 3.3-V operation 3.135 3.3 3.465 V VCCD_PLL PLL digital supply 1.16 1.2 1.24 V VCCA PLL Analog supply 2.375 2.5 2.625 V VCCIO(1) +VI Input voltage at input pins –0.3 V0.3 TJ Operating junction temperature 0 85 °C tRAMP Power-supply ramp time 50 3000 µs (1) VCCIO is the corresponding bank voltage

6.4 Thermal Information

THERMAL METRIC(1) ZVM (NFBGA) UNIT

256 BALLS

RθJA Junction-to-ambient thermal resistance 30.6 RθJC(top) Junction-to-case (top) thermal resistance 7.6 °C/W RθJB Junction-to-board thermal resistance 16.0 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: OPT9221

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com

6.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.8-V CMOS I/Os VIH High-level input threshold 0.65 × VCCIO(1) V VIL Low-level input threshold 0.35 × VCCIO V VOH High-level output voltage VCCIO – 0.45 V VOL Low-level output voltage 0.45 V Ilkg Input pin leakage current(2) –10 10 µA IOH High-level output current –2 mA IOL Low-level output current 2 mA 3.3-V LVCMOS I/Os VIH High-level input voltage 1.7 V VIL Low-level input voltage 0.8 V VOH High-level output voltage VCCIO – 0.2 V VOL Low-level output voltage 0.2 V Ilkg Input pin leakage current(2) –10 10 µA IOH High-level output current –2 mA IOL Low-level output current 2 mA (1) VCCIO is the corresponding bank voltage. (2) For, 0 < Input voltage < VCCIO.

6.6 Timing Requirements

PARAMETER MIN TYP MAX UNIT

6 MHz

12 MHz

System input clock frequency SYSCLK_IN 24 MHz

48 MHz

Duty cycle 40% 60% SYSCLK_FR Internal system clock frequency 48 MHzEQ VD_IN VD_IN pulse duration 40 ns RESET RESET pulse duration 40 ns Slave I2C interface clock frequency 400 KHz I2C clock Master I2C interface clock frequency 400 KHz Sensor I2C interface clock frequency 400 KHz PARALLEL CMOS MODE (Assuming default OP_CLK polarity) tsu Data setup time Data valid to zero crossing of CLKOUT 5 ns th Data hold time Zero crossing of CLKOUT to data 20 nsbecoming invalid

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Product Folder Links: OPT9221

Figure 1. Timing Diagram

I2C Master, Slave Controller Output Interface Module Data, Clock DVP, SSI VD_IN GPOs Slave I2C Flow Control Master I2C Configuration TIC_MS (4 Lines) OPT9221 Temperature Compensation SYSCLK_IN VD, CLK, Reset, I2C Control Temperature Compensation From Illumination To OPT8241 From OPT8241 To DDR To Optional EEPROM To Optional Temperature Sensor To Host IOVDD 1.8 V, 2.5 V, 3.3 V VCCINT 1.2 V VCCD_PLL 1.2 V VCCA 2.5 V OPT9221 SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com

7 Detailed Description

7.1 Overview

The TFC has the following blocks:

• Timing generator – Generates the sequencing signals for sensor, illumination and depth processor
• Input LVDS receiver and de-serializer
• Depth engine - Calculates phase and amplitude
• Output data interface module
• DDR2 memory controller for external DDR memory
• I2C slave - for configuration of TFC registers by the host processor
• I2C master – for temperature sensing
• I2C sensor interface – for controlling the OPT8241 sensor

7.2 Functional Block Diagram

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Product Folder Links: OPT9221

7.3 Feature Description

7.3.1 DDR2 Interface

recommended DDR part is Micron MT47H32M16NF-25E:H.

7.3.2 I2C Master Interface

status registers are listed in Table 1. Table 1. I2C Master Interface tillum_slv_addr I2C address of the temperature sensor next to the illumination driver. Status registers. Indicates the temperature readout from the temperature sensor next to thetillum illumination driver.

7.3.3 Timing Coordinator

• Frame rate control
• Sensor addressing
• Integration time control
• Modulation clock generation

7.3.3.1 Basic Frame Structure

Each frame is divided into sub-frames used for internal averaging. Each quad is further split into 4 stages.

Integration The pixel array and illumination are modulated by the TFC. The sensor captures the raw ToF signal. Readout The raw pixel data in the selected region of interest is readout from the sensor by the TFC. Dead The sensor is inactive. The TFC and the sensor enter a low power mode.

7.3.3.2 Frame Rate Control and Sub Frames

Table 2 control the master and slave behavior. Table 2. Master and Slave Parameters Start the timing generator and hence the full chipset operation. tg_dis 1 '0' : Enable the timing generator. external input through VD_IN pin for the start of frames, but does not depend on it.sync_mode 0 If both slave_mode and sync_mode are enabled, sync_mode takes higher priority. By default, this mode is disabled. The programmable delay between external VD_IN pulse and internal start offrame_sync_delay 1 frame. The delay has to be at the least 1 cycle.. and therefore there is a possibility disruption of output data and hence loss of information. Figure 2. Timing Diagram

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Table 3. Frame-Rate Parameters The number of quads in each sub-frame. Number of quads can be currentlyquad_cnt_max 4 programmed to 4 and 6 only. Behavior is not determined for other values. The number of system clock cycles in one frame divided by the product ofpix_cnt_max 100000 quad_cnt_max and sub_frame_cnt _max. and readout time, pix_cnt_max_set_failed is set. artefacts and power consumption. By default, distributed dead time is used.

7.3.3.3 Input Clock Generation

related parameter is shown in Table 4. Table 4. Input Clock Generation

7.3.3.4 Sensor Addressing Engine

sequence can be configured to allow custom sensor readouts as per the requirements of the system.

7.3.3.4.1 Region of Interest (ROI)

ToF system. An ROI comprises of a set of row and column limits. The row and column counts start from zero. multiple of 16 and column end is one less than a multiple of 16. The relevant parameters are listed in Table 5. Table 5. ROI Parameters

• Preparation time = 401 + total number of columns (Measured in system clock cycles) (5)

7.3.3.4.2 Readout Sequence

Table 6. Readout Sequence Parameters

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7.3.3.5 Integration Time

configurable parameters are listed in Table 7. Table 7. Integration Time Parameters intg_duty_cycle 6 This parameter controls the ratio of integration time to total frame time. checked again. This process has to be repeated till the flag clears. normal_frm_intg_scale 0 Scaling of integration time.

• quad_cnt_max
• sub_frame_cnt_max
• pix_cnt_max
• lumped_dead_time
• row_start
• col_start
• row_end
• col_end When OPT9221 is in slave mode, the duty cycle will still correspond to the frame length calculated as per the internal registers and not as per the period of the external sync signal. The sync signal period should be large enough to make sure that the frame data is streamed successfully. When the sync signal period is larger than the internal frame period, actual integration duty cycle will be lesser than the programmed value.

7.3.3.5.1 High Dynamic Range Functionality

Table 8. High Dynamic Range Functionality Parameter

7.3.3.6 Modulation Clock Generator

the illumination module from quad to quad.

7.3.3.6.1 Sensor Output Signals

Table 9. Sensor Output signals High frequency input to the illumination driver – Non-inverting. Modulates during integration time. Low by default duringILLUM_P rest of the time. High frequency input to the illumination driver – Inverting. Modulates during integration time. High by default during restILLUM_N of the time. integration time. The polarities and the position of the pulse are programmable. Figure 3. Timing Diagram

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8 Data lanes

Table 10. Pin Programmability modulation_hold 0 Disable modulation during integration period. Set to ‘0’for normal operation. demod_static_pol 0 DC state of illumination pins during integration period if mod_static=’1’. value of this register is 11 which results into a total correction of about +/-5 ns. Table 11. Phase Sequence Programmability quad_hop_en 0 Enables a different sequence of quads for odd and even frames. quad_hop_offset_f1 0 The offset of the quad sequence for alternate frames for base frequency. Note that the quad number is offset by the flicker cancel offset for that sub-frame.

7.3.4 Output Interface

to wide variety of host processors. Figure 4. Output Interface Module

Table 12. Output Interface Pins edge of this clock. By default, the output signals transition on the negative edge of this clock. Output CMOS data pins. By default, all the pins are used for transfer of data. In the 4-lane mode, only Data[3:0] areOP_DATA [7:0] used. In the 1-lane mode, only Data[0] is used. This signal is used as horizontal sync in the DVP mode to indicate row data transfer. In 8-lane generic CMOS mode, itHD/BD is used to indicate the validity of the data available on output bus. VD Frame sync. It used to indicate the beginning of a new frame. Chip select. This signal is used to indicate the validity of the data on the data bus. It can be used in the TI SSI mode asOP_CS SSIFss. FE Frame-end. This signal pulses for a single clock cycle to indicate frame end. Ready This signal is used for flow control when enabled. Output data is buffered when the ready signal is not active. Overflow This signal is used by host processor to indicate buffer overflow. This is used for debug only.

7.3.4.1 Output Data Format

• 12 bits amplitude (C)
• 4 bits ambient (A)
• 12 bits phase (P)
• 4 bits flags (F) Byte 3 Byte 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Flags[3:0] Phase[11:0] Byte 1 Byte 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ambient[3:0] Amplitude[11:0] Ambient and amplitude information together form a 16-bit word with ambient in the MSBs. Flags and phase information together form a 16-bit word with flags in the MSBs. There are two modes of arrangement possible : Contiguous Pixel0 Pixel1 Pixel3 … … …

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• 4 bits amplitude (C)
• 12 bits phase (P ) Byte 1 Byte 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Amplitude [3:0] Phase[11:0] Amplitude and phase information together form a 16-bit word with confidence in the MSBs

7.3.4.1.3 Register Controls

Table 13. Register Controls

7.3.4.2 Frame Fragmentation

can be employed to achieve UVC streaming on to a USB host.

7.3.4.3 Data Output Waveforms

and row boundaries respectively. Output data order is least significant byte first.

Table 14. Timing Notations Table 15. Parameters 1: Activate frame end signal one output clock cycle after the last byte of data. by row. Output data order is least significant byte first.

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OP_Data<0> CS tBA=(Blocksize*8) tBB OPT9221 SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com Table 18. TIMING NOTATION DESCRIPTION (Number of OP_CLK cycles) PROGRAMMABLE OR CALCULATED Block active time Programmable using the blk_size parameter.tBA tBA= blk_size × 2 tBB Block blanking time Programmable using blk_blank_size parameter Chip-select (OP_CS) signal indicates the validity of the data presented on Data[3:0]. For example, if a block- blanking period of 2 clocks and a block-size of 4 bytes are programmed, OP_CS remains inactive of 2 clocks and become active for 8 clock cycles. Chip-select polarity is programmable using the op_cs_pol parameter. A 4-byte header containing a unique sequence – 0xFF, 0xFF, 0xFF, 0xFF is inserted in the beginning of each frame to indicate the start of frame in this mode. Serialization Logic in 4-Lane Mode Figure 11. Each chunk of 4-byte data is serialized and sent out on Data[3:0]. While the 1st byte is being sent out on Data[0], the successive bytes are sent on the other data lanes simultaneously. Within each byte, the LSB is sent out first. 7.3.4.3.4 1-Lane Mode – SSI Figure 12. Table 19. TIMING NOTATION DESCRIPTION (Number of OP_CLK cycles) PROGRAMMABLE OR CALCULATED Block active time Programmable using the blk_size parameter.tBA tBA= blk_size × 8 tBB Block blanking time Programmable using blk_blank_size parameter

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Product Folder Links: OPT9221

www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015 Chip-select (OP_CS) indicates the validity of the data presented on Data[0]. For example, if a block-blanking period of 2 clocks and a block size of 4 bytes are programmed, OP_CS remains inactive of 2 clocks and remain active for 32 clock cycles. Chip-select polarity is programmable using the op_cs_pol parameter. A 4-byte header containing a unique sequence – 0xFF, 0xFF, 0xFF, 0xFF is inserted in the beginning of each frame to indicate the start of frame in this mode . Serialization Logic in 1-Lane Mode Figure 13. Each byte of data is serialized and sent out on Data[0]. Within each byte, the LSB is sent out first. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: OPT9221

7.3.4.3.5 Register Controls

Table 20. Register Control Parameters this parameter has no effect. blk_header_en When enabled, a 12 byte UVC header for every packet is inserted. Data transitions on the configured edge of the output clock.

• Where, pixel data size is set by the pixel_data_size register. (10)

7.3.5 Modulation Frequency

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Figure 14. Modulation PLL Block Diagram To enable accurate setting of desired modulation frequency, Mod_m is split into an integer and a fractional part. The programmable parameters are listed in Table 21. The default modulation frequency on start-up is 48 MHz. Table 21. Programmable Parameters update starts on the positive edge.

7.3.6 LVDS Receiver and Deserializer

with the TI ToF integrated ADC+TG+sensor - OPT8241.

7.3.7 Depth Engine

• Phase/amplitude calculation
• Temperature calibration
• Binning
• De-aliasing
• Histogram

7.3.7.1 Phase Data

phase varying from 0 to 2π, the distance varies from 0 to R where R is the unambiguous range.

/ca7 /cb7 /ca8 /cb8 /ca9 /cb9 /ca6 n=N n n=0 2/c8c/c51I = Q Cos N /ca7 /cb7 /ca8 /cb8 /ca9 /cb9 /ca6 n=N n n=0 2/c8c/c51Q = Q Sin N -1 QPhase = tan I OPT9221 SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com (14) where

• C is speed of light
• F is the modulation frequency (15) At the output of the depth processor block, phase of 2π is typically represented by a full 12-bit code. That is, 212. If the application requires knowledge of the distance (in meters) of the points in the scene, it must be calculated from the TFC output using the following formula: (16) The above formula assumes that the phase has no offset. If offset correction is not done within the TFC, the formula is: (17) The sensor data collected in the quads is used to compute the phase information. The quad information is then used to compute in-phase and quadrature components as shown in Equation 18: where
• ‘N’is the number of quads in each sub-frame and ‘n’is the quad index. The Cos and Sin coefficients need to be programmed into the TFC as per the number of quads. The default coefficients are programmed for 4 quads. (18)

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/ca7 /cb7 /c75/ca8 /cb8 /ca9 /cb9 2/c8c/c51cos_fx_qn_coeff = 32767 CosN /ca7 /cb7 /c75/ca8 /cb8 /ca9 /cb9 2/c8c/c51sin_fx_qn_coeff = 32767 SinN OPT9221 www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015 Each parameter in the register set is a coefficient represented in 16-bits signed representation. The formula for calculating the parameter is shown in Equation 19: where

• n is the index of the coefficient, ‘x’represents the frequency (base or de-aliasing frequency). N is the number of quads (same as quad_cnt_max). (19) When de-aliasing is not enabled, the default number of quads is 4. To use 6 quads without de-aliasing, the following configuration has to be programmed.
• Reduce the number of sub-frames (sub_frame_cnt_max) to 2 or reduce the output clock to 12 MHz (op_clk_freq).
• Program base frequency (f1) to desired value.
• Set the number of quads (quad_cnt_max) to 6.
• Set ind_freq_data_sel to ‘1’to use the alternate set of coefficients to process the obtained data.
• Set cos_f2_qn_coeff and sin_f2_qn_coeff registers to the appropriate values.

7.3.7.2 De-Aliasing

Unambiguous range of a ToF system is defined by the modulation frequency (F). It is given by the equation Equation 20: where

• C is the speed of light in the medium. (20) For example, for a modulation frequency of 50 MHz, R = 3m in open air. If the total range of the application is beyond the unambiguous range for a given modulation frequency, de-aliasing can be enabled to extend the unambiguous range. This technique employs two modulation frequencies. The unambiguous range is given by Equation 21: (21) The de-aliasing filter implemented in the depth processor computes the unambiguous phase automatically when de-aliasing is enabled.

7.3.7.2.1 Procedure for Enabling the De-Aliasing Mode

1. Disable the timing generator using the tg_dis parameter. 2. set quad_cnt_max parameter to 6. 3. Set the base frequency and de-aliasing modulation frequency as described in Modulation Clock Generator section. Always ensure that base frequency is lower than the de-aliasing frequency. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: OPT9221

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com 4. Set the de-aliasing coefficients as shown in Setting the De-Aliasing Coefficients. 5. Set the phase calibration parameters for each frequency as described in Phase Offset Correction section. 6. Set sub_frame_cnt_max count to meet the relation (refer Equation 10) between sub_frame_cnt_max and quad_cnt_max. 7. Set pix_cnt_max to meet frame rate requirements. 8. Set dealias_en parameter to 1. 9. Enable the timing generator using the tg_enable parameter. When de-aliasing is enabled, for the purpose of calibration, streaming of individual frequency data can be enabled in place of de-aliased data using the parameters in Table 22. Table 22. PARAMETER DEFAULT DESCRIPTION Enables streaming of output data corresponding to individual frequencies. ind_freq_data_en 0 0: disabled 1: enabled 0: Stream output data corresponding to base frequencyind_freq_data_sel 0 1: Stream output data corresponding to de-aliasing frequency

7.3.7.2.2 Procedure for Disabling the De-Aliasing Mode

1. Disable the timing generator using the tg_dis parameter. 2. Set the pix_cnt_max, sub_frame_cnt_max and quad_cnt_max parameters to meet the frame rate requirements and satisfy Equation 10. 3. Set the base frequency as described in Modulation Clock Generator section. 4. Set the phase calibration parameter for base frequency as described in Phase Offset Correction section. 5. Set dealias_en parameter to 0. 6. Enable the timing generator using the tg_dis parameter.

7.3.7.2.3 Setting the De-Aliasing Coefficients

The parameters ma and mb have to be chosen such that the following conditions are met: (22) And the parameter freq_ratio has to be programmed to match the ratio between the two frequencies as shown in Equation 23: (23) Where, f1 is the base frequency and f2 is the de-aliasing frequency. The coefficients ka and kb have to be chosen such that (ka × ma) - (kb × mb) = 1

7.3.7.2.4 Scaling of Phase

The de-aliased phase is internally masked. The mask is programmable using a register configuration as shown by Equation 24: (24) Where,

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www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015 (25) Where, R is the total unambiguous range. The internal de-aliased phase is 16-bit wide. But the final phase output is only 12 bit. The application of the mask leads to a scaling in the output. Therefore, to correctly calculate the distance, Equation 26 should be used in the external host. (26) Programmable parameters are listed in Table 23. Table 23. PARAMETER DEFAULT DESCRIPTION The mask for the getting the output phase from the calculated de-aliased phase. The mask is dealiased_ph_mask 0 16bits wide. The least significant bit of the mask is given by the following relation. LSB=5- dealiased_ph_mask. Example: Table 24. F1 = 18 MHz F2 = 24 MHz ma = 3 mb = 4 Unambiguous range = 8.33 m Unambiguous range= 6.25 m Therefore, the total unambiguous range with de-aliasing is given by Equation 27: (27) For a value of 20m, the value of de-aliased phase is given by Equation 28: (28) If the default value of dealised_ph_mask is used, the phase output for 20m will be given by Equation 29: (29) At the host, the original distance value can be calculated as shown by Equation 30: (30) Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: OPT9221

7.3.7.2.5 LSBs in the De-Aliased Phase

phase output, the following parameter can bet set as shown in Table 25. when using 16-bit de-aliased phase output.

7.3.7.3 Binning

rows/columns can be binned. The programmable parameters are listed in Table 26. Table 26. Binning Parameters bin_row_count 240 Number of rows after binning. rows_to_merge=7, bin_row_count = floor(total no of rows / 7) = floor(240/7) = 34.

7.3.7.4 Spatial Filter

by I + jQ. The spatial filter coefficients are arranged as shown in Table 27. The relevant parameters are listed in Table 28. filt_scale Filters are scaled down by 2(2 + filt_scale).

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7.3.7.5 Auxiliary Depth Data

amplitude is higher and hence the phase SNR is higher. The value of amplitude output is given by Equation 31. pixels divided by the nearest power of two which is greater than the number of pixels binned together. values decrease with increase in voltage. Therefore, near zero values indicate pixel saturation. purpose of basic filtering. The related parameters are listed in Table 29. Table 29. Auxiliary Depth Data Parameters amplitude_threshold If the amplitude of the pixel is lower than this number, the pixel phase data is set to0 FFFh. amplitude_post_scale Left shifts the computed amplitude by the configured value. If the amplitude of any pixel0 exceeds the full scale value, the amplitude is clipped to FFFh. saturation_threshold Saturation flag is set if the ambient value of the pixel is lesser than or equal to this value.0 Also, pixel phase data is set to 000h. Flags[3:0] indicate important pixel data reliability parameters. The flags are described in Table 30. Table 30. Pixel Data

7.3.8 Calibration

7.3.8.1 Phase Offset Correction

phase_corr parameter to the computed phase. The programmable parameters are listed in Table 31. Table 31. Phase Offset Correction Parameters

Table 31. Phase Offset Correction Parameters (continued) disable_offset_corr Disables phase offset correction in the TFC. Phase offset correction is enabled by default. Due to temperature variations, system delays in the illumination and sensor modulation path can vary differently. measuring the illumination driver temperature. The programmable parameters are listed in Table 32. Table 32. Temperature Coefficient Parameters tillum_calib Illumination driver temperature when phase_corr was measured. tsensor_calib Sensor temperature when phase_corr was measured. coeff_illum Phase vs temperature coefficients for illumination driver for the base frequency. coeff_sensor Phase vs temperature coefficients for sensor for the base frequency. Where, calibration scale is 1 when calib_prec = 0 and 16 when calib_prec = 1 .

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IO_MOD_REF External Feedback Circuit ILLUM_MOD_FB ILLUM_P COMP_MOD_REF COMP_MOD_FB Illumination source OPT9221 www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015

7.3.8.2 Illumination Path Delay Correction Using Feedback

The illumination modulation path delay can be compensated to reduce the absolute and temperature dependent phase offsets. The illumination modulation path delay is measured using feedback from the sensor and the illumination modulation. The appropriate feedback has to be implemented in the system. A typical block diagram of such a feedback system is shown in Figure 15. Figure 15. The delay compensation circuit measures the delay from ILLUM_P to COMP_MOD_FB during the integration time and measures the delay of the external feedback circuit from COMP_MOD_REF to COMP_MOD_FB during sensor readout. For measuring the delay, an internal uncorrelated clock (with a frequency between 10 MHz to 50 MHz) is used to sample the feedback waveforms. The difference between the two delays measured is used as a phase offset that is used to correct the obtained phase. Functional requirements of the feedback circuit:

• ILLUM_P output from OPT8241 should be connected to ILLUM_MOD_REF input pin of OPT9221
• The output of a feedback ckt that converts illumination current waveform to a square wave must be connected to COMP_MOD_FB pin.
• The same feedback ckt or a replica with similar delays must be driven by COMP_MOD_REF and the output must be fed back to COMP_MOD_FB pin
• The feedback circuit must have a minimum frequency of operation of 48 MHz or the operating modulation frequency (whichever is higher) The relevant parameters for configuring the delay correction block are listed in Table 34. Table 34. PARAMETER DESCRIPTION Enabled phase correction using illumination path delay feedback and set the direction ofdelay_fb_corr_mode correction. Enable using the duty cycle of the obtained feedback signal for calculating the phasedelay_fb_dc_corr_mode compensation and set the direction of correction. comp_mod_ref_inv Enable inversion of feedback signal in the signal chain before evaluating the delay. Enable inversion of the signal at ILLUM_FB pin in the signal chain before evaluating theIllum_fb_inv delay. fb_error_cnt_threshold Number of errors that can be tolerated in sampling the pulses per 4096 samples. comp_fb_error_cnt Number of pulses not sampled correctly on the COMP_FB pin. illum_fb_error_cnt Number of pulses not sampled correctly on the ILLUM_FB pin. delay_fb_coeff Ratio of modulation frequency to 24MHz. Refer to Equation 34 The delay coefficients have to be calculated as per the below equations . When de-aliasing is not enabled: (34) Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Links: OPT9221

7.3.8.3 Phase Non-Linearity Correction

table is used for converting the obtained phase to linearized phase. The relevant registers are listed in Table 35. phase_lin_corr_period The period after which the non-linearity function repeats. lookup table is repeated for rest of the angles.

7.4 Device Functional Modes

7.4.1 Standby and Low-Power Modes

achieved using register settings. The parameters that control the low power operation are listed inTable 36. Table 36. Parameter Description Selects the active polarity of standby pin. For example, when set to ‘1’the chipset enters low-power mode whenstandby_pin_pol standby pin is pulled high. Active only when standby_pin_en is set.

7.5 Programming

7.5.1 Boot Sequence

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Figure 16. Boot Sequence Timing Diagram Table 37. Boot Sequence Timing Parameters(1) tCONF Configuration time. Depends on the mode of configuration and the - -clock rates. (1) Configuration time (tCONF ) depends on the mode of the configuration.

7.5.1.1 Configuration

After the POR is complete, one of the configuration methods is chosen as per the state of the BOOT[2:0] pins. The recommended modes are listed in Table 38. Table 38. Recommended Boot Modes

011 Master serial configuration Firmware is loaded from an external EEPROM

000 Slave serial configuration External host loads the firmware using single data pin

111 Slave parallel configuration External host loads the firmware using 8 data pins. After the configuration is complete and the TFC is ready for operation the TFC pulls the INT_OUT pin low.

7.5.1.1.1 Master Serial Configuration

firmware has to be programmed in the least significant bit first order into the EEPROM for proper functionality. The recommended EEPROM is W25Q04DWSSIG.

Figure 17. Recommended Connections

7.5.1.1.2 Slave Serial Configuration (SS mode)

Figure 18. Connection Diagram

7.5.1.1.3 Slave Parallel Configuration (SP mode)

data lanes instead of a single lane in the SS mode.

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7.5.1.1.4 Slave Parallel and Serial Timing

Figure 20. Slave Parallel and Serial Timing Diagram Table 39. Slave Parallel and Serial Timing Characteristics configuration data from the host on every falling edge of the clock.

after the configuration is complete. Hold the TIC_CONFIG pin high after the configuration.

7.5.2 Slave I2C Interface

without taking into account the state of the TFC. appropriate register settings in I2C control register is necessary. The individual registers are 24 bit length in this device. However, the register read/write is in chunks of eight bits. an acknowledgment in the case of write. The following figures explain the I2C format. Figure 21. I2C Write Example Table 40. I2C Register Write Table 41. I2C Register Read Table 42. I2C Register Write (Continuous mode) Table 43. I2C Register Read (Continuous mode)

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7.6 Register Maps

7.6.1 Serial Interface Register Map

Table 44. DE Register Map

Table 44. DE Register Map (continued)

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7.6.2 Register Descriptions

7.6.2.1 Register 0h (offset = 0h) [reset = 0h]

Figure 22. Register 0h Table 45. Register 00 Field Descriptions

7.6.2.2 Register 1h (offset = 1h) [reset = 1XXh]

Figure 23. Register 1h Table 46. Register 01 Field Descriptions

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7.6.2.3 Register 2h (offset = 2h) [reset = 100C81h]

Figure 24. Register 2h Table 47. Register 02 Field Descriptions Enables de-aliasing whenBit D23 DEALIAS_EN R/W 0h set to '1'.

7.6.2.4 Register 3h (offset = 3h) [reset = 100000h]

Figure 25. Register 3h

0 DEALIASED_PH_MASK 0 0 0

Table 48. Register 03 Field Descriptions representation.Bits[14:11] DEALIASED_PH_MASK R/W 0h The mask is 16bits wide.

7.6.2.5 Register 4h (offset = 4h) [reset = 0h]

Figure 26. Register 4h Table 49. Register 04 Field Descriptions

48 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.6 Register 5h (offset = 5h) [reset = 7FFFh]

Figure 27. Register 5h Table 50. Register 05 Field Descriptions

7.6.2.7 Register 6h (offset = 6h) [reset = 0h]

Figure 28. Register 6h Table 51. Register 06 Field Descriptions

7.6.2.8 Register 7h (offset = 7h) [reset = 8001h]

Figure 29. Register 7h Table 52. Register 07 Field Descriptions

7.6.2.9 Register 8h (offset = 8h) [reset = 0h]

Figure 30. Register 8h Table 53. Register 08 Field Descriptions

7.6.2.10 Register 9h (offset = 9h) [reset = 0h]

Figure 31. Register 9h Table 54. Register 09 Field Descriptions

7.6.2.11 Register Ah (offset = Ah) [reset = 7FFFh]

Figure 32. Register Ah Table 55. Register 0A Field Descriptions

50 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.12 Register Bh (offset = Bh) [reset = 0h]

Figure 33. Register Bh Table 56. Register 0B Field Descriptions

7.6.2.13 Register Ch (offset = Ch) [reset = 8001h]

Figure 34. Register Ch Table 57. Register 0C Field Descriptions

7.6.2.14 Register Dh (offset = Dh) [reset = 0h]

Figure 35. Register Dh Table 58. Register 0D Field Descriptions

7.6.2.15 Register Eh (offset = Eh) [reset = 0h]

Figure 36. Register Eh Table 59. Register 0E Field Descriptions

7.6.2.16 Register Fh (offset = Fh) [reset = 0h]

Figure 37. Register Fh Table 60. Register 0F Field Descriptions

7.6.2.17 Register 10h (offset = 10h) [reset = 0h]

Figure 38. Register 10h Table 61. Register 10 Field Descriptions

52 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.18 Register 11h (offset = 11h) [reset = 6ED9h]

Figure 39. Register 11h Table 62. Register 11 Field Descriptions

7.6.2.19 Register 12h (offset = 12h) [reset = 9127h]

Figure 40. Register 12h Table 63. Register 12 Field Descriptions

7.6.2.20 Register 13h (offset = 13h) [reset = 0h]

Figure 41. Register 13h Table 64. Register 13 Field Descriptions

7.6.2.21 Register 14h (offset = 14h) [reset = 6ED9h]

Figure 42. Register 14h Table 65. Register 14 Field Descriptions

7.6.2.22 Register 15h (offset = 15h) [reset = 9127h]

Figure 43. Register 15h Table 66. Register 15 Field Descriptions

7.6.2.23 Register 16h (offset = 16h) [reset = 7FFFh]

Figure 44. Register 16h Table 67. Register 16 Field Descriptions

54 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.24 Register 17h (offset = 17h) [reset = C000h]

Figure 45. Register 17h Table 68. Register 17 Field Descriptions

7.6.2.25 Register 18h (offset = 18h) [reset = C000h]

Figure 46. Register 18h Table 69. Register 18 Field Descriptions

7.6.2.26 Register 19h (offset = 19h) [reset = 7FFFh]

Figure 47. Register 19h Table 70. Register 19 Field Descriptions

7.6.2.27 Register 1Ah (offset = 1Ah) [reset = C000h]

Figure 48. Register 1Ah Table 71. Register 1A Field Descriptions

7.6.2.28 Register 1Bh (offset = 1Bh) [reset = C000h]

Figure 49. Register 1Bh Table 72. Register 1B Field Descriptions

7.6.2.29 Register 1Fh (offset = 1Fh) [reset = 54321h]

Figure 50. Register 1Fh

0 IQ_SCALE 0 1 0 1

Table 73. Register 1F Field Descriptions

56 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.30 Register 25h (offset = 25h) [reset = 80001h]

Figure 51. Register 25h Table 74. Register 25 Field Descriptions

7.6.2.31 Register 27h (offset = 27h) [reset = 2000h]

Figure 52. Register 27h

0 PIXEL_DATA_SIZE 0 0 0

Table 75. Register 27 Field Descriptions

7.6.2.32 Register 28h (offset = 28h) [reset = 0h]

Figure 53. Register 28h Table 76. Register 28 Field Descriptions

7.6.2.33 Register 29h (offset = 29h) [reset = 304000h]

Figure 54. Register 29h Table 77. Register 29 Field Descriptions Bit D1 PHY_TEST_ENABLE R/W 0h Outputs an 8-bit ramp.

58 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.34 Register 2Eh (offset = 2Eh) [reset = 871h]

Figure 55. Register 2Eh

0 TILLUM_SLV_ADDR

Table 78. Register 2E Field Descriptions

7.6.2.35 Register 2Fh (offset = 2Fh) [reset = 3C0001h]

Figure 56. Register 2Fh Table 79. Register 2F Field Descriptions

7.6.2.36 Register 30h (offset = 30h) [reset = 500001h]

Figure 57. Register 30h Table 80. Register 30 Field Descriptions

60 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.37 Register 31h (offset = 31h) [reset = 1802h]

Figure 58. Register 31h Table 81. Register 31 Field Descriptions

7.6.2.38 Register 33h (offset = 33h) [reset = 30h]

Figure 59. Register 33h Table 82. Register 33 Field Descriptions Bits[23:16] SYSCLK_IN_FREQ R/W 0h 48MHz system clock.

7.6.2.39 Register 35h (offset = 35h) [reset = 800000h]

Figure 60. Register 35h

1 ILLUM_MOD_E ILLUM_EN_EA 0 0 0 0 0

Table 83. Register 35 Field Descriptions integration starts by 15usBit D22 ILLUM_MOD_EARLY R/W 0h when set to '1'.

62 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.40 Register 36h (offset = 36h) [reset = 0h]

Figure 61. Register 36h Table 84. Register 36 Field Descriptions

7.6.2.41 Register 37h (offset = 37h) [reset = 0h]

Figure 62. Register 37h Table 85. Register 37 Field Descriptions

7.6.2.42 Register 38h (offset = 38h) [reset = 0h]

Figure 63. Register 38h Table 86. Register 38 Field Descriptions

7.6.2.43 Register 39h (offset = 39h) [reset = 0h]

Figure 64. Register 39h Table 87. Register 39 Field Descriptions

64 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.44 Register 3Ah (offset = 3Ah) [reset = 0h]

Figure 65. Register 3Ah Table 88. Register 3A Field Descriptions Bits[15:4] HDR_PHASE_CORR_1 R/W 0h the base frequency data.

7.6.2.45 Register 3Bh (offset = 3Bh) [reset = 0h]

Figure 66. Register 3Bh Table 89. Register 3B Field Descriptions

7.6.2.46 Register 3Ch (offset = 3Ch) [reset = 4000h]

Figure 67. Register 3Ch Table 90. Register 3C Field Descriptions terms of the number ofBits[23:4] BLK_SIZE R/W 400h output clock cycles.

66 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.47 Register 3Dh (offset = 3Dh) [reset = 0h]

Figure 68. Register 3Dh Table 91. Register 3D Field Descriptions

7.6.2.48 Register 3Eh (offset = 3Eh) [reset = 80h]

Figure 69. Register 3Eh Table 92. Register 3E Field Descriptions

7.6.2.49 Register 3Fh (offset = 3Fh) [reset = Bh]

Figure 70. Register 3Fh Table 93. Register 3F Field Descriptions

68 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.50 Register 40h (offset = 40h) [reset = 50455h]

Figure 71. Register 40h

0 OP_CS_POL 0 0 0 PHASE_AUX_ 0 PHASE_AUX_

0 VD_POL 0 1 0 HD_POL 0 1

Table 94. Register 40 Field Descriptions Bit D10 PHASE_AUX_POL R/W 1h active. Bit D2 HD_POL R/W 1h active.

7.6.2.51 Register 47h (offset = 47h) [reset = 0h]

Figure 72. Register 47h Table 95. Register 47 Field Descriptions

7.6.2.52 Register 48h (offset = 48h) [reset = 0h]

Figure 73. Register 48h Table 96. Register 48 Field Descriptions

70 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.53 Register 4Ch (offset = 4Ch) [reset = 800006h]

Figure 74. Register 4Ch Table 97. Register 4C Field Descriptions Active only whenBit D20 STANDBY_PIN_POL R/W 0h standby_pin_en is set.

7.6.2.54 Register 4Dh (offset = 4Dh) [reset = 0h]

Figure 75. Register 4Dh Table 98. Register 4D Field Descriptions

72 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.55 Register 51h (offset = 51h) [reset = 140000h]

Figure 76. Register 51h Table 99. Register 51 Field Descriptions Bit D20 CALIB_PREC R/W 1h down by calib_prec. Disables phase calibrationBit D16 DISABLE_OFFSET_CORR R/W 0h completely when set to '1'.

7.6.2.56 Register 52h (offset = 52h) [reset = 0h]

Figure 77. Register 52h Table 100. Register 52 Field Descriptions Scales the amplitude values.

7.6.2.57 Register 61h (offset = 61h) [reset = 0h]

Figure 78. Register 61h Table 101. Register 61 Field Descriptions

7.6.2.58 Register 62h (offset = 62h) [reset = 0h]

Figure 79. Register 62h Table 102. Register 62 Field Descriptions address =Bits[7:0] TILLUM R 0h TILLUM_SLV_ADDR.

74 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.59 Register 63h (offset = 63h) [reset = 0h]

Figure 80. Register 63h Table 103. Register 63 Field Descriptions indicates the pix_cnt_maxBit D22 PIX_CNT_MAX_SET_FAILED R 0h setting is too low.

7.6.2.60 Register 65h (offset = 65h) [reset = 0h]

Figure 81. Register 65h Table 104. Register 65 Field Descriptions

7.6.2.61 Register 66h (offset = 66h) [reset = 0h]

Figure 82. Register 66h Table 105. Register 66 Field Descriptions

7.6.2.62 Register 80h (offset = 80h) [reset = 0h]

Figure 83. Register 80h Table 106. Register 80 Field Descriptions

76 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.63 Register 81h (offset = 81h) [reset = 0h]

Figure 84. Register 81h Table 107. Register 81 Field Descriptions

7.6.2.64 Register 82h (offset = 82h) [reset = 0h]

Figure 85. Register 82h Table 108. Register 82 Field Descriptions

7.6.2.65 Register 83h (offset = 83h) [reset = 0h]

Figure 86. Register 83h Table 109. Register 83 Field Descriptions

7.6.2.66 Register 84h (offset = 84h) [reset = 0h]

Figure 87. Register 84h Table 110. Register 84 Field Descriptions

7.6.2.67 Register 85h (offset = 85h) [reset = 0h]

Figure 88. Register 85h Table 111. Register 85 Field Descriptions

7.6.2.68 Register 86h (offset = 86h) [reset = 0h]

Figure 89. Register 86h Table 112. Register 86 Field Descriptions

78 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.69 Register 87h (offset = 87h) [reset = 0h]

Figure 90. Register 87h Table 113. Register 87 Field Descriptions

7.6.2.70 Register 88h (offset = 88h) [reset = 0h]

Figure 91. Register 88h Table 114. Register 88 Field Descriptions

7.6.2.71 Register 91h (offset = 91h) [reset = 0h]

Figure 92. Register 91h Table 115. Register 91 Field Descriptions

7.6.2.72 Register 92h (offset = 92h) [reset = 0h]

Figure 93. Register 92h Table 116. Register 92 Field Descriptions

7.6.2.73 Register 93h (offset = 93h) [reset = 0h]

Figure 94. Register 93h Table 117. Register 93 Field Descriptions

7.6.2.74 Register 94h (offset = 94h) [reset = 0h]

Figure 95. Register 94h Table 118. Register 94 Field Descriptions

80 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.75 Register 95h (offset = 95h) [reset = 0h]

Figure 96. Register 95h Table 119. Register 95 Field Descriptions

7.6.2.76 Register 96h (offset = 96h) [reset = 0h]

Figure 97. Register 96h Table 120. Register 96 Field Descriptions

7.6.2.77 Register 97h (offset = 97h) [reset = 0h]

Figure 98. Register 97h Table 121. Register 97 Field Descriptions

7.6.2.78 Register 98h (offset = 98h) [reset = 0h]

Figure 99. Register 98h Table 122. Register 98 Field Descriptions

7.6.2.79 Register ABh (offset = ABh) [reset = 0h]

Figure 100. Register ABh Table 123. Register AB Field Descriptions Used if filt_en is set to '1'. Location : Above or belowBits[23:16] FILT_COEF_Y_IM_F2 R/W 0h the center pixel. Used if filt_en is set to '1'. Location : Above or belowBits[15:8] FILT_COEF_Y_RE_F2 R/W 0h the center pixel.

82 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.80 Register ACh (offset = ACh) [reset = 0h]

Figure 101. Register ACh Table 124. Register AC Field Descriptions Used if filt_en is set to '1'. Location : Left or Right ofBits[23:16] FILT_COEF_X_RE_F2 R/W 0h the center pixel. Used if filt_en is set to '1'. Location : Left or Right ofBits[15:8] FILT_COEF_X_IM_F2 R/W 0h the center pixel.

7.6.2.81 Register ADh (offset = ADh) [reset = 0h]

Figure 102. Register ADh Table 125. Register AD Field Descriptions Used if filt_en is set to '1'. Location : Above or belowBits[23:16] FILT_COEF_Y_IM_F1 R/W 0h the center pixel. Used if filt_en is set to '1'. Location : Above or belowBits[15:8] FILT_COEF_Y_RE_F1 R/W 0h the center pixel.

7.6.2.82 Register AEh (offset = AEh) [reset = 0h]

Figure 103. Register AEh Table 126. Register AE Field Descriptions Used if filt_en is set to '1'. Location : Left or Right ofBits[23:16] FILT_COEF_X_IM_F1 R/W 0h the center pixel. Used if filt_en is set to '1'. Location : Left or Right ofBits[15:8] FILT_COEF_X_RE_F1 R/W 0h the center pixel.

84 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.83 Register AFh (offset = AFh) [reset = 0h]

Figure 104. Register AFh Table 127. Register AF Field Descriptions

7.6.2.84 Register B0h (offset = B0h) [reset = 0h]

Figure 105. Register B0h Table 128. Register B0 Field Descriptions

7.6.2.85 Register B1h (offset = B1h) [reset = 5004h]

Figure 106. Register B1h

0 DELAY_FB_CORR_MODE DELAY_FB_DC_CORR_MODE FB_ERROR_CNT_THRESHOLD

Table 129. Register B1 Field Descriptions

7.6.2.86 Register B2h (offset = B2h) [reset = C00h]

Figure 107. Register B2h Table 130. Register B2 Field Descriptions

86 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.2.87 Register B3h (offset = B3h) [reset = 800h]

Figure 108. Register B3h Table 131. Register B3 Field Descriptions

7.6.2.88 Register B6h (offset = B6h) [reset = 0h]

Figure 109. Register B6h Table 132. Register B6 Field Descriptions

7.6.3 Serial Interface Register Map

Table 133. TG Register Map

88 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.3.1 Register 2h (offset = 2h) [reset = 0h]

Figure 110. Register 2h Table 134. Register 02 Field Descriptions

7.6.3.2 Register Ch (offset = Ch) [reset = 100000h]

Figure 111. Register Ch Table 135. Register 0C Field Descriptions

7.6.3.3 Register Dh (offset = Dh) [reset = 100000h]

Figure 112. Register Dh Table 136. Register 0D Field Descriptions

7.6.3.4 Register Eh (offset = Eh) [reset = 04h]

Figure 113. Register Eh Table 137. Register 0E Field Descriptions

90 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.3.5 Register Fh (offset = Fh) [reset = 49Ah]

Figure 114. Register Fh Table 138. Register 0F Field Descriptions

7.6.3.6 Register 12h (offset = 12h) [reset = 0h]

Figure 115. Register 12h Table 139. Register 12 Field Descriptions

7.6.3.7 Register 1Fh (offset = 1Fh) [reset = EF0000h]

Figure 116. Register 1Fh Table 140. Register 1F Field Descriptions end address for row addrBits[23:16] ROW_END R/W EFh bus for default ROI.

92 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.3.8 Register 20h (offset = 20h) [reset = 0h]

Figure 117. Register 20h Table 141. Register 20 Field Descriptions

7.6.3.9 Register 21h (offset = 21h) [reset = 40009Fh]

Figure 118. Register 21h Table 142. Register 21 Field Descriptions Bits[7:3] COL_END R/W 13h ROI.

7.6.3.10 Register 22h (offset = 22h) [reset = 12020h]

Figure 119. Register 22h Table 143. Register 22 Field Descriptions

7.6.3.11 Register 80h (offset = 80h) [reset = 1h]

Figure 120. Register 80h Table 144. Register 80 Field Descriptions

7.6.3.12 Register 81h (offset = 81h) [reset = A0h]

Figure 121. Register 81h Table 145. Register 81 Field Descriptions

94 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

7.6.3.13 Register 82h (offset = 82h) [reset = 186A0h]

Figure 122. Register 82h Table 146. Register 82 Field Descriptions

7.6.3.14 Register 83h (offset = 83h) [reset = 44h]

Figure 123. Register 83h Table 147. Register 83 Field Descriptions unpredicatable when setBits[7:4] SUB_FRAME_CNT_MAX R/W 4h to other values.

7.6.3.15 Register CCh (offset = CCh) [reset = 400003h]

Figure 124. Register CCh Table 148. Register CC Field Descriptions

7.6.3.16 Register D6h (offset = D6h) [reset = 1h]

Figure 125. Register D6h Table 149. Register D6 Field Descriptions

96 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

not recommended. Application information is covered as part of the OPT8241 data sheet.

8.2 Typical Application

Figure 126. TFC Application Diagram

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com

9 Power Supply Recommendations

9.1 Power-Up Sequence

The power rails VCCA, VCCIO, VCCD_PLL, and VCC_INT can come up in any order. All the rails have to rise monotonically to the recommended voltage levels within tRAMP time (see Figure 16). A power on reset (POR) is internally generated as soon as all the power rails are within the recommended levels.

98 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: OPT9221

www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015

10 Layout

10.1 Layout Guidelines

10.1.1 DDR Placement and Routing

The DDR2 interface on the OPT9221 device works at a frequency of 144 MHz. It is recommended to place the DDR2 memory IC as close as possible to the device to avoid any signal integrity issues. All the nets between OPT9221 and the DDR2 memory IC must have a trace length lesser than 50 mm to avoid using terminations. Considering the relatively lower frequency of operation of DDR2 interface and the short trace lengths, termination resistors on data or address pins may not be necessary for proper functioning of the DDR2 interface.

10.1.2 LVDS Receiver

The sensor data receiver pins (named CAP_) are LVDS pairs. The OPT9221 device does not have internal 100- Ω differential termination. Termination resistors need to be placed externally as close as possible to the OPT9221 device. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 99 Product Folder Links: OPT9221

SBAS703A – JUNE 2015– REVISED JUNE 2015 www.ti.com

10.2 Layout Example

Figure 127.

100 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: OPT9221

www.ti.com SBAS703A – JUNE 2015–REVISED JUNE 2015

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

OPT8241 3D Time-of-Flight Sensor Data Sheet, SBAS704

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 101 Product Folder Links: OPT9221

www.ti.com 30-Jun-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples OPT9221ZVM ACTIVE NFBGA ZVM 256 250 TBD Call TI Call TI 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 30-Jun-2015 Addendum-Page 2

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