OPT3101

OPT3101 ToF-Based Long-Range Proximity and Distance Sensor AFE datasheet (Rev. A)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SBAS883,A]
• PDF pages: 120

Technical content

Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPT3101 SBAS883A – FEBRUARY 2018– REVISED JUNE 2018 OPT3101ToF-BasedLong-RangeProximityandDistanceSensorAFE

1 Features

1• Long-Range Distance Measurement, Obstacle Detection and Avoidance

• Flexibility to Customize Design With a Wide Variety of Photodiodes and Emitters
• Sample Rate up to 4 kHz
• 16-Bit Distance Output at 15-m Unambiguous Range
• De-Aliasing to Extend the Distance Range
• Supports 3 Transmitter Channels for Multi-Zone Operation
• Excellent Ambient and Sunlight Rejection
• 200-nA Full-Scale Signal Current
• 88-dB Signal Phase Dynamic Range at 1 kHz
• Supports DC Ambient up to 200 µA, 60-dB Rejection for Ambient at 1 kHz
• Distance Measurement Independent of Object Reflectivity
• Adaptive HDR to Save Power and Increase the Dynamic Range
• Configurable Event Detection and Interrupt Output Mechanism
• I2C Interface for Control and Data
• Integrated Illumination Driver With Programmable Current Control up to 173 mA
• Integrated Temperature Sensor for Calibration
• Single 3.3-V or 1.8-V and 3.3-V Supply Operation
• Operating Ambient Temperature: –40 to 85°C Application Block Diagram

2 Applications

• Precise Long-Range Distance Measurement – Background Suppression and Accurate Object Counting in High-Speed Conveyor Belt Systems – Precise Displacement Sensing in Factory Automation – Non-Contact Distance and/or Level Measurement in Harsh Environments (High- Temperature or Hazardous Conditions)
• Obstacle Detection and Avoidance – Precise Distance Measurement for Drone Landing and Navigation – Cliff and Edge Detection in Vacuum Cleaners (No False Triggers From Dark Carpets) – Perimeter Scan in Automatic Guided Vehicle Like Lawnmowers, Robots – Obstruction Sensing in Applications Such as Smoke Detectors, Emergency Exits

3 Description

The OPT3101 device is a high-speed, high-resolution AFE for continuous-wave, time-of-flight based proximity sensing and range finding. The device integrates the complete depth processing pipeline that includes the ADC, timing sequencer, and the digital processing engine. The device also has a built- in illumination driver that covers most of the target applications. Given the high ambient rejection ratio, the device can support very high ambient conditions, including full sunlight of 130 klx. The timing sequencer is highly configurable to provide for application-specific trade-offs of power versus performance. The device provides depth data that consists of phase, amplitude, and ambient measurements. The calibration subsystem supports phase-data calibration for inaccuracies resulting from temperature and crosstalk. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) OPT3101 VQFN (28) 5.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.

SBAS883A – FEBRUARY 2018– REVISED JUNE 2018 www.ti.com Product Folder Links: OPT3101 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents

11.2 Receiving Notification of Documentation

12 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (February 2018) to Revision A Page

13SCL_S 14SDA_S

15 SCL_M

16 SDA_M

17 RST_MS

18 REG_MODE

19 DVDD

20 AVDD3

21 AVDD

23 AVSS

24 INM

25 INP

26 AVSS

27 AVSS

www.ti.com SBAS883A – FEBRUARY 2018– REVISED JUNE 2018 Product Folder Links: OPT3101 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) This column provides the I/O voltage domain of the input and output pins.

5 Pin Configuration and Functions

(RHF Package) (28-Pin VQFN) Top View NC – No internal connection Pin Functions PIN I/O TYPE(1) DESCRIPTION NAME NO. A0 28 I AVDD I2C slave LSB0 address bit A1 1 I AVDD I2C slave LSB1 address bit A2 2 I AVDD I2C slave LSB2 address bit AVDD 21 — — 1.8-V analog supply AVDD3 20 — — 3.3-V analog supply AVSS 23, 26, 27 — — Analog ground DVDD 19 — — 1.8-V digital supply GP1 11 O IOVDD General-purpose output GP2 12 I/O IOVDD General-purpose output, CLKREF input INM 24 I AVDD AFE negative input. Connect photodiode equivalent capacitance. Connect the other end of the capacitor to ground AVSS. INP 25 I AVDD AFE positive input. Connect photodiode cathode. Connect the Anode of the photodiode to ground AVSS. IOVDD 9, 10 — — Supply for I/O and illumination driver IOVSS 3, 8 — — Ground for digital and I/O NC 22 — — No internal connection REG_MODE 18 I IOVDD Mode to select internal regulator for 1.8-V supplies (AVDD, DVDD)

SBAS883A – FEBRUARY 2018– REVISED JUNE 2018 www.ti.com Product Folder Links: OPT3101 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN I/O TYPE(1) DESCRIPTION NAME NO. RST_MS 17 I IOVDD Active-low global reset, monoshot trigger. There is no internal pullup on this pin. Connect this pin to the host controller or add a pullup resistor. SCL_M 15 O IOVDD I2C master clock. Connect with a 10-kΩ resistor to a 3.3-V supply. SCL_S 13 I IOVDD I2C slave clock. Connect with a 10-kΩ resistor to a 3.3-V supply. SDA_M 16 I/O IOVDD I2C master data. Connect with a 10-kΩ resistor to a 3.3-V supply. SDA_S 14 I/O IOVDD I2C slave data. Connect with a 10-kΩ resistor to a 3.3-V supply. TX0 7 O IOVDD Illumination driver output. Connect to LED cathode. Anode should be connected to a supply. TX1 5 O IOVDD Illumination driver output. Connect to LED cathode. Anode should be connected to a supply. TX2 4 O IOVDD Illumination driver output. Connect to LED cathode. Anode should be connected to a supply. VSSL 6 — — Illumination driver ground. Thermal pad — — — Thermal pad of the device. Connect thermal pad to AVSS PCB ground plane using multiple vias for good thermal performance.

www.ti.com SBAS883A – FEBRUARY 2018– REVISED JUNE 2018 Product Folder Links: OPT3101 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) VCC is equal to IOVDD or AVDD, based on the I/O voltage domain listed in the Pin Functions table.

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted) (1) MIN MAX UNIT IOVDD Digital I/O supply –0.3 4 V AVDD3 Analog supply –0.3 4 V AVDD Analog supply –0.3 2.2 V DVDD Digital supply –0.3 2.2 V VI Input voltage at input pins –0.3 VCC + 0.3 (2) V VO Output voltage at output pins –0.3 VCC + 0.3 (2) V TJ Junction temperature –40 125 °C Tstg Storage temperature –40 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V (ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±1000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±250 (1) VCC is equal to IOVDD or AVDD, based on the I/O voltage domain listed in the Pin Functions table.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT IOVDD Digital I/O supply 1.7 1.8 to 3.3 3.6 V AVDD3 Analog supply 3 3.3 3.6 V AVDD Analog supply 1.7 1.8 1.9 V DVDD Digital supply 1.7 1.8 1.9 V VDRV TX0, TX1, TX2 pin voltage 0.7 3.6 V VI Input voltage at input pins –0.1 VCC + 0.3 (1) V VO Output voltage at output pins –0.1 VCC + 0.3 (1) V TA Ambient temperature –40 85 °C

SBAS883A – FEBRUARY 2018– REVISED JUNE 2018 www.ti.com Product Folder Links: OPT3101 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

6.4 Thermal Information

THERMAL METRIC (1) OPT3101 UNITRHF (QFN)

28 PINS

RθJA Junction-to-ambient thermal resistance 32.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 21.6 °C/W RθJB Junction-to-board thermal resistance 10.8 °C/W ΨJT Junction-to-top characterization parameter 0.3 °C/W ΨJB Junction-to-board characterization parameter 10.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.6 °C/W (1) Noise is higher by 20% with a photodiode capacitance of 6 pF at the AFE input. (2) IambMax is programmable through register setting IAMB_MAX_SEL. (3) Reference, oscillator, and ambient cancellation are not powered down.

6.5 Electrical Characteristics

All specifications at TA = 25°C, VAVDD = 1.8 V, VAVDD3 = 3.3 V, VDVDD = 1.8 V, VIOVDD = 3.3 V, IambMax = 20 µA, photodiode with a capacitance of 2 pF at AFE input unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AFE Iref Full-scale signal current at fmod 200 nA Inoise AFE input-referred current noise 1.5(1) pA/√Hz IambMax Maximum ambient dc current at input AVDD3 = 3.3 V 200 (2) µA µ1000Hz Ambient attenuation at 1000 Hz 60 dB VR Bias voltage at INM, INP 1 V Cin Maximum external photodiode capacitance at input 6 pF fmod Modulation frequency 10 MHz sps Sample rate 4000 Hz tPU,Deepsleep Deep sleep recovery time Monoshot mode only 1 ms tPU,Standby Standby recovery time (3) 50 µs ILLUMINATION DRIVER IDRV Maximum built-in illumination driver current 173.6 mA POWER (ACTIVE MODE AT MAXIMUM FRAME RATE) IAVDD 1.8-V analog supply current 11.6 mA IDVDD 1.8-V digital supply current 5.7 mA IAVDD3 3.3-V analog supply current 0.5 mA IIOVDD 3.3-V I/O supply current 0.7 mA POWER (DEEP SLEEP MODE) IAVDD 1.8-V analog supply current 1 µA IDVDD 1.8-V digital supply current 3 µA IAVDD3 3.3-V analog supply current 1 µA IIOVDD 3.3-V I/O current 2 µA POWER (ACTIVE MODE AT MAXIMUM FRAME RATE), INTERNAL LDO MODE IAVDD3 3.3-V analog supply current Internal LDO mode 17.9 mA IIOVDD 3.3-V I/O supply current Internal LDO mode 0.7 mA POWER (DEEP SLEEP MODE), INTERNAL LDO MODE IAVDD3 3.3-V analog supply current Internal LDO mode 80 µA IIOVDD 3.3-V I/O supply current Internal LDO mode 2 µA CMOS I/Os

www.ti.com SBAS883A – FEBRUARY 2018– REVISED JUNE 2018 Product Folder Links: OPT3101 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) All specifications at TA = 25°C, VAVDD = 1.8 V, VAVDD3 = 3.3 V, VDVDD = 1.8 V, VIOVDD = 3.3 V, IambMax = 20 µA, photodiode with a capacitance of 2 pF at AFE input unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (4) VCC is equal to IOVDD or AVDD, based on the I/O voltage domain listed in the Pin Functions table. VIH Input high-level threshold 0.7 × VCC V VIL Input low-level threshold 0.3 × VCC V VOH Output high level IOH = –2 mA VCC (4) – 0.45 V IOH = –8 mA VCC (4) – 0.5 VOL Output low level IOL = 2 mA 0.35 V IOL = 8 mA 0.65 II Input pin leakage current Pins with pullup, pulldown resistor ±50 µA Pins without pullup, pulldown resistor ±10 CI Input capacitance 5 pF IOH Maximum output current high level 10 mA IOL Maximum output current low level 10 mA

6.6 Timing Requirements

RSTZ_MS Pin tPWMonoShot Pulse duration of monoshot trigger 0.1 1 µs tPWReset Reset pulse duration 30 µs I2C Slave fSCL I 2 C slave SCL operating frequency 400 kHz

6.7 Typical Characteristics

a capacitance of 2 pF at INP and INM, unless otherwise noted. Figure 1. Distance Standard Deviation vs AFE Input Signal Figure 2. AFE Thermal Noise vs Maximum Ambient Current Figure 3. Illumination Driver I-V Characteristics

6.7.1 Continuous Mode

Figure 4. Supply Current in Continuous Mode Figure 5. Supply Current in Continuous Mode with Internal

6.7.2 Monoshot Mode

Figure 6. AVDD Supply Current in Monoshot Mode Figure 7. DVDD Supply Current in Monoshot Mode

6.7.3 Monoshot Mode With Internal LDO

Figure 11. AVDD3 Supply Current in Monoshot Mode With Figure 12. IOVDD Supply Current in Monoshot Mode With Figure 13. Illumination Supply Current in Monoshot Mode With Internal LDO

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7 Detailed Description

7.1 Overview

The OPT3101 device is a fully integrated analog front end (AFE) based on the time-of-flight (ToF) principle using active illumination. The OPT3101 AFE connects to an external illuminator (LED, VCSEL, or LASER) to transmit modulated optical signals, and reflected signals are received by an external photodiode which connects to the input of the AFE. The received signal is converted to amplitude and phase information by the AFE and depth engine. This output is stored in registers, which can be read out through the device I2C interface. The OPT3101 AFE has the following blocks:

• Timing generator: generates the sequencing signals for the sensor, illumination, and depth processor
• ToF receiver AFE
• Illumination driver
• Depth engine: calculates phase and amplitude
• I2C slave for configuration and output data interface of the device registers by the host processor
• I2C master for external temperature sensing, auto load registers from an external EEPROM

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Timing Generator

The timing generator (TG) generates the timing sequence for each frame. The TG has the following features:

• Frame rate control
• Sequencing The following are various modes of operation:
• Continuous or monoshot mode
• Auto high-dynamic-range (HDR) mode or non-HDR mode
• Single-LED or multi-LED mode

Different modes of operation are explained below. Figure 14. Continuous and Monoshot Modes

7.3.1.1 Continuous Operating Mode

are described in Non-HDR Mode and Auto HDR Mode.

7.3.1.2 Monoshot Mode

synchronized capture from an external host. that is > 30 µs. For monoshot trigger, give a pulse duration that is < 1 µs and > 100 ns. Figure 15. Timing for Pin-Triggered Monoshot Mode With RST_MS

register bit and goes into deep sleep state. Figure 16. Timing for Register (MONOSHOT_BIT) Triggered Monoshot Mode Table 1. Monoshot Mode Register Settings MONOSHOT_NUMFRAME 27h[7:2] Number of frames to be captured for every trigger. POWERUP_DELAY 26h[23:10] Register to program the delay from the external trigger to start of frame (FRAME_VD). Delay = (64 × POWERUP_DELAY + 2) × tCLK, tCLK = 25 ns. MONOSHOT_BIT 0h[23] Monoshot trigger register. Write 1 to start sample capture. The bit is auto cleared after capture completion.

7.3.1.3 Non-HDR Mode

(NUM_SUB_FRAMES = 0) in a frame. Table 2. Sample-Rate Configuration Registers Total number of sub-frames in a frame. Each sub-frame is 0.25 ms. Number of sub frames in a frame = NUM_SUB_FRAMES + 1. This number must be equal or greater than NUM_AVG_SUB_FRAMES. Averaging sub-frames = NUM_AVG_SUB_FRAMES + 1. recommended to use number of averaged sub-frames as a power of 2.

(1) N1 = 10,000; number of 40-MHz clocks in a sub-frame. (2) N2 = NUM_SUB_FRAMES + 1 is the number of sub-frames in a frame, programmable in the range of 1 to 212. Figure 17. Frame Timing Diagram

7.3.1.4 Auto HDR Mode

Figure 18. When the illumination driver current is high and the amplitude exceeds the saturation threshold, switched to the higher current. Figure 18. Auto HDR Mode: State Diagram

Table 3. HDR Mode Configuration Registers SEL_HDR_MODE 2Ah[16] Chooses which current to use when EN_ADAPTIVE_HDR = 0.

7.3.1.5 Multi Channel Mode

continuous mode, monoshot mode, non-HDR mode, or auto HDR mode. Table 4. Multi LED Configuration Registers EN_TX_SWITCH 2Ah[0] Enable switching between Illumination channels TX0, TX1, TX2. SEL_TX_CH 2Ah[2:1] Selects the ILLUM channels when switching is disabled. TX_SEQ_REG 2Ah[14:3] Stores the sequence of ILLUM channel switching in this register.

7.3.2 AFE

current of 200 nA peak-to-peak and supports a photodiode capacitance up to 6 pF.

Figure 21. AFE, Photodiode Interface

• Isig_afe = signal current entering the AFE
• Inoise = Input referred current noise floor of the AFE = 1.5 pA/√Hz with IAMB_MAX=20 µA and CPD= 2pF (Figure 2)
• BW = Signal measurement bandwidth (4) where
• σphase= Phase standard deviation in radians
• SNR is calculated from Equation 4 (5) where
• σdistance= Distance standard deviation in meters
• c = Speed of light
• fMOD = 10 MHz, modulation frequency (6) For example, with an AFE signal current of 20 nA peak-to-peak (–20 dBFS), frame rate of 125 Hz (NUM_AVG_SUB_FRAMES = 31), SNR = 1193 = 61.5 dB. Depth noise standard deviation for this scenario is σdistance = 15 m / (2π) / 1193 = 2 mm.

7.3.3 Ambient Cancellation

The ambient cancellation circuit provides the dc and low-frequency diode current while biasing the diode at 1 V. 0 (20 µA ambient current support). Below frequency fc1 (approximately at 10 Hz), attenuation becomes first-order. So for a frequency of 1 kHz, the rejection would be (50 kHz / 1 kHz) × 2 = 2500 = 68 dB.

Figure 22. Ambient Cancellation Circuit Frequency Response Figure 2. For low-ambient systems, the lower value of maximum ambient support should be used to reduce the can be calculated from the AMB_DATA using Equation 7.

• IAMB_MAX= Maximum ambient current supported. Listed in Table 5
• AMB_CALIB = ambient ADC output in the dark. Typical value is 64, could vary by few codes from device to device. (7)

Table 5. Ambient Cancellation Register Settings

7.3.4 Oscillator

for the on-chip oscillator variations for continuous background frequency calibration.

7.3.5 CLKGEN

Table 6. Register Settings to Change the Phase of Illumination SHIFT_ILLUM_PHASE 71h[6:3] Mode to generate different Illumination clock phases.

7.3.6 Illumination Driver

Figure 23. Illumination Driver Block Diagram range of 0.5 mA to 7.5 mA in steps of 0.5 mA using ILLUM_DC_CURR_DAC. Table 7. Illumination Driver Register Settings

7.3.7 Depth Engine

• Phase offset
• Phase correction with temperature
• Crosstalk
• Frequency
• Square wave nonlinearity
• Phase correction with ambient For a detailed calibration procedure, see OPT3101 Distance Sensor System Calibration

Table 8. Phase Offset Correction Registers

Table 8. Phase Offset Correction Registers (continued) Table 9. Phase Temperature Coefficient Registers Table 10. Phase Temperature Coefficient Registers for External Temperature Sensor

Table 10. Phase Temperature Coefficient Registers for External Temperature Sensor (continued) Table 11. Ambient-Dependent Phase Correction Registers SCALE_AMB_PHASE_CORR_COEFF B5h[2:0] Scaling factor for ambient-based PWL phase correction. Table 12. Internal Crosstalk Correction Registers See OPT3101 Distance Sensor System Calibration. frames. At least 5τ should be allowed for settling of crosstalk measurement. USE_XTALK_FILT_INT 2Eh[5] Select filter or direct sampling for internal crosstalk measurement. Table 13. Illumination Crosstalk Correction Registers no modulated light is received. See OPT3101 Distance Sensor System Calibration. USE_XTALK_FILT_ILLUM 2Eh[7] Select filter or direct sampling for illumination crosstalk measurement.

Table 13. Illumination Crosstalk Correction Registers (continued) Table 14. Frequency Correction Registers EN_FLOOP 0Fh[22] Enables the frequency calibration block. REF_COUNT_LIMIT 0Fh[14:0] This sets the limit for reference-clock count. system clock = 40 MHz / 210 = 39.0625 kHz to bring close to 32.768 kHz. Enables continuous frequency calibration. 1 – Frequency is continuously measured. FREQ_COUNT_READ_REG 10h[14:0] Read the register which holds the value of frequency calibration. START_FREQ_CALIB 0Fh[16] Starts the frequency calibration. Table 15. Phase Nonlinearity Correction Registers

16 MOD

Table 15. Phase Nonlinearity Correction Registers (continued)

7.3.8 Output Data

Equation 8. A single code of PHASE_OUT is 228.7µm.

• c = Speed of light
• fMOD = 10 MHz, modulation frequency (8) Along with phase and amplitude of the signal, ambient ADC output and temperature sensor output are also stored in the registers. All the output data is stored in contiguous registers 8, 9, and 10.

Table 16. Output Data Registers

Table 17. Output Data Registers Description PHASE_OUT 08h[15:0] Final calibrated phase. PHASE_OVERFLOW 08h[16] Phase overflow during frequency correction. AMP_OUT 09h[15:0] Amplitude of the signal. TX_CHANNEL 08h[19:18] Indicates which Illumination channel of TX0/TX1/TX2 is used. PHASE_OVER_FLOW_F2 09h[19] Phase overflow of second modulation frequency during frequency correction.

7.3.9 General Purpose I/O

device on-chip oscillator frequency calibration. Table 18. GPIO Configuration Registers GPO1_MUX_SEL 78h[8:6] Select signal for the GP1 output multiplexer. pin for frequency calibration. Select signal for the GP2 output multiplexer.

7.3.10 Temperature Sensor

sensor has a range of –25°C to 125°C. The output of this temperature sensor is accessible from register TMAIN. It can be used for phase temperature compensation.

7.3.11 On-Chip Regulator

and the decoupling capacitor on DVDD should be connected to IOVSS.

7.3.12 Sequencer

TG_SEQ_INT_END, TG_SEQ_INT_MASK_START, and TG_SEQ_INT_MASK_END registers. TG_SEQ_INT_START and TG_SEQ_INT_END define the position of the interrupt pulse within a sub-frame.

• Switching of transmitter channels
• Generating an interrupt based on a phase or amplitude comparison with defined thresholds
• Generating an interrupt based on a phase or amplitude comparison with hysteresis
• Extending the dynamic range using four illumination driver currents
• Performing a de-alias operation to extend the distance range from 15 m to 75 m.

Table 19. Sequencer Commands

0000 NOP

16 cycles the sequencer does not do anything.

0001 WRITE

register values only if EN_PROCESSOR_VALUES = 1.

0010 GOTO

0011 DGOTO

executes next instruction as well. The next command is executed on the same frame VD.

0101 COMP0

1. If the comparison fails, the program counter moves to the line indicated by the operand,

0110 COMP0_INV Similar to COMP but the comparison used is: COMP_IN ≥ COMPARE_REG2

0111 COMP_WINDOW

Table 19. Sequencer Commands (continued)

1000 COMP2

1001 COMP3

COMP_STATUS is set to 1, else to 0.

1010 COMP_HYST

≥ COMPARE_REG2) then COMP_STATUS = 1.

1011 COMP1

1. If the comparison fails the program counter moves to the line indicated by the operand

executes the command and moves to next command at the same interrupt. Table 20. Sequencer STATUS_OUT Register Mapping Table 21. Sequencer Registers Select the value used for comp_in. EN_SEQUENCER 14h[16] Enable the sequencer. ES 14h[17] Uses processor values instead of register values. DIS_INTERRUPT 14h[19] Disables the interrupt which triggers the sequencer. COMMAND19 15h[11:0] to 1Eh[23:12] Sequencer command registers. A total of 20 command registers are available.

7.3.12.1 Interrupt Output

Figure 24. Interrupt Output Using Different Comparison Commands Table 22. Register Settings to Use Sequencer for Generating Interrupt Output GPIO1_OBUF_EN 1 Enable GP1 output buffer. Sequencer enable should be only be changed while TG_EN = 0. register and then enable TG (TG_EN = 1). EN_PROCESSOR_VALUES 1 Enable processor values to control the STATUS_OUT register bits.

7.3.12.2 Super-HDR Mode Using Sequencer

IILLUM_L_TX0.Table 23 lists the register settings to operate the device in super HDR mode using the sequencer. HDR_THR_LOW should be determined by the minimum of the two adaptive HDR settings listed below.

• HDR_THR_HIGH × ILLUM_DAC_L_TX0 / ILLUM_DAC_H_TX0
• HDR_THR_HIGH × ILLUM_DAC_L_TX1 / ILLUM_DAC_H_TX1

Figure 25. Super-HDR Mode Using Sequencer: State Diagram Table 23. Register Settings to Use Sequencer for Super HDR Mode COMMAND1 0xB02 COMP1 command. If COMP_IN > COMPARE_REG1, move to COMMAND2. COMMAND3 0xC00 COMP1_INV command. If COMP_IN < COMPARE_REG2, move to COMMAND0.

500 Should be greater than the hdr High threshold: HDR_THR_HIGH

500 Should be less than the hdr low threshold HDR_THR_LOW. Sequencer enable should be only be changed while TG_EN = 0. register, and then enable TG (TG_EN = 1). EN_PROCESSOR_VALUES 1 Enable processor values to control the STATUS_OUT register bits.

7.4 Programming

host which can be used to interface with an external temperature sensor or external EEPROM.

7.4.1 I2C Slave

can be single R/W or continuous R/W with auto-increment of register address. Table 24. I2C Slave Configuration Registers The individual registers are 24-bit length in this device. However, the register read/write is in chunks of eight bits. an acknowledgement in the case of write. Figure 26 shows the I2C timing for register write operation. Figure 26. I2C Register Write Example followed by [15:8] and then followed by [23:16]. Figure 27 shows the different read/write modes. Figure 27. I2C Slave Interface R/W Modes

7.4.2 I2C Master

also read temperature from an external temperature sensor with the I2C interface (default address of 1001 000). Table 25 lists the register settings to configure the I2C Host.

Table 25. I2C Master Register Settings I2C_SEL_READ_BYTES 07h[19:18] Selects the byte of read data. I2C_READ_DATA 03h[7:0] I2C host read data can be accessed through this register.

7.4.2.1 External Temperature Sensor

temperature changes. An external temperature sensor is required if an external illumination driver is used. Table 26. Register Settings to Enable External Temperature Readout Using I2C 12-bit data. Further averaging not required.

7.4.2.2 External EEPROM

the rest of the memory should be filled with all 0x00 or 0xFF. Table 27. External EEPROM

0 Register address i

1 Register data i[7:0]

2 Register data i[15:8]

3 Register data i[23:16]

4 Register address j

5 Register data j[7:0]

6 Register data j[15:8]

7 Register data j[23:16]

255 Register data k[23:16]

7.4.2.3 External EEPROM Programming

Figure 28. EEPROM Programming Flow Chart Table 28. Register Settings to Write to External EEPROM Using I2C Master I2C_HOST_EN 1 Enable device I2C host.

7.5 Register Maps

7.5.1 Serial Interface Register Map

Table 29. Default Register Map

Table 29. Default Register Map (continued)

0 SCALE_PHASE_TEMP_CO

0 SHIFT_ILLUM_PHASE

7.5.1.1 Register Descriptions

Table 30. Access Type Codes

7.5.1.1.1 Register 0h (Address = 0h) [reset = 0h]

Figure 29. Register 0h

0 I2C_CONT_R

Table 31. Register 00 Field Descriptions

23 MONOSHOT_BIT R/W 0h

22 FORCE_EN_SLAVE R/W 0h

21 FORCE_EN_BYPASS R/W 0h Setting this bit to 1 disables the device I2C host and shorts the I2C host bus

20:7 RESERVED R/W 0h Always read or write 0h. 6 I2C_CONT_RW R/W 0h Enable continuous read/write of the device I2C slave registers. 5:1 RESERVED R/W 0h Always read or write 0h.

0 SOFTWARE_RESET R/W 0h Generates a device reset on writing this bit and resets all the register

settings to default values, including this bit.

7.5.1.1.2 Register 1h (Address = 1h) [reset = 120140h]

Figure 30. Register 1h

Table 32. Register 01 Field Descriptions 23 RESERVED R/W 0h Always read or write 0h. Chooses R/W for I2C host operation. 19 I2C_EN R/W 0h Enables the I2C host.

18 I2C_TRIG_REG R/W 0h The trigger register for I2C transactions

triggered based on the setting of I2C_TRIG_REG. 16:9 RESERVED R/W 0h Always read or write 0h. 8:2 ADDR_SLAVE_EEPROM R/W 50h External EEPROM I2C slave address. 1 SWAP_READ_DATA R/W 0h Setting this bit to 1 reverses the data read by I2C host from [7:0] to [0:7]. 0 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.3 Register 2h (Address = 2h) [reset = 92A4C8h]

Figure 31. Register 2h Table 33. Register 02 Field Descriptions Average external temperature sensor reading.

21 EN_TILLUM_READ R/W 0h

7.5.1.1.4 Register 3h (Address = 3h) [reset = 800000h]

Figure 32. Register 3h Table 34. Register 03 Field Descriptions 23:22 TEMP_AVG_MAIN R/W 0h Average on-chip temperature sensor reading. 21:18 RESERVED R/W 0h Always read or write 0h. 17 I2C_NUM_TRAN R/W 0h The number of I2C host transactions. 0: 1 transaction | 1: 2 transactions. read this is not required to be programmed.

8 INIT_LOAD_DONE R 0h

7:0 I2C_READ_DATA R 0h The I2C host read data.

7.5.1.1.5 Register 4h (Address = 4h) [reset = 17h]

Figure 33. Register 4h Table 35. Register 04 Field Descriptions

23 TILLUM_UNSIGNED R/W 0h Set this bit to 1 when the temperature given by the external temperature

sensor is in unsigned format. 22:20 RESERVED R/W 0h Always read or write 0h. 19:8 TILLUM R 0h The temperature value of the external temperature sensor. 7:0 RESERVED R/W 17h Always read or write 17h.

7.5.1.1.6 Register 5h (Address = 5h) [reset = 80000h]

Figure 34. Register 5h Table 36. Register 05 Field Descriptions 23:22 I2C_NUM_BYTES_TRAN2 R/W 0h Number of bytes used in transaction 2 of the I2C host transaction. 21:16 RESERVED R/W 08h Always read or write 08h. 15:0 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.7 Register 7h (Address = 7h) [reset = 0h]

Figure 35. Register 7h Table 37. Register 07 Field Descriptions Along with this register also set the EN_TILLUM_12B regsiter to 1. 17:16 I2C_NUM_BYTES_TRAN1 R/W 0h Number of bytes used in the transaction 1 of I2C host transaction. 15:8 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.8 Register 8h (Address = 8h) [reset = 0h]

Figure 36. Register 8h

Table 38. Register 08 Field Descriptions 23 FRAME_COUNT0 R 0h Frame counter LSB bit.

22 AMB_OVL_FLAG R 0h Overload flag to indicate ambient saturation

21 MOD_FREQ R 0h Indicates the frequency used.

20 FRAME_STATUS R 0h

crosstalk calibration frame (ILLUM_XTALK_CALIB = 1). 19:18 TX_CHANNEL R 0h Indicates which Illumination channel used. 17 HDR_MODE R 0h Indicates the illumination driver DAC current used.

16 PHASE_OVER_FLOW R 0h PHASE_OUT overflow bit during frequency correction

15:0 PHASE_OUT R 0h Final calibrated phase.

7.5.1.1.9 Register 9h (Address = 9h) [reset = 0h]

Figure 37. Register 9h Table 39. Register 09 Field Descriptions Distance bin in de-alias mode.

19 PHASE_OVER_FLOW_F2 R 0h

during frequency correction.

18 SIG_OVL_FLAG R 0h Overload flag to indicate signal saturation

15:0 AMP_OUT R 0h Amplitude of the received signal.

7.5.1.1.10 Register Ah (Address = Ah) [reset = 0h]

Figure 38. Register Ah Table 40. Register 0A Field Descriptions 11:2 AMB_DATA R 0h Ambient ADC output. Indicates the ambient light. 1:0 FRAME_COUNT2 R 0h Frame counter MSB bits [4:3].

7.5.1.1.11 Register Bh (Address = Bh) [reset = FC009h]

Figure 39. Register Bh Table 41. Register 0B Field Descriptions 9:8 0 R/W 0h Always read or write 0h.

7.5.1.1.12 Register Ch (Address = Ch) [reset = 0h]

Figure 40. Register Ch Table 42. Register 0C Field Descriptions _COEFF0 R/W 0h Coefficient 0 for piecewise linear (PWL) phase correction with ambient.

7.5.1.1.13 Register Dh (Address = Dh) [reset = 6000h]

Figure 41. Register Dh Table 43. Register 0D Field Descriptions

23 EN_TILLUM_12B R/W 0h

22:17 RESERVED R/W 0h Always read or write 0h. Ambient threshold which is used to detect the ambient overload. AMB_OVL_FLAG is set to 1 if it exceeds the threshold. 6:0 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.14 Register Fh (Address = Fh) [reset = 144C4Bh]

Figure 42. Register Fh

Table 44. Register 0F Field Descriptions 23 EN_FREQ_CORR R/W 0h Enable frequency correction for the phase output.

22 EN_FLOOP R/W 0h

Enables the frequency calibration block. 21 EN_AUTO_FREQ_COUNT R/W 0h Determines the value to be used for frequency correction. 16 START_FREQ_CALIB R/W 0h Setting this bit to 1 starts the frequency calibration. 15 RESERVED R/W 0h Always read or write 0h. 14:0 REF_COUNT_LIMIT R/W 4C4Bh This sets the limit for ref-clock count.

7.5.1.1.15 Register 10h (Address = 10h) [reset = 4000h]

Figure 43. Register 10h Table 45. Register 10 Field Descriptions 8] R/W 0h MSB of minimum amplitude threshold below which phase is made FFFFh.

15 EN_CONT_FCALIB R/W 0h

Enables continuous frequency calibration. Frequency is continuously measured.

7.5.1.1.16 Register 11h (Address = 11h) [reset = 0h]

Figure 44. Register 11h

Table 46. Register 11 Field Descriptions ] R/W 0h LSB of minimum amplitude threshold below which phase is made FFFFh.

15 DIS_OVL_GATING R/W 0h

Disable gating of phase output when SIG_OVL_FLAG becomes 1. correction when EN_AUTO_FREQ_COUNT = 0.

7.5.1.1.17 Register 13h (Address = 13h) [reset = 0h]

Figure 45. Register 13h Table 47. Register 13 Field Descriptions 23:19 RESERVED R/W 0h Always read or write 0h. Chooses the value used for comparator input register of sequencer.

7.5.1.1.18 Register 14h (Address = 14h) [reset = 0h]

Figure 46. Register 14h

Table 48. Register 14 Field Descriptions 23:20 RESERVED R/W 0h Always read or write 0h. 19 DIS_INTERRUPT R/W 0h Disables the interrupt that triggers sequencer.

18 STATUS_IN_REG R/W 0h This register is used to control the program flow in the sequencer

17 EN_PROCESSOR_VALUE

16 EN_SEQUENCER R/W 0h Enable the sequencer.

7.5.1.1.19 Register 15h (Address = 15h) [reset = 101063h]

Figure 47. Register 15h Table 49. Register 15 Field Descriptions 23:12 COMMAND1 R/W 101h Sequencer command 1. 11:0 COMMAND0 R/W 63h Sequencer command 0.

7.5.1.1.20 Register 16h (Address = 16h) [reset = 400100h]

Figure 48. Register 16h Table 50. Register 16 Field Descriptions 23:12 COMMAND3 R/W 400h Sequencer command 3. 11:0 COMMAND2 R/W 100h Sequencer command 2.

7.5.1.1.21 Register 17h (Address = 17h) [reset = 0h]

Figure 49. Register 17h Table 51. Register 17 Field Descriptions 23:12 COMMAND5 R/W 0h Sequencer command 5. 11:0 COMMAND4 R/W 0h Sequencer command 4.

7.5.1.1.22 Register 18h (Address = 18h) [reset = 0h]

Figure 50. Register 18h Table 52. Register 18 Field Descriptions 23:12 COMMAND7 R/W 0h Sequencer command 7. 11:0 COMMAND6 R/W 0h Sequencer command 6.

7.5.1.1.23 Register 19h (Address = 19h) [reset = 0h]

Figure 51. Register 19h Table 53. Register 19 Field Descriptions 23:12 COMMAND9 R/W 0h Sequencer command 9. 11:0 COMMAND8 R/W 0h Sequencer command 8.

7.5.1.1.24 Register 1Ah (Address = 1Ah) [reset = 0h]

Figure 52. Register 1Ah Table 54. Register 1A Field Descriptions 23:12 COMMAND11 R/W 0h Sequencer command 11. 11:0 COMMAND10 R/W 0h Sequencer command 10.

7.5.1.1.25 Register 1Bh (Address = 1Bh) [reset = 0h]

Figure 53. Register 1Bh Table 55. Register 1B Field Descriptions 23:12 COMMAND13 R/W 0h Sequencer command 13. 11:0 COMMAND12 R/W 0h Sequencer command 12.

7.5.1.1.26 Register 1Ch (Address = 1Ch) [reset = 0h]

Figure 54. Register 1Ch

Table 56. Register 1C Field Descriptions 23:12 COMMAND15 R/W 0h Sequencer command 15. 11:0 COMMAND14 R/W 0h Sequencer command 14.

7.5.1.1.27 Register 1Dh (Address = 1Dh) [reset = 0h]

Figure 55. Register 1Dh Table 57. Register 1D Field Descriptions 23:12 COMMAND17 R/W 0h Sequencer command 17. 11:0 COMMAND16 R/W 0h Sequencer command 16.

7.5.1.1.28 Register 1Eh (Address = 1Eh) [reset = 0h]

Figure 56. Register 1Eh Table 58. Register 1E Field Descriptions 23:12 COMMAND19 R/W 0h Sequencer command 19. 11:0 COMMAND18 R/W 0h Sequencer command 18.

7.5.1.1.29 Register 26h (Address = 26h) [reset = 4000Fh]

Figure 57. Register 26h

Table 59. Register 26 Field Descriptions (FRAME_VD). Delay = (64 × POWERUP_DELAY + 2) × tCLK, tCLK = 25 ns. 9:0 RESERVED R/W Fh Always read or write Fh.

7.5.1.1.30 Register 27h (Address = 27h) [reset = 26AC18h]

Figure 58. Register 27h Table 60. Register 27 Field Descriptions 23:8 MONOSHOT_FZ_CLKCNT R/W 26ACh The CLK count at which a monoshot operation freezes. 7:2 MONOSHOT_NUMFRAME R/W 6h The number of samples to be captured on every monoshot trigger event. 1:0 MONOSHOT_MODE R/W 0h Select monoshot mode.

7.5.1.1.31 Register 29h (Address = 29h) [reset = 3F0FC3h]

Figure 59. Register 29h Table 61. Register 29 Field Descriptions

7.5.1.1.32 Register 2Ah (Address = 2Ah) [reset = 784920h]

Figure 60. Register 2Ah Table 62. Register 2A Field Descriptions

23 ILLUM_DAC_L_TX2[0] R/W 1h Illumination driver current DAC register, ILLUM_DAC_L[0] of TX2 channel

17 RESERVED R/W 0h Always read or write 0h.

16 SEL_HDR_MODE R/W 0h Selects which current to use when EN_ADAPTIVE_HDR = 0

15 EN_ADAPTIVE_HDR R/W 0h

2:1 SEL_TX_CH R/W 0h Selects the illumination channel when channel switching is disabled.

0 EN_TX_SWITCH R/W 0h

Enable switching of illumination channels.

7.5.1.1.33 Register 2Bh (Address = 2Bh) [reset = 6000h]

Figure 61. Register 2Bh

Table 63. Register 2B Field Descriptions 23:22 RESERVED R/W 0h Always read or write 0h. 18:16 ILLUM_SCALE_L_TX0 R/W 0h Illumination driver current scale register of TX0 channel with DAC_L current. switches to ILLUM_DAC_L if the amplitude exceeds this threshold value.

7.5.1.1.34 Register 2Ch (Address = 2Ch) [reset = 800h]

Figure 62. Register 2Ch Table 64. Register 2C Field Descriptions 23:22 RESERVED R/W 0h Always read or write 0h. 18:16 ILLUM_SCALE_L_TX0 R/W 0h Illumination driver current scale register of TX1 channel with DAC_L current.

7.5.1.1.35 Register 2Dh (Address = 2Dh) [reset = 0h]

Figure 63. Register 2Dh

Table 65. Register 2D Field Descriptions

7.5.1.1.36 Register 2Eh (Address = 2Eh) [reset = 8001A0h]

Figure 64. Register 2Eh Table 66. Register 2E Field Descriptions 13 0 R/W 0h Always read or write 0.

12 ILLUM_XTALK_CALIB R/W 0h

such that no modulated light is received. 7 USE_XTALK_FILT_ILLUM R/W 1h Select filter or direct sampling for Illumination crosstalk measurement.

6 USE_XTALK_REG_INT R/W 0h Select register value or internally calibrated value for internal crosstalk

5 USE_XTALK_FILT_INT R/W 1h Select filter or direct sampling for internal crosstalk measurement.

Table 66. Register 2E Field Descriptions (continued)

4 INT_XTALK_CALIB R/W 0h

3 DIS_AUTO_SCALE R/W 0h Disable digital auto scale in the signal path. 0: Auto scale enabled | 1: Auto scale disabled.

7.5.1.1.37 Register 2Fh (Address = 2Fh) [reset = 0h]

Figure 65. Register 2Fh Table 67. Register 2F Field Descriptions

7.5.1.1.38 Register 30h (Address = 30h) [reset = 0h]

Figure 66. Register 30h Table 68. Register 30 Field Descriptions 19:16 RESERVED R/W 0h Always read or write 0h.

Table 68. Register 30 Field Descriptions (continued)

7.5.1.1.39 Register 31h (Address = 31h) [reset = 0h]

Figure 67. Register 31h Table 69. Register 31 Field Descriptions

7.5.1.1.40 Register 32h (Address = 32h) [reset = 0h]

Figure 68. Register 32h Table 70. Register 32 Field Descriptions 19:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.41 Register 33h (Address = 33h) [reset = 0h]

Figure 69. Register 33h Table 71. Register 33 Field Descriptions

7.5.1.1.42 Register 34h (Address = 34h) [reset = 0h]

Figure 70. Register 34h Table 72. Register 34 Field Descriptions 19:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.43 Register 35h (Address = 35h) [reset = 0h]

Figure 71. Register 35h

Table 73. Register 35 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.44 Register 36h (Address = 36h) [reset = 0h]

Figure 72. Register 36h Table 74. Register 36 Field Descriptions TX0 channel with ILLUM_DAC_L_TX0 current.

7.5.1.1.45 Register 37h (Address = 37h) [reset = 0h]

Figure 73. Register 37h Table 75. Register 37 Field Descriptions TILLUM for TX0 channel with ILLUM_DAC_L_TX0 current.

7.5.1.1.46 Register 38h (Address = 38h) [reset = 0h]

Figure 74. Register 38h Table 76. Register 38 Field Descriptions

7.5.1.1.47 Register 39h (Address = 39h) [reset = 0h]

Figure 75. Register 39h Table 77. Register 39 Field Descriptions

7.5.1.1.48 Register 3Ah (Address = 3Ah) [reset = 0h]

Figure 76. Register 3Ah

Table 78. Register 3A Field Descriptions 23 RESERVED R/W 0h Always read or write 0h. TEMP_COEFF_XTALK_QPHASE_HDR<i>_TX<j>; i = 0, 1; j = 0, 1, 2). 16 EN_TEMP_XTALK_CORR R/W 0h Enable crosstalk correction with temperature.

7.5.1.1.49 Register 3Bh (Address = 3Bh) [reset = 0h]

Figure 77. Register 3Bh Table 79. Register 3B Field Descriptions to be read out with IQ_READ_DATA_SEL.

7.5.1.1.50 Register 3Ch (Address = 3Ch) [reset = 0h]

Figure 78. Register 3Ch Table 80. Register 3C Field Descriptions selected to be read out with IQ_READ_DATA_SEL.

7.5.1.1.51 Register 3Dh (Address = 3Dh) [reset = 0h]

Figure 79. Register 3Dh Table 81. Register 3D Field Descriptions

7.5.1.1.52 Register 3Eh (Address = 3Eh) [reset = 0h]

Figure 80. Register 3Eh Table 82. Register 3E Field Descriptions

7.5.1.1.53 Register 3Fh (Address = 3Fh) [reset = 0h]

Figure 81. Register 3Fh Table 83. Register 3F Field Descriptions

2 R/W 0h Calibration temperature of external temperature sensor (TILLUM) for TX2

Table 83. Register 3F Field Descriptions (continued)

7.5.1.1.54 Register 40h (Address = 40h) [reset = 2021E0h]

Figure 82. Register 40h Table 84. Register 40 Field Descriptions 23 RESERVED R/W 0h Always read or write 0h.

22 EN_MULTI_FREQ_PHASE R/W 0h

of the phase is indicated in MOD_FREQ status bit. 21 NCR_CONFIG R/W 1h Select second frequency for de-alias operation. 20:15 BETA0_DEALIAS_SCALE R/W 0h Internal crosstalk scaling for de-alias frequency. β = BETA0_DEALIAS_SCALE / 16. 14:9 ALPHA0_DEALIAS_SCALE R/W 10h Internal crosstalk scaling for de-alias frequency. α = ALPHA0_DEALIAS_SCALE / 16. 8:1 RESERVED R/W F0h Always read or write F0h. 0 EN_DEALIAS_MEAS R/W 0h Enables de-alias measurement.

7.5.1.1.55 Register 41h (Address = 41h) [reset = 10h]

Figure 83. Register 41h

Table 85. Register 41 Field Descriptions 11:6 BETA1_DEALIAS_SCALE R/W 0h Illumination crosstalk scaling for de-alias frequency. 5:0 ALPHA1_DEALIAS_SCALE R/W 10h Illumination crosstalk scaling for de-alias frequency.

7.5.1.1.56 Register 42h (Address = 42h) [reset = 0h]

Figure 84. Register 42h Table 86. Register 42 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.57 Register 43h (Address = 43h) [reset = 81h]

Figure 85. Register 43h Table 87. Register 43 Field Descriptions

1 R/W 0h Calibration temperature of external temperature sensor (TILLUM) for TX1

illumination channel with current of ILLUM_DAC_H_TX1. OEFF R/W 2h Scaling factor for phase temperature coefficient. 5:2 RESERVED R/W 0h Always read or write 0h.

1 EN_TEMP_CORR R/W 0h

Enables temperature correction for phase.

Table 87. Register 43 Field Descriptions (continued) 0 EN_PHASE_CORR R/W 1h Enables phase offset correction.

7.5.1.1.58 Register 44h (Address = 44h) [reset = 0h]

Figure 86. Register 44h Table 88. Register 44 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.59 Register 45h (Address = 45h) [reset = 0h]

Figure 87. Register 45h Table 89. Register 45 Field Descriptions

7.5.1.1.60 Register 46h (Address = 46h) [reset = 0h]

Figure 88. Register 46h

Table 90. Register 46 Field Descriptions

7.5.1.1.61 Register 47h (Address = 47h) [reset = 800800h]

Figure 89. Register 47h Table 91. Register 47 Field Descriptions

0 R/W 800h Calibration temperature of external temperature sensor (TILLUM) for TX0

7.5.1.1.62 Register 48h (Address = 48h) [reset = 0h]

Figure 90. Register 48h Table 92. Register 48 Field Descriptions

0 R/W 0h Calibration temperature of external temperature sensor (TILLUM) for TX0

7.5.1.1.63 Register 49h (Address = 49h) [reset = 0h]

Figure 91. Register 49h Table 93. Register 49 Field Descriptions

7.5.1.1.64 Register 4Ah (Address = 4Ah) [reset = 0h]

Figure 92. Register 4Ah Table 94. Register 4A Field Descriptions 23:20 RESERVED R/W 0h Always read or write 0h. 1 RESERVED R/W 0h Always read or write 0h.

0 EN_NL_CORR R/W 0h Enables square wave harmonic nonlinearity correction

7.5.1.1.65 Register 4Bh (Address = 4Bh) [reset = 407h]

Figure 93. Register 4Bh

Table 95. Register 4B Field Descriptions 23:16 RESERVED R 0h Always read or write 0h. illumination channel with current of ILLUM_DAC_L_TX0.

7.5.1.1.66 Register 4Ch (Address = 4Ch) [reset = F23Eh]

Figure 94. Register 4Ch Table 96. Register 4C Field Descriptions 23:16 RESERVED R 0h Always read or write 0h. illumination channel with current of ILLUM_DAC_L_TX0.

7.5.1.1.67 Register 4Dh (Address = 4Dh) [reset = 1144h]

Figure 95. Register 4Dh Table 97. Register 4D Field Descriptions illumination channel with current of ILLUM_DAC_L_TX0.

7.5.1.1.68 Register 4Eh (Address = 4Eh) [reset = F881h]

Figure 96. Register 4Eh Table 98. Register 4E Field Descriptions

7.5.1.1.69 Register 50h (Address = 50h) [reset = 200100h]

Figure 97. Register 50h

0 OVERRIDE_CL

Table 99. Register 50 Field Descriptions 23 RESERVED R/W 0h Always read or write 0h.

22 OVERRIDE_CLKGEN_RE

21:4 RESERVED R/W 2 0010h Always read or write 2 0010h.

3 CLIP_MODE_OFFSET R/W 0h

2 CLIP_MODE_TEMP R/W 0h

1 CLIP_MODE_NL R/W 0h

0 CLIP_MODE_FC R/W 0h Chooses clipping or wrap around when applying freq-correction for phase.

7.5.1.1.70 Register 51h (Address = 51h) [reset = 0h]

Figure 98. Register 51h Table 100. Register 51 Field Descriptions

7.5.1.1.71 Register 52h (Address = 52h) [reset = 0h]

Figure 99. Register 52h Table 101. Register 52 Field Descriptions

7.5.1.1.72 Register 53h (Address = 53h) [reset = 0h]

Figure 100. Register 53h

Table 102. Register 53 Field Descriptions

7.5.1.1.73 Register 54h (Address = 54h) [reset = 0h]

Figure 101. Register 54h Table 103. Register 54 Field Descriptions 19:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.74 Register 55h (Address = 55h) [reset = 0h]

Figure 102. Register 55h Table 104. Register 55 Field Descriptions

7.5.1.1.75 Register 56h (Address = 56h) [reset = 0h]

Figure 103. Register 56h Table 105. Register 56 Field Descriptions 19:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.76 Register 57h (Address = 57h) [reset = 0h]

Figure 104. Register 57h Table 106. Register 57 Field Descriptions

7.5.1.1.77 Register 58h (Address = 58h) [reset = 0h]

Figure 105. Register 58h

Table 107. Register 58 Field Descriptions 19:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.78 Register 59h (Address = 59h) [reset = 0h]

Figure 106. Register 59h Table 108. Register 59 Field Descriptions

7.5.1.1.79 Register 5Ah (Address = 5Ah) [reset = 0h]

Figure 107. Register 5Ah Table 109. Register 5A Field Descriptions 19:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.80 Register 5Bh (Address = 5Bh) [reset = 0h]

Figure 108. Register 5Bh Table 110. Register 5B Field Descriptions TX1 channel with ILLUM_DAC_H_TX1 current. TX1 channel with ILLUM_DAC_L_TX1 current. TX0 channel with ILLUM_DAC_H_TX0 current.

7.5.1.1.81 Register 5Ch (Address = 5Ch) [reset = 0h]

Figure 109. Register 5Ch Table 111. Register 5C Field Descriptions TILLUM for TX0 channel with ILLUM_DAC_H_TX0 current. TX2 channel with ILLUM_DAC_H_TX2 current. TX2 channel with ILLUM_DAC_H_TX2 current.

7.5.1.1.82 Register 5Dh (Address = 5Dh) [reset = 0h]

Figure 110. Register 5Dh

Table 112. Register 5D Field Descriptions TILLUM for TX2 channel with ILLUM_DAC_L_TX2 current. TILLUM for TX1 channel with ILLUM_DAC_H_TX1 current. TILLUM for TX1 channel with ILLUM_DAC_L_TX1 current.

7.5.1.1.83 Register 5Eh (Address = 5Eh) [reset = 0h]

Figure 111. Register 5Eh Table 113. Register 5E Field Descriptions TILLUM for TX2 channel with ILLUM_DAC_H_TX2 current.

7.5.1.1.84 Register 5Fh (Address = 5Fh) [reset = 0h]

Figure 112. Register 5Fh Table 114. Register 5F Field Descriptions

Table 114. Register 5F Field Descriptions (continued)

7.5.1.1.85 Register 60h (Address = 60h) [reset = 0h]

Figure 113. Register 60h Table 115. Register 60 Field Descriptions

7.5.1.1.86 Register 61h (Address = 61h) [reset = 0h]

Figure 114. Register 61h Table 116. Register 61 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.87 Register 64h (Address = 64h) [reset = 280C00h]

Figure 115. Register 64h Table 117. Register 64 Field Descriptions 17:0 RESERVED R/W 0C00h Always read or write 0C00h.

7.5.1.1.88 Register 65h (Address = 65h) [reset = 0h]

Figure 116. Register 65h Table 118. Register 65 Field Descriptions

23 DIS_OVLDET R/W 0h

Disables AFE overload detection. 22:0 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.89 Register 6Eh (Address = 6Eh) [reset = 20000h]

Figure 117. Register 6Eh

Table 119. Register 6E Field Descriptions 23:20 RESERVED R/W 0h Always read or write 0h.

19 EN_TEMP_CONV R/W 0h

18:0 RESERVED R/W 2 0000h Always read or write 2 0000h.

7.5.1.1.90 Register 71h (Address = 71h) [reset = 0h]

Figure 118. Register 71h Table 120. Register 71 Field Descriptions 23:18 RESERVED R/W 0h Always read or write 0h.

17 UNMASK_ILLUMEN_INTX

16 EN_ILLUM_CLK_GPIO R/W 0h

15 ILLUM_CLK_GPIO_MODE R/W 0h

Disable ILLUM_EN_TX0 gating ILLUM_CLK going to GPIO. 14:13 RESERVED R/W 0h Always read or write 0h.

12 DIS_ILLUM_CLK_TX R/W 0h

11 INVERT_AFE_CLK R/W 0h Invert CLK input to AFE. 0: AFE CLK is not inverted | 1: AFE CLK is inverted. 10 RESERVED R/W 0h Always read or write 0h. 9 INVERT_TG_CLK R/W 0h Invert CLK input to timing generation unit. 0: TG CLK is not inverted | 1: TG CLK is inverted. 8 SHUT_CLOCKS R/W 0h Shut down all CLK signals at modulation frequency. 0: Modulation clocks is alive | 1: Modulation clock is shut down. 7 RESERVED R/W 0h Always read or write 0h. 6:3 SHIFT_ILLUM_PHASE R/W 0h Shift the phase of ILLUM_CLK. PHASE = SHIFT_ILLUM_PHASE × 22.5°.

2 DEALIAS_FREQ R/W 0h

only when OVERRIDE_CLKGEN_REG = 1.

Table 120. Register 71 Field Descriptions (continued) 0 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.91 Register 72h (Address = 72h) [reset = C0h]

Figure 119. Register 72h Table 121. Register 72 Field Descriptions 23:8 RESERVED R/W 0h Always read or write 0h. 3:0 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.92 Register 76h (Address = 76h) [reset = 0h]

Figure 120. Register 76h Table 122. Register 76 Field Descriptions 23:12 RESERVED R/W 0h Always read or write 0h. 11 PDN_GLOBAL R/W 0h Global power down of all the blocks. 10 RESERVED R/W 0h Always read or write 0h. 9 DIS_GLB_PD_I2CHOST R/W 0h Disable global power down of I2C host. 0: Enable global power down | 1: Disable global power down. 8 DIS_GLB_PD_OSC R/W 0h Disable global power down of main oscillator. 0: Enable global power down | 1: Disable global power down. 7 RESERVED R/W 0h Always read or write 0h. 6 DIS_GLB_PD_AMB_ADC R/W 0h Disable global power down of ambient ADC. 0: Enable global power down | 1: Disable global power down.

Table 122. Register 76 Field Descriptions (continued) 5 DIS_GLB_PD_AMB_DAC R/W 0h Disable global power down of ambient cancellation. 0: Enable global power down | 1: Disable global power down. 4 DIS_GLB_PD_AFE_DAC R/W 0h Disable global power down of AFE DAC. 0: Enable global power down | 1: Disable global power down. 3 DIS_GLB_PD_AFE R/W 0h Disable global power down of AFE. 0: Enable global power down | 1: Disable global power down. 2 DIS_GLB_PD_ILLUM_DRV R/W 0h Disable global power down of illumination driver. 0: Enable global power down | 1: Disable global power down.

1 DIS_GLB_PD_TEMP_SEN

S R/W 0h Disable global power down of temperature sensor. 0: Enable global power down | 1: Disable global power down. 0 DIS_GLB_PD_REFSYS R/W 0h Disable global power down of reference. 0: Enable global power down | 1: Disable global power down.

7.5.1.1.93 Register 77h (Address = 77h) [reset = 0h]

Figure 121. Register 77h Table 123. Register 77 Field Descriptions 23:10 RESERVED R/W 0h Always read or write 0h.

9 EN_DYN_PD_I2CHOST_O

SC R/W 0h Enable dynamic power down of I2C host oscillator. 0: Disable dynamic power down | 1: Enable dynamic power down. 8 EN_DYN_PD_OSC R/W 0h Enable dynamic power down of main oscillator. 0: Disable dynamic power down | 1: Enable dynamic power down. 7 RESERVED R/W 0h Always read or write 0h. 6 EN_DYN_PD_AMB_ADC R/W 0h Enable dynamic power down of ambient ADC. 0: Disable dynamic power down | 1: Enable dynamic power down. 5 EN_DYN_PD_AMB_DAC R/W 0h Enable dynamic power down of ambient cancellation. 0: Disable dynamic power down | 1: Enable dynamic power down. 4 EN_DYN_PD_AFE_DAC R/W 0h Enable dynamic power down of AFE DAC. 0: Disable dynamic power down | 1: Enable dynamic power down. 3 EN_DYN_PD_AFE R/W 0h Enable dynamic power down of AFE. 0: Disable dynamic power down | 1: Enable dynamic power down. 2 EN_DYN_PD_ILLUM_DRV R/W 0h Enable dynamic power down of illumination driver. 0: Disable dynamic power down | 1: Enable dynamic power down.

1 EN_DYN_PD_TEMP_SEN

S R/W 0h Enable dynamic power down of temperature sensor. 0: Disable dynamic power down | 1: Enable dynamic power down. 0 EN_DYN_PD_REFSYS R/W 0h Enable dynamic power down of reference. 0: Disable dynamic power down | 1: Enable dynamic power down.

7.5.1.1.94 Register 78h (Address = 78h) [reset = 0h]

Figure 122. Register 78h Table 124. Register 78 Field Descriptions 23 RESERVED R/W 0h Always read or write 0h.

22 SEL_GP3_ON_SDAM R/W 0h

power the signal on this pin are inverted (active low). 21:17 RESERVED R/W 0h Always read or write 0h. 16 GPIO2_IBUF_EN R/W 0h Enable input buffer on GP2 pin. Used for reference CLK input. 0: Disable input buffer | 1: Enable input buffer. 15 GPIO2_OBUF_EN R/W 0h Enable output buffer on GP2 pin. 0: Disable output buffer | 1: Enable output buffer. 14:13 RESERVED R/W 0h Always read or write 0h. 12 GPIO1_OBUF_EN R/W 0h Enable output buffer on GP1 pin. 0: Disable output buffer | 1: Enable output buffer. Select signal for the GP2 output multiplexer. Select signal for the GP1 output multiplexer. 5:3 RESERVED R/W 0h Always read or write 0h. Select signal for the GP3 output multiplexer.

7.5.1.1.95 Register 79h (Address = 79h) [reset = 1h]

Figure 123. Register 79h

Table 125. Register 79 Field Descriptions 23:20 RESERVED R/W 0h Always read or write 0. 19 PDN_ILLUM_DRV R/W 0h Test-mode bit to power down the illumination driver. 0: Illumination driver is active | 1: Illumination driver is powered down. 18:14 RESERVED R/W 0h Always read or write 0.

12 PDN_ILLUM_DC_CURR R/W 0h

Power down the dc bias current through the TX pins. 7:5 RESERVED R/W 0h Always read or write 0. 4 EN_TX_DC_CURR_ALL R/W 0h Enable dc current of all TX channels when TX0 is selected.

3 SEL_ILLUM_TX0_ON_TX1 R/W 0h

2 EN_TX_CLKZ R/W 0h

Enable inverted modulation CLK. 1 RESERVED R/W 0h Always read or write 0. 0 EN_TX_CLKB R/W 1h Enable modulation CLK. 0: Modulation clock is disabled | 1: Modulation clock is enabled.

7.5.1.1.96 Register 7Ah (Address = 7Ah) [reset = 0h]

Figure 124. Register 7Ah Table 126. Register 7A Field Descriptions 23:6 RESERVED R/W 0h Always read or write 0.

7.5.1.1.97 Register 80h (Address = 80h) [reset = 4E1Eh]

Figure 125. Register 80h

Table 127. Register 80 Field Descriptions

23 DIS_TG_ACONF R/W 0h

above mentioned TG signal registers. 22:17 RESERVED R/W 0h Always read or write 0h. 16:1 SUB_VD_CLK_CNT R/W 270Fh The number of TG clocks in a sub-frame. 0 TG_EN R/W 0h Enable the timing generation unit. 0: TG is disabled | 1: TG is enabled.

7.5.1.1.98 Register 83h (Address = 83h) [reset = D0h]

Figure 126. Register 83h Table 128. Register 83 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. in the number of TG CLKs (tCLK) in a sub-frame.

7.5.1.1.99 Register 84h (Address = 84h) [reset = D8h]

Figure 127. Register 84h

Table 129. Register 84 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. signal in the number of TG clocks (tCLK) in a sub-frame.

7.5.1.1.100 Register 85h (Address = 85h) [reset = 20h]

Figure 128. Register 85h Table 130. Register 85 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. clocks (tCLK) in a sub-frame.

7.5.1.1.101 Register 86h (Address = 86h) [reset = 28h]

Figure 129. Register 86h Table 131. Register 86 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. clocks (tCLK) in a sub-frame.

7.5.1.1.102 Register 87h (Address = 87h) [reset = 2454h]

Figure 130. Register 87h

Table 132. Register 87 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. clocks (tCLK) in a sub-frame.

7.5.1.1.103 Register 88h (Address = 88h) [reset = 2648h]

Figure 131. Register 88h Table 133. Register 88 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. clocks (tCLK) in a sub-frame.

7.5.1.1.104 Register 89h (Address = 89h) [reset = 3E8h]

Figure 132. Register 89h Table 134. Register 89 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. number of TG clocks (tCLK) in a sub-frame.

7.5.1.1.105 Register 8Ah (Address = 8Ah) [reset = 1F40h]

Figure 133. Register 8Ah Table 135. Register 8A Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. number of TG clocks (tCLK) in a sub-frame.

7.5.1.1.106 Register 8Fh (Address = 8Fh) [reset = 0h]

Figure 134. Register 8Fh Table 136. Register 8F Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. clocks (tCLK) in a sub-frame.

7.5.1.1.107 Register 90h (Address = 90h) [reset = 2134h]

Figure 135. Register 90h

Table 137. Register 90 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. clocks (tCLK) in a sub-frame.

7.5.1.1.108 Register 91h (Address = 91h) [reset = 2134h]

Figure 136. Register 91h Table 138. Register 91 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.109 Register 92h (Address = 92h) [reset = 2EE0h]

Figure 137. Register 92h Table 139. Register 92 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h.

7.5.1.1.110 Register 93h (Address = 93h) [reset = 0h]

Figure 138. Register 93h

Table 140. Register 93 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. clocks (tCLK) in a sub-frame.

7.5.1.1.111 Register 94h (Address = 94h) [reset = FFFFh]

Figure 139. Register 94h Table 141. Register 94 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. clocks (tCLK) in a sub-frame.

7.5.1.1.112 Register 97h (Address = 97h) [reset = 0h]

Figure 140. Register 97h Table 142. Register 97 Field Descriptions

7.5.1.1.113 Register 98h (Address = 98h) [reset = 0h]

Figure 141. Register 98h Table 143. Register 98 Field Descriptions NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1. exists between the START and END sub-frames.

7.5.1.1.114 Register 99h (Address = 99h) [reset = 1h]

Figure 142. Register 99h Table 144. Register 99 Field Descriptions NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.

7.5.1.1.115 Register 9Ch (Address = 9Ch) [reset = FFF000h]

Figure 143. Register 9Ch

Table 145. Register 9C Field Descriptions NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.

7.5.1.1.116 Register 9Dh (Address = 9Dh) [reset = 0h]

Figure 144. Register 9Dh Table 146. Register 9D Field Descriptions NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.

7.5.1.1.117 Register 9Eh (Address = 9Eh) [reset = 0h]

Figure 145. Register 9Eh Table 147. Register 9E Field Descriptions NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.

Table 147. Register 9E Field Descriptions (continued) TG_DYNPDN_MASK_START and TG_DYNPDN_MASK_END sub-frames.

7.5.1.1.118 Register 9Fh (Address = 9Fh) [reset = 0h]

Figure 146. Register 9Fh Table 148. Register 9F Field Descriptions 23:12 NUM_AVG_SUB_FRAMES R/W 0h Specifies the number of sub-frames to be averaged in a frame. Averaging sub-frames = NUM_AVG_SUB_FRAMES + 1. Number of sub-frames in a frame = NUM_SUB_FRAMES + 1. This number must be equal to or greater than NUM_AVG_SUB_FRAMES.

7.5.1.1.119 Register A0h (Address = A0h) [reset = 2198h]

Figure 147. Register A0h Table 149. Register A0 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. 15:0 CAPTURE_CLK_CNT R/W 2198h Internal data capture position (number of TG clocks, tCLK) in a sub-frame.

7.5.1.1.120 Register A2h (Address = A2h) [reset = 0h]

Figure 148. Register A2h Table 150. Register A2 Field Descriptions TX1 illumination channel with current of ILLUM_DAC_L_TX1. channel with current of ILLUM_DAC_H_TX0.

7.5.1.1.121 Register A3h (Address = A3h) [reset = 0h]

Figure 149. Register A3h Table 151. Register A3 Field Descriptions illumination channel with current of ILLUM_DAC_L_TX1. channel with current of ILLUM_DAC_L_TX1.

7.5.1.1.122 Register A4h (Address = A4h) [reset = 0h]

Figure 150. Register A4h

Table 152. Register A4 Field Descriptions TX1 illumination channel with current of ILLUM_DAC_H_TX1. channel with current of ILLUM_DAC_H_TX1.

7.5.1.1.123 Register A5h (Address = A5h) [reset = 0h]

Figure 151. Register A5h Table 153. Register A5 Field Descriptions illumination channel with current of ILLUM_DAC_H_TX1. channel with current of ILLUM_DAC_L_TX2.

7.5.1.1.124 Register A6h (Address = A6h) [reset = 0h]

Figure 152. Register A6h Table 154. Register A6 Field Descriptions TX2 illumination channel with current of ILLUM_DAC_L_TX2. channel with current of ILLUM_DAC_H_TX2.

7.5.1.1.125 Register A7h (Address = A7h) [reset = 0h]

Figure 153. Register A7h Table 155. Register A7 Field Descriptions illumination channel with current of ILLUM_DAC_L_TX2. illumination channel with current of ILLUM_DAC_H_TX0.

7.5.1.1.126 Register A8h (Address = A8h) [reset = 0h]

Figure 154. Register A8h Table 156. Register A8 Field Descriptions TX2 illumination channel with current of ILLUM_DAC_H_TX2. illumination channel with current of ILLUM_DAC_L_TX1.

7.5.1.1.127 Register A9h (Address = A9h) [reset = 0h]

Figure 155. Register A9h

Table 157. Register A9 Field Descriptions illumination channel with current of ILLUM_DAC_H_TX2. illumination channel with current of ILLUM_DAC_H_TX1.

7.5.1.1.128 Register AAh (Address = AAh) [reset = 0h]

Figure 156. Register AAh Table 158. Register AA Field Descriptions TX0 illumination channel with current of ILLUM_DAC_H_TX0. illumination channel with current of ILLUM_DAC_L_TX2.

7.5.1.1.129 Register ABh (Address = ABh) [reset = 0h]

Figure 157. Register ABh Table 159. Register AB Field Descriptions TX0 illumination channel with current of ILLUM_DAC_H_TX0. illumination channel with current of ILLUM_DAC_H_TX2.

7.5.1.1.130 Register ACh (Address = ACh) [reset = 0h]

Figure 158. Register ACh Table 160. Register AC Field Descriptions TX1 illumination channel with current of ILLUM_DAC_L_TX1. illumination channel with current of ILLUM_DAC_H_TX0.

7.5.1.1.131 Register ADh (Address = ADh) [reset = 0h]

Figure 159. Register ADh Table 161. Register AD Field Descriptions TX1 illumination channel with current of ILLUM_DAC_L_TX1. illumination channel with current of ILLUM_DAC_L_TX1.

7.5.1.1.132 Register AEh (Address = AEh) [reset = 0h]

Figure 160. Register AEh

Table 162. Register AE Field Descriptions TX1 illumination channel with current of ILLUM_DAC_H_TX1. illumination channel with current of ILLUM_DAC_H_TX1.

7.5.1.1.133 Register AFh (Address = AFh) [reset = 0h]

Figure 161. Register AFh Table 163. Register AF Field Descriptions TX1 illumination channel with current of ILLUM_DAC_H_TX1. illumination channel with current of ILLUM_DAC_L_TX2.

7.5.1.1.134 Register B0h (Address = B0h) [reset = 0h]

Figure 162. Register B0h Table 164. Register B0 Field Descriptions TX2 illumination channel with current of ILLUM_DAC_L_TX2. illumination channel with current of ILLUM_DAC_H_TX2.

7.5.1.1.135 Register B1h (Address = B1h) [reset = 0h]

Figure 163. Register B1h Table 165. Register B1 Field Descriptions for TX2 illumination channel with current of ILLUM_DAC_L_TX2. illumination channel with current of ILLUM_DAC_H_TX0.

7.5.1.1.136 Register B2h (Address = B2h) [reset = 0h]

Figure 164. Register B2h Table 166. Register B2 Field Descriptions 23:16 RESERVED R/W 0h Always read or write 0h. illumination channel with current of ILLUM_DAC_H_TX2.

7.5.1.1.137 Register B4h (Address = B4h) [reset = 0h]

Figure 165. Register B4h

Table 167. Register B4 Field Descriptions _COEFF3 R/W 0h Coefficient 3 for PWL phase correction with ambient. _COEFF2 R/W 0h Coefficient 2 for PWL phase correction with ambient. _COEFF1 R/W 0h Coefficient 1 for PWL phase correction with ambient.

7.5.1.1.138 Register B5h (Address = B5h) [reset = 0h]

Figure 166. Register B5h Table 168. Register B5 Field Descriptions 23:3 RESERVED R/W 0h Always read or write 0h. RR_COEFF R/W 0h Scaling factor for ambient-based PWL phase correction.

7.5.1.1.139 Register B8h (Address = B8h) [reset = 7FDFFh]

Figure 167. Register B8h Table 169. Register B8 Field Descriptions 23:21 RESERVED R/W 0h Always read or write 0h.

20 GIVE_DEALIAS_DATA R/W 0h When this register is set to 1, de-aliased phase is given out on

_X1 R/W 1FFh Second knee point of PWL phase correction with ambient. _X0 R/W 1FFh First knee point of PWL phase correction with ambient.

7.5.1.1.140 Register B8h (Address = B9h) [reset = 1FFh]

Figure 168. Register B9h Table 170. Register B9 Field Descriptions 17:16 AMB_ADC_IN_TX2 R/W 0h Select ambient ADC input when TX2 channel is selected. 15:14 AMB_ADC_IN_TX1 R/W 0h Select ambient ADC input when TX1 channel is selected. 13:12 AMB_ADC_IN_TX0 R/W 0h Select ambient ADC input when TX0 channel is selected.

11 EN_TX2_ON_TX0 R/W 0h If this bit is 1 when TX2 is selected, the illumination driver current flows

10 EN_TX1_ON_TX0 R/W 0h If this bit is 1 when TX1 is selected, the illumination driver current flows

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

non-HDR mode and 2000 sps in auto HDR mode.

8.2 Typical Application

sections. Figure 169 shows the interface between the OPT3101 device and an external MCU. Figure 169. Typical Application Block Diagram

8.2.1 Design Requirements

Table 171 lists the application requirements for obstacle avoidance system. Table 171. Application Specifications Distance accuracy 2 % For an object with 18% reflectivity. Wavelength 850 nm Infrared wavelength for illumination.

8.2.2 Detailed Design Procedure

8.2.2.1 Sample Rate

NUM_SUB_FRAME = 127 and NUM_AVG_SUB_FRAMES = 127, which gives a sample rate of 31.25 sps.

8.2.2.2 Photodiode and LED

• With a daylight filter, which has a very broad spectrum; example: SFH213
• Narrow-band IR spectrum; example: SFH213FA. A photiode with a narrow-band IR filter should be selected as it collects a lower ambient signal. Photodiode SFH213FA meets these requirements. This photodiode has a capacitance of 5.8 pF at 1-V reverse bias, which is within the supported capacitance range of the AFE. Photodiode characterisitcs are shown in Figure 171 and Figure 172

Figure 170. SFH4550 LED Radiation Characteristics Figure 171. SFH213FA Photodiode Directional Figure 172. SFH213FA Photodiode Reverse Bias

8.2.2.3 Ambient Support

• PAMB = Total ambient light power in the photodiode spectral bandwidth in W/m2
• Ascene = Area covered by photodiode FoV
• Ωlens = Solid angle from a point on target object to the photodiode lens
• Ωsemi-sphere= 2π (9) where
• φPD = Photodiode half-angle = 10° for SFH213FA (10)

Figure 173. SFH213FA Photodiode Spectral Response and Sunlight Power Within Photodiode Spectral Table 172. Photodiode Specifications specified half angle of ±10 degrees. Reverse bias capacitance at VR = 1 V 5.8 pF AFE supports a maximum capacitance of 6 pF.

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8.2.2.4 Distance Accuracy

For 30 sps operation, 128 sub-frames can be averaged to improve the noise performance by setting NUM_SUB_FRAMES = 127 and NUM_AVG_SUB_FRAMES = 127. AFE noise with a 6-pF photodiode capacitance and 100-µA ambient current support can be extracted from Figure 2 as 2.25 pA/√Hz. Total noise at 31.25 sps operation with the above settings is 12.6 pA. The minimum SNR required to meet the distance accuracy of 2%, (10 cm at 5 m) can be calculated using Equation 6 as 23.8. So the minimum signal current required is 12.6 pA × 23.8 = 300 pA. The photodiode current required to get a signal current of 300pA can be calculated from Equation 11 as 720 pA. With a diode responsivity of 0.5 A/W, the optical power required is 720 pA / (0.5 A/W) = 1.44 nW. Illumination power required with an 18% reflective target can be calculated from Equation 12 as 64 mW. The SFH4550 produces 70 mW of optical power for a current of 100 mA. From this, the required illumination current can be calculated as 91.5 mA where

• IPD = Photodiode signal current.
• ISIG_AFE = Signal current entering the AFE.
• CPD = Photodiode capacitance at a reverse bias voltage of 1 V (11) where
• Pr,sig = Signal power received by the photodiode
• PLED = LED output power
• R = Object reflectivity
• Ωlens = Solid angle from a point on a target object to the photodiode lens
• Ωsemi-sphere= 2π (12) where
• Dlens = Diameter of the lens over the photodiode = 5 mm for SFH213FA
• d = Object distance (13) Choose 100 mA as the illumination current for meeting the SNR requirement for the 18% reflective target at a 5- m distance. With this illumination current, a 90% reflective object gives a signal current of 1.5 nA for an object at 5 m, and the AFE saturates for an object at a distance of 5 m / √(200 nA / 1.5nA) = 0.43 m. Because the required minimum distance is lower than this, on-chip adaptive HDR should be used by setting ENABLE_ADAPTIVE_HDR = 1, ILLUM_DAC_L_TX0 = 2 and ILLUM_DAC_H_TX0 = 20. HDR switching thresholds can be set at HDR_THR_HIGH = 27 000 and HDR_THR_LOW = 27 000 / 10 / 1.2 = 2250.

8.2.2.5 Supply Voltage

Because the system must operate with a single supply, the OPT3101 device can be used in LDO mode, where the required 1.8-V supplies AVDD and DVDD are generated by the device itself using an internal LDO. To operate in this mode, connect the REG_MODE pin to the IOVDD supply (3.3 V).

8.2.3 Application Curves

Figure 174 and Figure 175 shows simulated received signal and distance standard deviation with object distance

Figure 174. Received Signal vs Object Distance Figure 175. Distance Standard Deviation vs Object

8.3 Initialization Set Up

After device power up, apply device reset by applying an active-low pulse of duration > 30 µs. Write the following registers to set the device running in required condition.

• Write the NUM_SUB_FRAMES and NUM_AVG_SUB_FRAMES registers to set the device to operate at the required sample rate.
• Select the maximum ambient current to be supported by writing IAMB_MAX_SEL.
• Enable adaptive HDR mode if required: EN_ADAPTIVE_HDR.
• Write illumination DAC currents ILLUM_DAC_L_TX0 and ILLUM_DAC_H_TX0.
• Program the adaptive HDR thresholds: HDR_THR_LOW and HDR_THR_HIGH.
• Load all the calibration settings: illumination crosstalk, phase offset, phase temperature coefficient, and phase ambient coefficient.
• Enable frequency calibration if an external reference CLK is connected to GP2: EN_AUTO_FREQ_COUNT = 1, EN_FLOOP = 1, EN_FREQ_CORR = 1, SYS_CLK_DIVIDER = round(log2(40×106 / fEXT)), REF_COUNT_LIMIT = 214 × (40×106 / 2SYS_CLK_DIV) / fEXT, EN_CONT_FCALIB = 1
• Enable on-chip temperature conversion: EN_TEMP_CONV = 1
• Write I2C host settings to read the external temperature sensor if it is present in the system. Register settings are listed in Table 26.
• Enable the timing generator by setting TG_EN = 1
• Perform internal crosstalk correction by making INT_XTALK_CALIB = 1, followed by INT_XTALK_CALIB = 0.

9 Power Supply Recommendations

switching to the AFE results in a crosstalk signal which affects the performance of the distance measurement. the supplies and decoupling capacitors with low impedance at fMOD on the supplies very close to the device. systems where the sample rate is very low that are kept in the power-down state most of the time. Figure 176. Power Supply Network in a System With External 1.8-V Regulator REG_MODE pin of the OPT3101 device should be connected to IOVDD in this mode.

Figure 177. Power Supply Network With On-Chip 1.8-V Regulator

10 Layout

10.1 Layout Guidelines

Figure 178. AFE Interface With Photodiode and LED

10.2 Layout Example

following guidelines should be followed to keep the crosstalk between transmitter and receiver low.

• Use a four-layer board, so that all the analog and digital supplies can be well isolated from each other.
• Place the photodiode and LED oriented orthogonal to each other .

Figure 181. Photodiode and LED Placement on PCB

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• OPT3101 Distance Sensor System Calibration
• Introduction to Time-of-Flight Optical Proximity Sensor System Design
• OPT3101 Evaluation Module User's Guide

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most- current data available for the designated device. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

www.ti.com 18-Aug-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) OPT3101RHFR Active Production VQFN (RHF) | 28 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 85 OPT 3101 OPT3101RHFR.A Active Production VQFN (RHF) | 28 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 85 OPT 3101 OPT3101RHFRG4 Active Production VQFN (RHF) | 28 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 OPT 3101 OPT3101RHFRG4.A Active Production VQFN (RHF) | 28 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 OPT 3101 OPT3101RHFT Obsolete Production VQFN (RHF) | 28 - - Call TI Call TI -40 to 85 OPT 3101 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 18-Aug-2026 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPT3101RHFR VQFN RHF 28 3000 367.0 367.0 35.0 OPT3101RHFRG4 VQFN RHF 28 3000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 28X 0.30 0.18 2.55 0.1 28X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.0024X 0.5 3.5 2X 2.5 3.55 0.1 A 4.1 3.9 B 5.1 4.9 0.30 0.18 0.5 0.3 VQFN - 1.0 mm max heightRHF0028A PLASTIC QUAD FLATPACK - NO LEAD 4220383/A 11/2016 PIN 1 INDEX AREA 0.08 C SEATING PLANE 8 15 9 14 28 23 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

29 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

28X (0.24) 28X (0.6) ( 0.2) TYP VIA 24X (0.5) (4.8) (3.8) (1.525) (2.55) (R0.05) TYP (1.025) (3.55) VQFN - 1.0 mm max heightRHF0028A PLASTIC QUAD FLATPACK - NO LEAD 4220383/A 11/2016 SYMM 9 14 2328 SYMM LAND PATTERN EXAMPLE SCALE:18X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 28X (0.6) 28X (0.24) 24X (0.5) (3.8) (4.8) 4X (1.13) (0.865) TYP (0.665) TYP (R0.05) TYP 4X (1.53) VQFN - 1.0 mm max heightRHF0028A PLASTIC QUAD FLATPACK - NO LEAD 4220383/A 11/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 29 76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 9 14 2328

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