SI8513-C-IS ETC2 | Alldatasheet
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The Si85xx products are unidirectional ac current sensors available in full-scale ranges of 5, 10, and 20 A. Si85xx produc ts are ideal upgrades for older current- sensing technologies offering size, performance, and cost advantages over current transformers, Hall effect devices, DCR circuits, and other approaches. The Si85xx are extremely low-loss, adding less than 1.3 m of series resistance and less than 2 nH series inductance in the sensing path at 25 °C. Current-sensing terminals are isolated from the other package pins, providing up to 5 kV RMS isolation level per safety approval ratings. Safety Approval (20-Pin SOIC Only) Functional Block Diagram Single-chip ac current sensor Low loss: <1.3 m primary series resistance and <2 nH inductance Leading-edge noise suppression eliminates need for leading-edge blanking "Ping-Pong" output version allows one Si85xx to replace two current transformers in full-bridge designs 5, 10, and 20 A full-scale versions ±5% initial accuracy 50 kHz to 1 MHz input frequency range FAULT output to safeguard operation Large 2 VPP min output at full scale High-side or low-side current sensing Compact 4x4x1 mm QFN package (1 kV RMS isolation) 20-pin wide-body SOIC (5 kV RMS isolation) –40 to 125 °C operating range UL/VDE/CSA approval Power supplies Motor controls Lighting equipment Industrial equipment UL 1577 recognized 5000 VRMS for 1 minute CSA component notice 5A approval IEC 60950, 61010, 60601 approved VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2) Typical Application VDD VOUT IIN IOUT L C PH1 PH2 OUT VDD1 GND2 VIN Si850x TRST Si851x METAL SLUG VDD TRST/FAULTIOUT IIN GND INTEGRATOR SIGNAL CONDITIONING ADC AUTO CALIBRATION LOGIC TEMP SENSOR OUT1 OUT2 MODE LOGIC MODE R1 R2 R3 R4 RESET LOGIC GND1 Patents pending Ordering Information: See page 26. Pin Assignments: See page 24 VDD MODE OUT1 OUT2 TRST/FAULT GND IIN IIN IIN IIN IIN IOUT IOUT IOUT IOUT IOUT Si851x 20-Pin SOIC 12-Pin QFN Si851x OUT1 OUT2 TRST/FAULT GND IOUT IIN MODE VDD
2 Preliminary Rev. 0.4
Preliminary Rev. 0.4 3 TABLE OF C ONTENTS Section Page
- Electrical Specifications
Table 1. Electrical Specifications
- Guaranteed by design and/or characterization.
- Maximum output load is not recommended to exceed 200 pF and 5 k.
- Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.
- See "2.4. Total Measurement Error" on page 11 for more information.
Table 2. Regulatory Information1 (SOIC-20 Only) The Si85xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. The Si85xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. The Si85xx is certified under UL1577 component recognition program. For more details, see File E257455. Table 1. Electrical Specifications (Continued)
- Guaranteed by design and/or characterization.
- Maximum output load is not recommended to exceed 200 pF and 5 k.
- Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.
- See "2.4. Total Measurement Error" on page 11 for more information.
Table 3. Insulation and Safety-Related Specifications
- To determine resistance and capacitance, the Si85xx is converted into a 2-terminal device. Pins 1–10 are shorted
then measured between these two terminals.
- Measured from input pin to ground.
Table 4. IEC 60664-1 (VDE 0884 Part 2) Ratings
Table 5. IEC 60747-5-2 Insulation Characteristics*
2652 V peak
compliant, certified, and factory-inspected to IEC60950. Table 6. IEC Safety Limiting Values1
- Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 1.
- The Si85xx is tested with VDD = 5.5 V, TJ =1 5 0º C , CL = 15 pF, and with an input current from IIN to IOUT equal to
20 Amps at 500 kHz (duty cycle = 50%).
Figure 1. SOIC-20 Thermal Derating Curve, Dependence of Safety Limiting Values Table 7. Thermal Characteristics Table 8. Absolute Maximum Ratings1
- Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
conditions for extended periods may affect device reliability.
- Refer to “AN329: Extending the Full-Scale Range of the Si85xx” for more information.
external reset timing is in error. Figure 4. Si85xx Startup and Control Timing
Table 11. It is typically used in applications where the R below the specified value in "1. than 150 ns (RTRST < 15 k) should not be used. Figure 5. Programming Reset Time (tR) can be improved by up to 2%. See Figure 6 for details. will result in a larger offset error than operating at 50 °C. measurement error can be expected. Table 9. Typical Reset Time vs. RTRST
2.2 M 20 µs
Table 10. Total Measurement Error Contributors
preferably, to a low-noise analog ground plane. MUST be tied to the VDD system power supply. Figures 9 and 10) should be implemented in the layout. 10 mA current-carrying capabilities should be used. of the inner layers or even the back side of the board. provide high isolation voltage. Figure 9. SOIC Layout Requirements Figure 10. QFN Layout Requirements
5 V VDD Trace
Preliminary Rev. 0.4 15 3.3.2. Selecting Reset Timing Signals Reset timing signals should be chosen to meet the following conditions: Satisfy reset time tR Not overlap integrator reset into the desired measurement period Not violate reset watchdog timeout period tWD 3.3.3. Configuring Integrator Reset Per Section “2. Functional Overview”, the integrator must be reset (zeroed) prior to the start of each measurement cycle to achieve specified measurement accuracy. This reset must be synchronized with the system switch timing signals to ensure that current is measured during the appropriate time; so, the Si85xx integrator reset circuitry uses system timing as its reference. Timing signals connect to reset inputs R1 through R4 where built-in lo gic functions allow the user to choose the conditions that cause an integrator reset event. Important Note: reset inputs R1–R4 are rated to a maximum input voltage of VDD. External resistor dividers must be used when connecting driver output signals to R1–R4 that swing beyond VDD. As shown in Table 11, the Si850x integrator reset logic is a simple XOR gate where reset is maintained (or triggered, depending on use of the TRST input) when states of reset inputs R1 and R2 are not equal. Figure 14 shows the logic for the Si851x products, where any one of three reset logic functions can cause integrator reset. The output mode (Si851x) is determined by the states of the Mode and R4 inputs, as shown in Table 11.
Table 11. Si85xx Output and Reset Mode Summary
- Device is in reset when Reset State = 1.
- For Si850x devices, RESET = XOR [R1, R2].
pulse whenever the reset logic output transitions from low to high. Figure 14. Si851x Integrator Reset Logic
OUT is VDD–1.4 V. Figure 17 illustrates the head room limitation of the Si85xx versus supply. Figure 17. Headroom Limitation
In this example, the Si850x is configured to operate in a single-phase synchronous buck converter (Figure 18). This converter has a PWM frequency of 1 MHz and a maximum duty cycle of 80%. maximum duty cycle (RTRST =2 0k ). output swings beyond the device VDD range). Figure 18. Si850x Single-Phase Buck Converter
2 Vpp
frequency of this phase-shifted full-bridge is 150 kHz, and the maximum control phase overlap is 70%. Figure 19. Full-Bridge Converter not being sourced from VIN). The external driver delay ensures reset is complete prior to the start of measurement.
require the selection of a lower tR value by connecting a resistor from TRST to ground. Figure 20. Push-Pull Example Using Default tR Value
24 Preliminary Rev. 0.4 4. Pin Descriptions—12-Pin QFN Figure 21. Example Pin Configurations Table 12. Si85xx Family Pin Descriptions
1 R1 Integrator reset input 1 R1 Integrator reset input 1
2 R2 Integrator reset input 2 R2 Integrator reset input 2
3 GND2 Ground R3 Integrator reset input 3
4 GND3 R4 Integrator reset input 4
5 OUT Output OUT1 Output in single-ended output mode, or
one of two outputs in Ping-Pong mode.
6 NC No connect OUT2 Second of two Ping-Pong mode outputs
7 TRST Reset time control T RST Reset time control
8 GND1 Ground GND Ground
9 IOUT Current output terminal IOUT Current ou tput terminal
10 IIN Current input terminal IIN Current input terminal
11 VDD1 Power supply input VDD Power supply input
12 VDD2 MODE Mode control input
Preliminary Rev. 0.4 25 5. Pin Descriptions—20-Pin SOIC Figure 22. Example Pin Configurations Table 13. Si85xx Family Pin Descriptions
1 VDD1
2 VDD2 MODE Mode control input
3 R1 Integrator reset input 1 R1 Integrator reset input 1
4 R2 Integrator reset input 2 R2 Integrator reset input 2
5 GND2 Ground R3 Integrator reset input 3
6 GND3 R4 Integrator reset input 4
7 OUT Output OUT1 Output in single-ended output mode, or
one of two outputs in Ping-Pong mode.
8 NC No connect OUT2 Second of two Ping-Pong mode outputs
9 TRST Reset time control T RST Reset time control
10 GND1 Ground GND Ground
11–15 IOUT Current output termi nal IOUT Current ou tput terminal 16–20 IIN Current input terminal IIN Current input terminal VDD MODE OUT1 OUT2 TRST/FAULT GND IIN IIN IIN IIN IIN IOUT IOUT IOUT IOUT IOUT Si851x 20-Pin SOIC VDD1 VDD2 GND2 OUT NC TRST GND1 IIN IIN IIN IIN IIN IOUT IOUT IOUT IOUT IOUT Si850x 20-Pin SOIC GND3
26 Preliminary Rev. 0.4 6. Ordering Guide New OPNs Full Scale Current (A) Initial Accuracy %1 Temp Range Pin 7 Function Isolation Rating Output Mode Package2 Old Obsolete OPNs3 (Previously Specified with ±5% Accuracy and –40C to +85 °C) Old Obsolete OPNs3 (Previously Specified with ±20% Accuracy) Si8501-C-IM 5 5% –40 to 125 °C Integrator Reset Pro- gramming Time Input 1k VRMS Single QFN-12 Si8501-C-GM Si8504-C-IM Si8502-C-IM 10 Si8502-C-GM Si8505-C-IM Si8503-C-IM 20 Si8503-C-GM Si8506-C-IM Si8501-C-IS 5 5k VRMS SOIC-20 New package offeringSi8502-C-IS 10 Si8503-C-IS 20 Si8511-C-IM 5 1k VRMS Ping- Pong QFN-12 Si8511-C-GM Si8514-C-IM Si8512-C-IM 10 Si8512-C-GM Si8515-C-IM Si8513-C-IM 20 Si8513-C-GM Si8516-C-IM Si8511-C-IS 5 5k VRMS SOIC-20 New package offeringSi8512-C-IS 10 Si8513-C-IS 20 Si8517-C-IM 5 FAULT Output 1k VRMS QFN-12 Si8517-C-GM —Si8518-C-IM 10 Si8518-C-GM Si8519-C-IM 20 Si8519-C-GM Si8517-C-IS 5 5k VRMS SOIC-20 New Package OfferingSi8518-C-IS 10 Si8519-C-IS 20 Notes: 1. See "2.4. Total Measurement Error" on page 11 for more information. 2. All packages are RoHS-compliant. Moisture Sensitivity level is MSL3 with peak reflow temperature of 260 °C according to the JEDEC industry classification, and peak solder temperature. 3. Since the initial accuracy for all devices is now specified as ±5%, Si8504/5/6 and Si8514/15/16 OPNs have been replaced with Si8501/2/3 and Si8511/12/13 OPNs, respectively.
Table 16. 20-Pin Wide Body SOIC Package Diagram Dimensions
- All dimensions shown are in millimeters (mm) unless otherwise noted.
- Dimensioning and Tolerancing per ANSI Y14.5M-1994.
- This drawing conforms to JEDEC Outline MS-013, Variation AC.
- Recommended reflow profile per JEDEC J-STD-020C specification for small body,
Figure 27. QFN Top Marking Table 18. Top Marking Explanation
Figure 28. SOIC Top Marking Table 19. Top Marking Explanation year and work week of the mold date.
34 Preliminary Rev. 0.4 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Updated Table 1, “Electrical Specifications,” on page 4. Added 20-pin wide-body SOIC package option. Updated "6. Ordering Guide" on page 26. All devices are now specified to ±5% initial accuracy. All devices are now specified for operation over –40 to +125 °C temperature range. All ordering part numbers have been updated to reflect this (i.e. previous “-GM” and “-GS” part number suffixes have been replaced with “-IM” and “-IS” suffixes). Added sections “8. Recommended PCB Land Pattern (12-Pin QFN)” and “10. Recommended PCB Land Pattern (20-Pin SOIC)”. Revision 0.2 to Revision 0.21 Added reference to IEC61010, IEC60601 on page 1. Updated "6. Ordering Guide" on page 26. Added Top Marking sections. Revision 0.21 to Revision 0.3 Updated Table 2 on page 5. Production test voltage is > 6.0 kVRMS. Added “2.5. Effect of Switching Frequency on Accuracy” on page 11. Added Figure 6, “Full-Scale Output Accuracy vs. Frequency,” on page 11. Updated "3.2. Layout Requirements" on page 13. Added layout recommendations for QFN. Added Figure 10, “QFN Layout Requirements,” on page 13. Revision 0.3 to Revision 0.4 Updated Table 8 on page 8. Added junction temperature spec. Removed Figure 6, “Full-Scale Output Accuracy vs. Frequency,” on page 11. Updated Figures 9 and 10 on page 13. Updated Table 11 on page 16. Updated notes. Updated Top Marks. Added revision description.
Preliminary Rev. 0.4 35 NOTES:
36 Preliminary Rev. 0.4 CONTACT INFORMATION Silicon Laboratories Inc.
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Click to View Pricing, Inventory, Delivery & Lifecycle Information: Silicon Laboratories: Si8505-B-IM Si8512-B-GM Si8515-B-IM Si8503-B-GM Si8516-B-IM Si8504-B-IM Si8514-B-IM Si8502-B-GM Si8513-B-GM Si8511-B-GM Si8501-B-GM Si8506-B-IM Si8517-B-GM Si8518-B-GM Si8519-B-GM Si8501-C-GM Si8502-C-GM Si8503-C-GM Si8504-C-IM Si8505-C-IM Si8506-C-IM Si8511-C-GM Si8512-C-GM Si8513-C-GM Si8514-C-IM Si8515-C-IM Si8516-C-IM Si8517-C-GM Si8518-C-GM Si8519-C-GM Si85XX5KV-EVB OPENLPPOL- EVB Si8501-C-IM Si8502-C-IM Si8503-C-IM Si8501-C-IS Si8502-C-IS Si8503-C-IS Si8511-C-IM Si8512-C-IM Si8513-C-IM Si8511-C-IS Si8512-C-IS Si8513-C-IS Si8517-C-IM Si8518-C-IM Si8519-C-IM Si8517-C-IS Si8518- C-IS Si8519-C-IS SI85XX20AQFN-KIT