OPA132U/2K5G4

OPA132_04 BURR-BROWN | Alldatasheet

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FEATURES

G FET INPUT: IB = 50pA max G WIDE BANDWIDTH: 8MHz G HIGH SLEW RATE: 20V/µs G LOW NOISE: 8nV/√Hz (1kHz) G LOW DISTORTION: 0.00008% G HIGH OPEN-LOOP GAIN: 130dB (600 Ω load) G WIDE SUPPLY RANGE: ±2.5 to ±18V G LOW OFFSET VOLTAGE: 500 µV max G SINGLE, DUAL, AND QUAD VERSIONS Out D –In D +In D +In C –In C Out C Out A –In A +In A +In B –In B Out B OPA4132 14-Pin DIP SO-14 AD BC OPA132 OPA2132 OPA4132 Offset Trim Output NC Offset Trim –In +In OPA132 8-Pin DIP, SO-8 Out B –In B +In B Out A –In A +In A OPA2132 8-Pin DIP, SO-8 A B High-Speed FET-INPUT OPERATIONAL AMPLIFIERS

DESCRIPTION

The OPA132 series of FET-input op amps provides high- speed and excellent dc performance. The combination of high slew rate and wide bandwidth provide fast settling time. Single, dual, and quad versions have identical specifications for maximum design flexibility. High performance grades are available in the single and dual versions. All are ideal for general-purpose, audio, data acquisition and communica- tions applications, especially where high source impedance is encountered. OPA132 op amps are easy to use and free from phase inversion and overload problems often found in common FET-input op amps. Input cascode circuitry pro- vides excellent common-mode rejection and maintains low input bias current over its wide input voltage range. OPA132 series op amps are stable in unity gain and provide excellent dynamic behavior over a wide range of load conditions, including high load capacitance. Dual and quad versions feature completely independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or overloaded. Single and dual versions are available in 8-pin DIP and SO-8 surface-mount packages. Quad is available in 14-pin DIP and SO-14 surface-mount packages. All are specified for –40°C to +85°C operation. SBOS054A – JANUARY 1995 – REVISED JUNE 2004 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995-2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. O PA132 O PA2132 O PA132 O PA2132 O PA4132 O PA4132

OPA132, 2132, 41322 SBOS054Awww.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to ob- serve proper handling and installation procedures can cause damage. ESD damage can range from subtle performance deg- radation to complete device failure. Precision inte- grated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS NOTE: (1) Short-circuit to ground, one amplifier per package. For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. PACKAGE/ORDERING INFORMATION

OPA132, 2132, 4132 3 SBOS054A www.ti.com SPECIFICATIONS At TA = +25°C, VS = ±15V, unless otherwise noted. OPA132P, U OPA2132P, U OPA132PA, UA OPA2132PA, UA OPA4132PA, UA PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage ±0.25 ±0.5 ±0.5 ±2m V vs Temperature(1) Operating Temperature Range ±2 ±10 ✻✻ µV/°C vs Power Supply V S = ±2.5V to ±18V 5 15 ✻ 30 µV/V Channel Separation (dual and quad) R L = 2kΩ 0.2 ✻ µV/V INPUT BIAS CURRENT Input Bias Current(2) VCM = 0V +5 ±50 ✻✻ pA vs Temperature See Typical Curve ✻ Input Offset Current(2) VCM = 0V ±2 ±50 ✻✻ pA NOISE Input Voltage Noise Noise Density, f = 10Hz 23 ✻ nV/√Hz f = 100Hz 10 ✻ nV/√Hz f = 1kHz 8 ✻ nV/√Hz f = 10kHz 8 ✻ nV/√Hz Current Noise Density, f = 1kHz 3 ✻ fA/√Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range (V –)+2.5 ±13 (V+) –2.5 ✻✻ ✻ V Common-Mode Rejection V CM = –12.5V to +12.5V 96 100 86 94 dB INPUT IMPEDANCE Differential 1013 || 2 ✻ Ω || pF Common-Mode V CM = –12.5V to +12.5V 10 13 || 6 ✻ Ω || pF OPEN-LOOP GAIN Open-Loop Voltage Gain R L = 10kΩ, VO = –14.5V to +13.8V 110 120 104 ✻ dB R L = 2kΩ, VO = –13.8V to +13.5V 110 126 104 120 dB R L = 600Ω, VO = –12.8V to +12.5V 110 130 104 120 dB FREQUENCY RESPONSE Gain-Bandwidth Product 8 ✻ MHz Slew Rate ±20 ✻ V/µs Settling Time: 0.1% G = –1, 10V Step, CL = 100pF 0.7 ✻ µs 0.01% G = –1, 10V Step, CL = 100pF 1 ✻ µs Overload Recovery Time G = ±1 0.5 ✻ µs Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 3.5Vrms R L = 2kΩ 0.00008 ✻ % R L = 600Ω 0.00009 ✻ % OUTPUT Voltage Output, Positive R L = 10kΩ (V+)–1.2 (V+)–0.9 ✻✻ V Negative (V –)+0.5 (V–)+0.3 ✻✻ V Positive R L = 2kΩ (V+)–1.5 (V+)–1.2 ✻✻ V Negative (V –)+1.2 (V–)+0.9 ✻✻ V Positive R L = 600Ω (V+)–2.5 (V+)–2.0 ✻✻ V Negative (V –)+2.2 (V–)+1.9 ✻✻ V Short-Circuit Current ±40 ✻ mA Capacitive Load Drive (Stable Operation) See Typical Curve ✻ POWER SUPPLY Specified Operating Voltage ±15 ✻ V Operating Voltage Range ±2.5 ±18 ✻✻ V Quiescent Current (per amplifier) I O = 0 ±4 ±4.8 ✻✻ mA TEMPERATURE RANGE Operating Range –40 +85 ✻✻ °C Storage –40 +125 ✻✻ °C Thermal Resistance, θJA 8-Pin DIP 100 ✻ °C/W SO-8 Surface-Mount 150 ✻ °C/W 14-Pin DIP 80 ✻ °C/W SO-14 Surface-Mount 110 ✻ °C/W ✻ Specifications same as OPA132P, OPA132U. NOTES: (1) Guaranteed by wafer test. (2) High-speed test at TJ = 25°C.

OPA132, 2132, 41324 SBOS054Awww.ti.com TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, RL = 2kΩ , unless otherwise noted. OPEN-LOOP GAIN/PHASE vs FREQUENCY 0.1 1 10 100 1k 10k 100k 1M 10M 160 140 120 100 –20 –45 –90 –135 –180 Voltage Gain (dB) Phase Shift (°) Frequency (Hz) φ G INPUT BIAS CURRENT vs TEMPERATURE Ambient Temperature (°C) Input Bias Current (pA) 100k 10k 100 0.1 –75 –50 –25 0 25 50 75 100 125 Dual Quad Single High Speed Test Warmed Up INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY 100 Voltage Noise (nV/√Hz) Frequency (Hz) 10 100 1k 10k 100k 1M Current Noise (fA/√Hz) Voltage Noise Current Noise POWER SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY Frequency (Hz) PSR, CMR (dB) 120 100 10 100 1k 10k 100k 1M CMR –PSR +PSR CHANNEL SEPARATION vs FREQUENCY Frequency (Hz) Channel Separation (dB) 160 140 120 100 100 1k 10k 100k Dual and quad devices. G = 1, all channels. Quad measured channel A to D or B to C— other combinations yield improved rejection. R L = ∞ R L = 2kΩ INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE Common-Mode Voltage (V) Input Bias Current (pA) –15 –10 –50 51 0 1 5 High Speed Test

OPA132, 2132, 4132 5 SBOS054A www.ti.com TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VS = ±15V, RL = 2kΩ , unless otherwise noted. AOL , CMR, PSR vs TEMPERATURE Ambient Temperature (°C) AOL , CMR, PSR (dB) 130 120 110 100 –75 –50 –25 0 25 50 75 100 125 Open-Loop Gain PSR CMR OFFSET VOLTAGE PRODUCTION DISTRIBUTION Percent of Amplifiers (%) Offset Voltage (µV) –1400 –1200 –1000 –800 –600 –400 –200 200 400 600 800 1000 1200 1400 Typical production distribution of packaged units. Single, dual and quad units included. OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Percent of Amplifiers (%) Offset Voltage Drift (µV/°C) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 Typical production distribution of packaged units. Single, dual and quad units included. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY Frequency (Hz) THD+Noise (%) 0.01 0.001 0.0001 0.00001 10 100 1k 10k 100k 2kΩ 600Ω R L G = +10 G = +1 VO = 3.5Vrms QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE Ambient Temperature (°C) Quiescent Current Per Amp (mA) 4.3 4.2 4.1 4.0 3.9 3.8 Short-Circuit Current (mA) –75 –50 –25 0 25 50 75 100 125 ±ISC ±IQ MAXIMUM OUTPUT VOLTAGE vs FREQUENCY Frequency (Hz) 10k 100k 1M 10M Output Voltage (Vp-p) VS = ±15V VS = ±2.5V VS = ±5V Maximum output voltage without slew-rate induced distortion

OPA132, 2132, 41326 SBOS054Awww.ti.com FPO SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 100pF 1nF 10nF Load Capacitance Overshoot (%) G = +1 G = ±10 G = –1 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VS = ±15V, RL = 2kΩ , unless otherwise noted. SETTLING TIME vs CLOSED-LOOP GAIN Closed-Loop Gain (V/V) Settling Time (µs) 100 0.1 ±1 ±10 ±100 ±1000 0.01% 0.1% OUTPUT VOLTAGE SWING vs OUTPUT CURRENT –10 –11 –12 –13 –14 –15 0 1 02 03 04 05 06 0 Output Current (mA) Output Voltage Swing (V) –55°C –55°C 25°C25°C 85°C 85°C 125°C 125°C 25°C VIN = –15V VIN = 15V SMALL-SIGNAL STEP RESPONSE G = 1, CL = 100pF 200ns/div 50mV/div LARGE-SIGNAL STEP RESPONSE G = 1, CL = 100pF 1µs/div 5V/div

FIGURE 1. OPA132 Offset Voltage Trim Circuit. tion than the single, leading to higher junction temperature. ing the devices to the circuit board rather than using a socket. offset voltage of op amp— see text.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) OPA132P OBSOLETE PDIP P 8 TBD Call TI Call TI OPA132P1 OBSOLETE PDIP P 8 TBD Call TI Call TI OPA132PA OBSOLETE PDIP P 8 TBD Call TI Call TI OPA132PA2 OBSOLETE PDIP P 8 TBD Call TI Call TI OPA132U ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132U1 OBSOLETE PDIP P 8 TBD Call TI Call TI OPA132UA ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132UA2 OBSOLETE PDIP P 8 TBD Call TI Call TI OPA132UAE4 ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132UAG4 ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA132UG4 ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA2132P ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA2132PA ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA2132U ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2132U/2K5 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2132U/2K5E4 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2132UA ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA2132UA/2K5 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2132UA/2K5E4 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2132UAE4 ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2132UAG4 ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA2132UE4 ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR PACKAGE OPTION ADDENDUM www.ti.com 12-Feb-2007 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) OPA4132PA OBSOLETE PDIP N 14 TBD Call TI Call TI OPA4132UA ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA4132UA/2K5 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA4132UA/2K5E4 ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA4132UAE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 12-Feb-2007 Addendum-Page 2

MPDI001A – JANUARY 1995 – REVISED JUNE 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.015 (0,38) Gage Plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM MAX 0.430 (10,92) 4040082/D 05/98 0.200 (5,08) MAX 0.125 (3,18) MIN 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

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