OPA132U/2K5

OPA132 TI | Alldatasheet

Document overview

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Technical content

OPAx132 High-Speed FET-Input Operational Amplifiers

1 Features

• A newer version of this device is now available: OPA2156
• FET input: IB = 50pA Maximum
• Wide bandwidth: 8MHz
• High slew rate: 20V/µs
• Low noise: 8nV/√Hz (1kHz)
• Low distortion: 0.00008%
• High open-loop gain: 126dB (2kΩ load)
• Wide supply range: ±2.5V to ±18V
• Low offset voltage: 500µV maximum
• Single, dual, and quad versions

2 Applications

• SAR ADC driver
• Voltage reference buffer
• Trans-impedance amplifier
• Photodiode amplifier
• Active filter
• Integrator 100 Voltage Noise (nV/√Hz) Frequency (Hz) 10 100 1k 10k 100k 1M Current Noise (fA/√Hz) Voltage Noise Current Noise Low-Noise JFET Input

3 Description

The OPA132, OPA2132, and OPA4132 (OPAx132) series of FET-input operational amplifiers provides high speed and excellent dc performance. The combination of high slew rate and wide bandwidth provide fast settling time. The single, dual, and quad versions have identical specifications for maximum design flexibility. High-performance grades are available in the single and dual versions. All are an excellent choice for general- purpose, audio, data-acquisition, and communications applications, especially where high source impedance is encountered. The OPAx132 operational amplifiers are easy to use and free from phase inversion and overload problems often found in common FET-input operational amplifiers. Input cascode circuitry provides excellent common-mode rejection and maintains low input bias current over the wide input voltage range. The OPAx132 series of operational amplifiers are stable in unity gain and provide excellent dynamic behavior over a wide range of load conditions, including high load capacitance. Dual and quad versions feature completely independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or overloaded. The single version is available in 8-pin SOIC surface mount package, the dual version is available in 8-pin DIP and SOIC surface-mount packages. The quad version is available in SOIC surface-mount packages. All are specified for –40°C to +85°C operation. The OPA2156 is a next-generation version, offering lower broadband noise (3nV/ √Hz), wider bandwidth (25MHz), and rail-to-rail inputs. Device Information PART NUMBER CHANNEL COUNT PACKAGE(1) OPA132 Single D (SOIC, 8) OPA2132 Dual D (SOIC, 8) P (PDIP,8) OPA4132 Quad D (SOIC, 14) (1) For more information, see Section 10. OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

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4 Pin Configuration and Functions

2±IN 7 V+ 3+IN 6 OUT 4V± 5 NC Not to scale Figure 4-1. OPA132: D Package, 8-Pin SOIC (Top View) Pin Functions: OPA132 PIN TYPE DESCRIPTION NAME NO. +IN 3 Input Noninverting input –IN 2 Input Inverting input NC 1, 5 — Do not connect these pins(1) NC 8 — No internal connection. Float this pin. Output 6 Output Output V+ 7 Power Positive power supply V– 4 Power Negative power supply (1) Existing layouts for the OPA132 before revision C of this data sheet do not need to be redesigned. 1OUT A 8 V+ 2±IN A 7 OUT B 3+IN A 6 ±IN B 4V± 5 +IN B Not to scale Figure 4-2. OPA2132: D Package, 8-Pin SOIC, and P Package, 8-Pin PDIP (Top View) Table 4-1. Pin Functions: OPA2132 PIN TYPE DESCRIPTION NAME NO. +IN A 3 Input Noninverting input, channel A +IN B 5 Input Noninverting input, channel B –IN A 2 Input Inverting input, channel A –IN B 6 Input Inverting input, channel B OUT A 1 Output Output, channel A OUT B 7 Output Output, channel B V+ 8 Power Positive (highest) power supply V– 4 Power Negative (lowest) power supply www.ti.com OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: OPA132 OPA2132 OPA4132

2±IN A 13 ±IN D 3+IN A 12 +IN D 4V+ 11 V ± 5+IN B 10 +IN C 6±IN B 9 ±IN C 7OUT B 8 OUT C Not to scale Figure 4-3. OPA4132- D Package, 14-Pin SOIC (Top View) Table 4-2. Pin Functions: OPA4132 PIN TYPE DESCRIPTION NAME NO. +IN A 3 Input Noninverting input, channel A +IN B 5 Input Noninverting input, channel B +IN C 10 Input Noninverting input, channel C +IN D 12 Input Noninverting input, channel D –IN A 2 Input Inverting input, channel A –IN B 6 Input Inverting input, channel B –IN C 9 Input Inverting input, channel C –IN D 13 Input Inverting input, channel D OUT A 1 Output Output, channel A OUT B 7 Output Output, channel B OUT C 8 Output Output, channel C OUT D 14 Output Output, channel D V+ 4 Power Positive (highest) power supply V– 11 Power Negative (lowest) power supply OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VS Supply voltage, (V+) – (V–) 36 V Input voltage(2) (V–) – 0.5 (V+) + 0.5 V Input current(2) ±10 mA ISC Output short-circuit(3) Continuous TA Operating temperature –40 125 °C TJ Junction temperature 150 °C Tstg Storage temperature –55 125 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails must be current limited to 10mA or less. (3) Short-circuit to ground, one amplifier per package.

5.2 ESD Ratings

OPA132 in SOIC Package, OPA2132 in PDIP Package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V OPA2132 in SOIC Package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 OPA4132 V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±200 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VS Supply voltage, (V+) – (V–) Dual supply ±2.5 ±15 ±18 V Single supply 9 30 36 TA Ambient temperature –40 85 °C www.ti.com OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: OPA132 OPA2132 OPA4132

5.4 Thermal Information - OPA132

THERMAL METRIC(1) OPA132 UNITD (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance 160 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75 °C/W RθJB Junction-to-board thermal resistance 60 °C/W ΨJT Junction-to-top characterization parameter 9 °C/W ΨJB Junction-to-board characterization parameter 50 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Thermal Information - OPA2132

THERMAL METRIC(1) OPA2132 UNITD (SOIC) P (PDIP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 160 71 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75 50 °C/W RθJB Junction-to-board thermal resistance 60 36 °C/W ΨJT Junction-to-top characterization parameter 9 16 °C/W ΨJB Junction-to-board characterization parameter 50 35 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.6 Thermal Information - OPA4132

THERMAL METRIC(1) OPA4132 UNITD (SOIC)

14 PINS

RθJA Junction-to-ambient thermal resistance 97 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56 °C/W RθJB Junction-to-board thermal resistance 53 °C/W ΨJT Junction-to-top characterization parameter 19 °C/W ΨJB Junction-to-board characterization parameter 46 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

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5.7 Electrical Characteristics

at TA = 25°C, VS = ±15V, RL = 2kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage OPAx132U ±0.2 ±0.5 mV OPAx132UA ±0.5 ±2 dVOS/dT Input offset voltage drift TA = –40°C to +85°C ±2 ±10 μV/°C PSRR Power-supply rejection ratio ±2.5V ≤ VS ≤ ±18V OPAx132U ±5 ±15 μV/V OPAx132UA ±5 ±30 Channel separation (dual and quad) RL = 2kΩ 0.2 μV/V INPUT BIAS CURRENT IB Input bias current(1) ±5 ±50 pA TA = –40°C to +85°C See Typical Characteristics IOS Input offset current(1) ±2 ±50 pA NOISE en Input voltage noise density f = 10Hz 23 nV/√Hz f = 100Hz 10 f = 1kHz 8 f = 10kHz 8 In Input current noise density f = 1kHz 3 fA/√Hz INPUT VOLTAGE VCM Common-mode voltage (V–) + 2.5 ±13 (V+) – 3.5 V CMRR Common-mode rejection ratio –12.5V ≤ VCM ≤ 11.5V OPAx132U 96 100 dB OPAx132UA 86 94 INPUT IMPEDANCE Differential 1013 || 10 Ω || pF Common-mode –12.5V ≤ VCM ≤ 11.5V 1013 || 7 OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10kΩ, OPAx132U 110 120 dB OPAx132UA 104 120 RL = 2kΩ, OPAx132U 110 126 OPAx132UA 104 120 RL = 600Ω, OPAx132U 110 130 OPAx132UA 104 120 FREQUENCY RESPONSE GBW Gain bandwidth product 8 MHz SR Slew rate ±20 V/μs Settling time 10V step, G = 1, CL = 100pF 0.1% 0.7 μs 0.01% 1 THD+N Total harmonic distortion plus noise f = 1kHz, G = 1, VO = 3.5Vrms RL = 2kΩ 0.0008% RL = 600Ω 0.0009% Overload recovery time G = ±1 600 ns OUTPUT VO Voltage output RL = 10kΩ Positive (V+) – 1.2 (V+) – 0.9 V Negative (V–) + 0.3 (V–) + 0.5 RL = 2kΩ Positive (V+) – 1.5 (V+) – 1.1 Negative (V–) + 1.2 (V–) + 0.9 RL = 600Ω Positive (V+) – 2.5 (V+) – 2.0 Negative (V–) + 2.2 (V–) + 1.5 ISC Short-circuit current Sourcing 36 mA Sinking –30 mA Capacitive load drive (stable operation) See Typical Characteristics POWER SUPPLY IQ Quiescent current (per amplifier) IO = 0mA ±4 ±4.8 mA (1) High-speed test at TJ = 25°C. www.ti.com OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: OPA132 OPA2132 OPA4132

5.8 Typical Characteristics

at TA = 25°C, VS = ±15V, RL = 2kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 0.1 1 10 100 1k 10k 100k 1M 10M 160 140 120 100 –20 –45 –90 –135 –180 Voltage Gain (dB) Phase Shift (°) Frequency (Hz) Φ G Figure 5-1. Open-Loop Gain and Phase vs Frequency Frequency (Hz) PSR, CMR (dB) 120 100 10 100 1k 10k 100k 1M CMR –PSR +PSR Figure 5-2. Power Supply and Common-Mode Rejection vs Frequency 100 Voltage Noise (nV/√Hz) Frequency (Hz) 10 100 1k 10k 100k 1M Current Noise (fA/√Hz) Voltage Noise Current Noise Figure 5-3. Input Voltage vs Frequency Frequency (Hz) Channel Separation (dB) 160 140 120 100 100 1k 10k 100k Dual and quad devices. G = 1, all channels. Quad measured channel A to D or B to C—other combinations yield improved rejection. RL = ∞ RL = 2kΩ Figure 5-4. Channel Separation vs Frequency Ambient Temperature (°C) Input Bias Current (pA) 100k 10k 100 0.1 –75 –50 –25 0 25 50 75 100 125 Dual Quad Single High Speed Test Warmed Up Figure 5-5. Input Bias Current vs Temperature Common-Mode Voltage (V) Input Bias Current (pA) –15 –10 –5 0 5 10 15 High Speed Test Figure 5-6. Input Bias Current vs Input Common-Mode Voltage OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

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5.8 Typical Characteristics (continued)

at TA = 25°C, VS = ±15V, RL = 2kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) Ambient Temperature (°C) A OL , CMR, PSR (dB) 130 120 110 100 –75 –50 –25 0 25 50 75 100 125 Open-Loop Gain PSR CMR Figure 5-7. AOL, CMR, PSR vs Temperature Ambient Temperature (°C) Quiescent Current Per Amp (mA) 4.3 4.2 4.1 4.0 3.9 3.8 Short-Circuit Current (mA) –75 –50 –25 0 25 50 75 100 125 ±ISC ±IQ Figure 5-8. Quiescent Current and Short-Circuit Current vs Temperature Percent of Amplifiers (%) Offset Voltage (µV) – 1400 – 1200 – 1000– 800 – 600 – 400 – 200 200 400 600 800 1000 1200 1400 Typical production distribution of packaged units. Single, dual and quad units included. Figure 5-9. Offset Voltage Production Distribution Percent of Amplifiers (%) Offset Voltage Drift (µV/°C) Typical production distribution of packaged units. Single, dual and quad units included. Figure 5-10. Offset Voltage Drift Production Distribution Frequency (Hz) THD+Noise (%) 0.01 0.001 0.0001 0.00001 10 100 1k 10k 100k 2kΩ 600Ω RL G = +10 G = +1 VO = 3.5Vrms Figure 5-11. Total Harmonic Distortion + Noise vs Frequency Frequency (Hz) 10k 100k 1M 10M Output Voltage (Vp-p) VS = /c17715V VS = /c1772.5V VS = /c1775V Maximum output voltage without slew-rate induced distortion Figure 5-12. Maximum Output Voltage vs Frequency www.ti.com OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: OPA132 OPA2132 OPA4132

at TA = 25°C, VS = ±15V, RL = 2kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 200ns/div 50mV/div G = 1 CL = 100pF Figure 5-13. Small-Signal Step Response 1 s/divμ 5V/div G = 1 CL = 100pF Figure 5-14. Large-Signal Step Response FPO Closed-Loop Gain (V/V) Settling Time (µs) 100 0.1 ±1 ±10 ±100 ±1000 0.01% 0.1% Figure 5-15. Settling Time vs Closed-Loop Gain 4035302520151050Overshoot (%) 02004006008001000120014001600Capacitive Load (pF) R = 0OUTΩR = 24OUTΩR = 51OUTΩ +15V-15VROUTCLRL G = +1 Figure 5-16. Small-Signal Overshoot vs Load Capacitance 50454035302520151050Overshoot (%) 0500100015002000Capacitive Load (pF) R = 24OUTΩR = 51OUTΩ R = 0OUTΩ R = 2kIΩ ROUTCL R = 2kFΩ+15V-15V G = -1 G = +1 Figure 5-17. Small-Signal Overshoot vs Load Capacitance Output Voltage (V) 0 10 20 30 40 50 60 70 Output Current (mA) +85 C/c176 +25 C/c176 18.0 17.5 17.0 16.5 16.0 /c45 16.0 16.5 17.0 17.5 18.0 /c45 /c45 /c45 /c45 +125 C/c176 /c45 40 C/c176 G = –1 Figure 5-18. Output Voltage Swing vs Output Current OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

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6 Detailed Description

6.1 Overview

The OPAx132 series of FET-input operational amplifiers provides high speed and excellent dc performance. The combination of high slew rate and wide bandwidth provide fast settling time. Single, dual, and quad versions have identical specifications for maximum design flexibility. High performance grades are available in the single and dual versions. All devices are an excellent choice for general-purpose, audio, data acquisition and communications applications; especially, where high source impedance is encountered.

6.2 Functional Block Diagram

V OUT IN+ IN OPAx132 Compensation

6.3 Feature Description

The OPAx132 series of JFET operational amplifiers combine low noise and wide bandwidth with precision and low input bias current to make the these devices an excellent choice for applications with a high source impedance. The OPAx132 is unity-gain stable and features high slew rate (±20V/ μs) and wide bandwidth (8MHz).

6.4 Device Functional Modes

The OPAx132 has a single functional mode and is operational when the power-supply voltage is greater than 5V (±2.5V). The maximum power supply voltage for the OPAx132 is 36V (±18V). www.ti.com OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: OPA132 OPA2132 OPA4132

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

The OPAx132 series operational amplifiers are unity-gain stable and an excellent choice for a wide range of general-purpose applications. Bypass power-supply pins with 10nF ceramic capacitors or larger. The OPAx132 series operational amplifiers are free from unexpected output phase reversal common with FET operational amplifiers. Many FET-input operational amplifiers exhibit phase-reversal of the output when the input common-mode voltage range is exceeded. This phase reversal can occur in voltage-follower circuits, causing serious problems in control-loop applications. The OPAx132 series of operational amplifiers are free from this undesirable behavior. All circuitry is completely independent in dual and quad versions, maintaining normal behavior when one amplifier in a package is overdriven or short-circuited.

7.1.1 Operating Voltage

The OPAx132 series of operation amplifiers operate with power supplies from ±2.5V to ±18V with excellent performance. Although specifications are production tested with ±15V supplies, most behavior remains unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltage are shown in Section 5.8 .

7.1.2 Offset Voltage Trim

The offset voltage of the OPAx132 amplifiers is laser trimmed and usually requires no user adjustment. The OPAx132 provide less than ±500µV of input offset voltage and less than 10µV/°C of input offset voltage drift over the operating temperature range

7.1.3 Input Bias Current

The FET-inputs of the OPAx132 series provide very low input bias current and cause negligible errors in most applications. For applications where low input bias current is crucial, minimize junction temperature rise. The input bias current of FET-input operational amplifiers increases with temperature; see also Figure 5-5. The OPAx132 series can be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using ±3V supplies reduces power dissipation to one-fifth used at ±15V. The dual and quad versions have higher total power dissipation than the single version, leading to higher junction temperature. Thus, a warmed-up quad has higher input bias current than a warmed-up single. Furthermore, an SOIC generally has higher junction temperature than a DIP at the same ambient temperature because of a larger θJA. Printed-circuit-board (PCB) layout also helps minimize junction temperature rise. Minimize temperature rise by soldering the devices to the PCB rather than using a socket. Wide copper traces also help dissipate the heat by acting as an additional heat sink. Input stage cascode circuitry keeps the input bias current virtually unchanged throughout the full input common- mode range of the OPAx132 series. See also Figure 5-6. OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

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7.2 Typical Application

The OPAx132 family offers outstanding dc precision and ac performance. These devices operate up to 36V supply rails and offer ultra-low input bias current and input bias current noise, as well as 8MHz bandwidth and high capacitive load drive. These features make the OPAx132 a robust, high-performance operational amplifier for high-voltage industrial applications with high source impedance. OPAx132 Input Output 2.94k 1nF 39nF 590 499 Figure 7-1. OPA132 2nd Order 30kHz, Low Pass Filter Schematic

7.2.1 Design Requirements

Use the following parameters for this application:

• Gain = 5V/V
• Low-pass cutoff frequency = 30kHz
• –40db/dec filter response
• Maintain less than 3dB gain peaking in the gain versus frequency response

7.2.2 Detailed Design Procedure

WEBENCH® Circuit Designer creates customized power supply and active filter circuits based on your system requirements. The environment gives you end-to-end selection, design, and simulation capabilities that save you time during all phases of the analog design process. Use our tools to help with your designs:

• Filter design tool
• Powerstage designer
• WEBENCH® Power designer
• PCB thermal calculator

7.2.3 Application Curve

Frequency (Hz) Gain (db) -60 -40 -20 100 1k 10k 100k 1M Figure 7-2. OPA132 2nd-Order 30kHz, Low-Pass Filter Response www.ti.com OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: OPA132 OPA2132 OPA4132

7.3 Power Supply Recommendations

The OPAx132 is specified for operation from 5V to 36V (±2.5V to ±18V); many specifications apply from –40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Section 5.8. CAUTION Supply voltages larger than 36V can permanently damage the device; see Section 5.1 . Place 10nF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedance power supplies. For more detailed information on bypass capacitor placement, see Section 7.4.1 .

7.4 Layout

7.4.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier individually. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 10nF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information, see also Circuit Board Layout Techniques .
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RF and RG close to the inverting input minimizes parasitic capacitance; see also Section 7.4.2 .
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

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7.4.2 Layout Example

–IN +IN OUTPUT NC NC VS+ GND VS– GND Ground (GND) plane on another layer VOUT VIN GND Run the input traces as far away from the supply lines as possible Use low-ESR, ceramic bypass capacitor RF RG Place components close to device and to each other to reduce parasitic errors +VIN VOUTRG RF (Schematic Representation) Use low-ESR, ceramic bypass capacitor Figure 7-3. OPA132 Layout Example for the Noninverting Configuration www.ti.com OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: OPA132 OPA2132 OPA4132

8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

8.1.1.1 Analog Filter Designer

Available as a web-based tool from the Design and simulation tool web page, the Analog Filter Designer allows the user to design, optimize, and simulate complete multistage active filter solutions within minutes.

8.1.1.2 TINA-TI™ Simulation Software (Free Download)

TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software or TINA-TI software be installed. Download the free TINA-TI simulation software from the TINA-TI™ software folder.

8.1.1.3 TI Reference Designs

TI reference designs are analog solutions created by TI’s precision analog applications experts. TI reference designs offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI reference designs are available online at https://www.ti.com/reference-designs.

8.2 Documentation Support

8.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
• Texas Instruments, Circuit Board Layout Techniques

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.5 Trademarks

TINA-TI™ and TI E2E™ are trademarks of Texas Instruments. TINA™ is a trademark of DesignSoft, Inc. All trademarks are the property of their respective owners. OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

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Product Folder Links: OPA132 OPA2132 OPA4132

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2015) to Revision C (August 2024) Page

• Changed input voltage from (V–) – 0.7 and (V+) + 0.7 to (V–) – 0.5 and (V+) + 0.5 in Absolute Maximum
• Changed common-mode rejection ratio and common-mode input impedance test conditions from –12.5V ≤
• Deleted redundant power supply and temperature range sections already covered in Recommended
• Changed Figure 16, Small-Signal Overshoot vs Load Capacitance into two plots, Figure 5-16 for G = +1 and www.ti.com OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: OPA132 OPA2132 OPA4132

Changes from Revision A (June 2004) to Revision B (September 2015) Page

• Added ESD Ratings, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. OPA132, OPA2132, OPA4132 SBOS054C – JANUARY 1995 – REVISED AUGUST 2024 www.ti.com

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: OPA132 OPA2132 OPA4132

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) OPA132U Active Production SOIC (D) | 8 75 | TUBE Yes Call TI | Nipdau Level-3-260C-168 HR - OPA 132U OPA132U.B Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 125 OPA 132U OPA132U/2K5 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-3-260C-168 HR - OPA 132U OPA132U/2K5.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 125 OPA 132U OPA132UA Active Production SOIC (D) | 8 75 | TUBE Yes Call TI | Nipdau Level-3-260C-168 HR -40 to 125 OPA 132U A OPA132UA.B Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 125 OPA 132U A OPA132UA/2K5 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-3-260C-168 HR -40 to 125 OPA 132U A OPA132UA/2K5.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 125 OPA 132U A OPA2132P Active Production PDIP (P) | 8 50 | TUBE Yes Call TI N/A for Pkg Type - OPA2132P OPA2132P.A Active Production PDIP (P) | 8 50 | TUBE Yes Call TI N/A for Pkg Type -40 to 125 OPA2132P OPA2132PA Active Production PDIP (P) | 8 50 | TUBE Yes Call TI N/A for Pkg Type - OPA2132P A OPA2132PA.A Active Production PDIP (P) | 8 50 | TUBE Yes Call TI N/A for Pkg Type -40 to 125 OPA2132P A OPA2132PAG4 Active Production PDIP (P) | 8 50 | TUBE Yes Call TI N/A for Pkg Type See OPA2132PA OPA2132P A OPA2132U Active Production SOIC (D) | 8 75 | TUBE Yes Call TI | Nipdau Level-3-260C-168 HR -40 to 125 (O2132U, OPA) 2132U OPA2132U.B Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 125 (O2132U, OPA) 2132U OPA2132U/2K5 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-3-260C-168 HR -40 to 125 (O2132U, OPA) 2132U Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) OPA2132U/2K5.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 125 (O2132U, OPA) 2132U OPA2132UA Active Production SOIC (D) | 8 75 | TUBE Yes Call TI | Nipdau Level-3-260C-168 HR -40 to 125 (O2132UA, OPA) 2132U A OPA2132UA.B Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 125 (O2132UA, OPA) 2132U A OPA2132UA/2K5 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 (O2132UA, OPA) 2132U A OPA2132UA/2K5.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 (O2132UA, OPA) 2132U A OPA4132UA Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 OPA4132UA OPA4132UA.B Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAUAG Level-3-260C-168 HR -40 to 85 OPA4132UA OPA4132UA/2K5 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 OPA4132UA OPA4132UA/2K5.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAUAG Level-3-260C-168 HR -40 to 85 OPA4132UA (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 2

www.ti.com 7-Oct-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA132U/2K5 SOIC D 8 2500 353.0 353.0 32.0 OPA132UA/2K5 SOIC D 8 2500 353.0 353.0 32.0 OPA2132U/2K5 SOIC D 8 2500 353.0 353.0 32.0 OPA2132UA/2K5 SOIC D 8 2500 353.0 353.0 32.0 OPA4132UA/2K5 SOIC D 14 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) OPA132U D SOIC 8 75 506.6 8 3940 4.32 OPA132U.B D SOIC 8 75 506.6 8 3940 4.32 OPA132UA D SOIC 8 75 506.6 8 3940 4.32 OPA132UA.B D SOIC 8 75 506.6 8 3940 4.32 OPA2132P P PDIP 8 50 506 13.97 11230 4.32 OPA2132P.A P PDIP 8 50 506 13.97 11230 4.32 OPA2132PA P PDIP 8 50 506 13.97 11230 4.32 OPA2132PA.A P PDIP 8 50 506 13.97 11230 4.32 OPA2132PAG4 P PDIP 8 50 506 13.97 11230 4.32 OPA2132U D SOIC 8 75 506.6 8 3940 4.32 OPA2132U.B D SOIC 8 75 506.6 8 3940 4.32 OPA2132UA D SOIC 8 75 506.6 8 3940 4.32 OPA2132UA.B D SOIC 8 75 506.6 8 3940 4.32 OPA4132UA D SOIC 14 50 506.6 8 3940 4.32 OPA4132UA.B D SOIC 14 50 506.6 8 3940 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

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