OPA129UBE4

OPA129UBE4 TI | Alldatasheet

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Ultra-Low Bias Current Difet® OPERATIONAL AMPLIFIER

FEATURES

G ULTRA-LOW BIAS CURRENT: 100fA max G LOW OFFSET: 2mV max G LOW DRIFT: 10 µV/°C max G HIGH OPEN-LOOP GAIN: 94dB min G LOW NOISE: 15nV/ √Hz at 10kHz G PLASTIC DIP AND SO PACKAGES

APPLICATIONS

DESCRIPTION

The OPA129 is an ultra-low bias current monolithic operational amplifier offered in an 8-pin PDIP and SO-8 package. Using advanced geometry dielectrically-isolated FET ( Difet® ) inputs, this monolithic amplifier achieves a high performance level. Difet fabrication eliminates isolation-junction leakage current—the main contributor to input bias current with conventional monolithic FETs. This reduces input bias current by a factor of 10 to 100. Very low input bias current can be achieved without resorting to small-geometry FETs or CMOS designs which can suffer from much larger offset voltage, voltage noise, drift, and poor power-supply rejection. The OPA129 special pinout eliminates leakage current that occurs with other op amps. Pins 1 and 4 have no internal connection, allowing circuit board guard traces— even with the surface-mount package version. OPA129 is available in 8-pin DIP and SO packages, specified for operation from –40°C to +85°C. +In Output Noise-Free Cascode 30kΩ 30kΩ –In Simplified Circuit Substrate OPA129 OPA129 OPA129 SBOS026A – JANUARY 1994 – REVISED APRIL 2007 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1994–2007, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Difet is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

SBOS026Awww.ti.com SPECIFICATIONS ELECTRICAL At VS = ±15V and TA = +25°C, unless otherwise noted. Pin 8 connected to ground. NOTES: (1) High-speed automated test. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. OPA129PB, UB OPA129P, U PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS INPUT BIAS CURRENT (1) VCM = 0V ±30 ±100 * ±250 fA vs Temperature Doubles every 10 °C* INPUT OFFSET CURRENT VCM = 0V ±30 * fA OFFSET VOLTAGE Input Offset Voltage V CM = 0V ±0.5 ±2 ±1 ±5m V vs Temperature ±3 ±10 ±5 µV/°C Supply Rejection V S = ±5V to ±18V ±3 ±100 * * µV/V NOISE Voltage f = 10Hz 85 * nV/ √Hz f = 100Hz 28 * nV/ √Hz f = 1kHz 17 * nV/ √Hz f = 10kHz 15 * nV/ √Hz fB = 0.1Hz to 10Hz 4 * µVPP Current f = 10kHz 0.1 * fA/ √Hz INPUT IMPEDANCE Differential 1013 || 1 * Ω || pF Common-Mode 1015 || 2 * Ω || pF VOLTAGE RANGE Common-Mode Input Range ±10 ±12 * * V Common-Mode Rejection V IN = ±10V 80 118 * * dB OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R L ≥ 2kΩ 94 120 * * dB FREQUENCY RESPONSE Unity Gain, Small Signal 1 * MHz Full Power Response 20Vp-p, R L = 2kΩ 47 * kHz Slew Rate V O = ±10V, RL = 2kΩ 1 2.5 * * V/ µs Settling Time: G = –1, RL = 2kΩ, 10V Step 0.1% 5* µs 0.01% 10 * µs Overload Recovery, 50% Overdrive(2) G = –15 * µs RATED OUTPUT Voltage Output R L = 2kΩ± 12 ±13 * * V Current Output V O = ±12V ±6 ±10 * * mA Load Capacitance Stability Gain = +1 1000 * pF Short-Circuit Current ±35 ±55 * * mA POWER SUPPLY Rated Voltage ±15 * V Voltage Range, Derated Performance ±5 ±18 * * V Current, Quiescent I O = 0mA 1.2 1.8 * * mA TEMPERATURE Specification Ambient Temperature –40 +85 * * °C Operating Ambient Temperature –40 +125 * * °C Storage –40 +125 * * °C Thermal Resistance θJA, Junction-to-Ambient DIP-8 90 * °C/W SO-8 100 * °C/W

SBOS026A www.ti.com 1001 1M 10M 1k 10k 100k10 POWER SUPPLY REJECTION vs FREQUENCY Frequency (Hz) Power Supply Rejection (dB) 140 120 100 +PSRR –PSRR OPEN-LOOP FREQUENCY RESPONSE Frequency (Hz) Voltage Gain (dB) 140 120 100 1001 1M 10M θ 135 180 Pulse Shift (degrees) Gain 1k 10k 100k10 Phase Margin ≈90° ABSOLUTE MAXIMUM RATINGS NOTE: (1) Short circuit may be to power supply common at +25°C ambient. PACKAGE INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA129P DIP-8 P OPA129PB DIP-8 P OPA129U SO-8 D OPA129UB SO-8 D NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com. CONNECTION DIAGRAM ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to ob- serve proper handling and installation procedures can cause damage. ESD damage can range from subtle performance deg- radation to complete device failure. Precision inte- grated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Top View DIP/SO TYPICAL PERFORMANCE CURVES At TA = +25°C, +15VDC, unless otherwise noted. Substrate Output NC –In +In NC OPA NC: No internal connection.

SBOS026Awww.ti.com Frequency (Hz) FULL-POWER OUTPUT vs FREQUENCY Output Voltage (VPP ) 10k 100k1k 1M Frequency (Hz) INPUT VOLTAGE NOISE SPECTRAL DENSITY Voltage Density (nV/√Hz) 1 10 100 1k 10k 100k 100 0.1 0.01 –15 –10 –55 1 0 1 5 Common-Mode Voltage (V) BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE Normalized Bias and Offset Current BIAS AND OFFSET CURRENT vs TEMPERATURE Ambient Temperature (°C) Bias and Offset Current (fA) 100pA 10pA 1pA 100 –50 50 125–25 0 25 75 100 IB and IOS 1001 1M 10M 1k 10k 100k10 COMMON-MODE REJECTION vs FREQUENCY Frequency (Hz) Common-Mode Rejection (dB) 140 120 100 COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE Common-Mode Voltage (V) Common-Mode Rejection (dB) 15 15 10 10 505 120 110 100 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +15VDC, unless otherwise noted.

SBOS026A www.ti.com OPEN-LOOP GAIN, PSR AND CMR vs TEMPERATURE Ambient Temperature (°C) PSR, CMR, Voltage Gain (dB) 130 120 110 100 CMR A OL PSR –75 125–50 75–25 0 25 50 100 SUPPLY CURRENT vs TEMPERATURE Ambient Temperature (°C) Supply Current (mA) 2.0 1.5 1.0 0.5 –75 125–50 75 –25 0 25 50 100 Supply Voltage (±VCC ) GAIN BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE Gain Bandwidth (MHz) 51 502 0 Slew Rate (v/µs) +Slew –Slew GBW GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE Ambient Temperature (°C) Gain Bandwidth (MHz) Slew Rate (V/µs) –75 125–50 75–25 0 25 50 100 LARGE SIGNAL TRANSIENT RESPONSE Time (µs) Output Voltage (V) –10 05 0 25 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +15VDC, unless otherwise noted. SMALL SIGNAL TRANSIENT RESPONSE Time (µs) Output Voltage (mV) –40 01 0 2468 –80 5µs5V 1µs20mV

TA = +25°C, +15VDC, unless otherwise noted. FIGURE 1. Offset Adjust Circuit. The OPA129 has no conventional offset trim connections. the Circuit Board Layout section. should have a guard trace on both sides of the circuit board. potential. This minimizes leakage current and noise pick-up. input connectors and input cables can cause noise and drift.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) OPA129P OBSOLETE PDIP P 8 TBD Call TI Call TI OPA129PB OBSOLETE PDIP P 8 TBD Call TI Call TI OPA129U ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UB ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UB/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UBE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UBG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 24-Feb-2009 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA129UB/2K5 SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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