OPA129 BURR-BROWN | Alldatasheet
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Technical content
Ultra-Low Bias Current Difet® OPERATIONAL AMPLIFIER
FEATURES
l ULTRA-LOW BIAS CURRENT: 100fA max l LOW OFFSET: 2mV max l LOW DRIFT: 10 µV/°C max l HIGH OPEN-LOOP GAIN: 94dB min l LOW NOISE: 15nV/ √Hz at 10kHz l PLASTIC DIP and SOIC PACKAGE
APPLICATIONS
DESCRIPTION
The OPA129 is an ultra-low bias current mono- lithic operational amplifier offered in an 8-pin PDIP and SO-8 package. Using advanced geometry dielectrically-isolated FET ( Difet® ) inputs, this mono- lithic amplifier achieves a high performance level. Difet fabrication eliminates isolation-junction leakage current—the main contributor to input bias current with conventional monolithic FETs. This reduces input bias current by a factor of 10 to 100. Very low input bias current can be achieved without resorting to small-geometry FETs or CMOS designs which can suffer from much larger offset voltage, voltage noise, drift, and poor power supply rejection. The OPA129's special pinout eliminates leakage cur- rent that occurs with other op amps. Pins 1 and 4 have no internal connection, allowing circuit board guard traces—even with the surface-mount package version. OPA129 is available in 8-pin DIP and SO-8 packages, specified for operation from –40°C to +85°C. OPA129 Difet® Burr-Brown Corp. +In Output Noise-Free Cascode 30kΩ 30kΩ –In Simplified Circuit Substrate International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1994 Burr-Brown Corporation PDS-1195A Printed in U.S.A. July, 1994
At VS = ±15V and TA = +25°C unless otherwise noted. Pin 8 connected to ground. NOTES: (1) High-speed automated test. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. OPA129PB, UB OPA129P, U PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS INPUT BIAS CURRENT (1) VCM = 0V ±30 ±100 * ±250 fA vs Temperature Doubles every 10 °C* INPUT OFFSET CURRENT VCM = 0V ±30 * fA OFFSET VOLTAGE Input Offset Voltage V CM = 0V ±0.5 ±2 ±1 ±5m V vs Temperature ±3 ±10 ±5 µV/°C Supply Rejection V S = ±5V to ±18V ±3 ±100 * * µV/V NOISE Voltage f = 10Hz 85 * nV/ √Hz f = 100Hz 28 * nV/ √Hz f = 1kHz 17 * nV/ √Hz f = 10kHz 15 * nV/ √Hz fB = 0.1Hz to 10Hz 4 * µVp-p Current f = 10kHz 0.1 * fA/ √Hz INPUT IMPEDANCE Differential 1013 || 1 * Ω || pF Common-Mode 1015 || 2 * Ω || pF VOLTAGE RANGE Common-Mode Input Range ±10 ±12 * * V Common-Mode Rejection V IN = ±10V 80 118 * * dB OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R L ≥ 2kΩ 94 120 * * dB FREQUENCY RESPONSE Unity Gain, Small Signal 1 * MHz Full Power Response 20Vp-p, R L = 2kΩ 47 * kHz Slew Rate V O = ±10V, RL = 2kΩ 1 2.5 * * V/ µs Settling Time: G = –1, R L = 2kΩ, 10V Step 0.1% 5* µs 0.01% 10 * µs Overload Recovery, 50% Overdrive(2) G = –1 5 * µs RATED OUTPUT Voltage Output R L = 2kΩ± 12 ±13 * * V Current Output V O = ±12V ±6 ±10 * * mA Load Capacitance Stability Gain = +1 1000 * pF Short-Circuit Current ±35 ±55 * * mA POWER SUPPLY Rated Voltage ±15 * V Voltage Range, Derated Performance ±5 ±18 * * V Current, Quiescent I O = 0mA 1.2 1.8 * * mA TEMPERATURE Specification Ambient Temperature –40 +85 * * °C Operating Ambient Temperature –40 +125 * * °C Storage –40 +125 * * °C Thermal Resistance θJA, Junction-to-Ambient PDIP—"P" 90 * °C/W SOIC—"U" 100 * °C/W
POWER SUPPLY REJECTION vs FREQUENCY Frequency (Hz) Power Supply Rejection (dB) 140 120 100 +PSRR –PSRR OPEN-LOOP FREQUENCY RESPONSE Frequency (Hz) Voltage Gain (dB) 140 120 100 1001 1M 10M θ 135 180 Pulse Shift (degrees) Gain 1k 10k 100k10 Phase Margin ≈90° ABSOLUTE MAXIMUM RATINGS NOTE: (1) Short circuit may be to power supply common at +25°C ambient.
PACKAGE INFORMATION
MODEL PACKAGE NUMBER (1) OPA129P 8-pin Plastic DIP 006 OPA129PB 8-pin Plastic DIP 006 OPA129U 8-pin SOIC 182 OPA129UB 8-pin SOIC 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. CONNECTION DIAGRAM ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Top View DIP/SOIC TYPICAL PERFORMANCE CURVES TA = +25°C, +15VDC, unless otherwise noted. Substrate Output NC –In +In NC OPA NC: No internal connection.
Frequency (Hz) FULL-POWER OUTPUT vs FREQUENCY Output Voltage (Vp-p) 10k 100k1k 1M Frequency (Hz) INPUT VOLTAGE NOISE SPECTRAL DENSITY Voltage Density (nV/√Hz) 1 10 100 1k 10k 100k 100 0.1 0.01 15 –10 –5 5 10 15 Common-Mode Voltage (V) BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE Normalized Bias and Offset Current BIAS AND OFFSET CURRENT vs TEMPERATURE Ambient Temperature (°C) Bias and Offset Current (fA) 100pA 10pA 1pA 100 –50 50 125–25 0 25 75 100 IB and IOS 1001 1M 10M 1k 10k 100k10 COMMON-MODE REJECTION vs FREQUENCY Frequency (Hz) Common-Mode Rejection (dB) 140 120 100 COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE Common-Mode Voltage (V) Common-Mode Rejection (dB) 15 15 10 10 505 120 110 100 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, +15VDC, unless otherwise noted.
OPEN-LOOP GAIN, PSR AND CMR vs TEMPERATURE Ambient Temperature (°C) PSR, CMR, Voltage Gain (dB) 130 120 110 100 CMR A OL PSR –75 125–50 75–25 0 25 50 100 SUPPLY CURRENT vs TEMPERATURE Ambient Temperature (°C) Supply Current (mA) 1.5 0.5 –75 125–50 75–25 0 25 50 100 Supply Voltage (±VCC ) GAIN BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE Gain Bandwidth (MHz) 51 502 0 Slew Rate (v/µs) +Slew –Slew GBW GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE Ambient Temperature (°C) Gain Bandwidth (MHz) Slew Rate (V/µs) –75 125–50 75–25 0 25 50 100 LARGE SIGNAL TRANSIENT RESPONSE Time (µs) Output Voltage (V) –10 05 0 25 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, +15VDC, unless otherwise noted. SMALL SIGNAL TRANSIENT RESPONSE Time (µs) Output Voltage (mV) –40 01 0 2468 –80
Supply Voltage (±VCC ) COMMON-MODE INPUT RANGE vs SUPPLY VOLTAGE Common-Mode Voltage (+V) 51 002 0 BIAS CURRENT vs ADDITIONAL POWER DISSIPATION Additional Power Dissipation (mW) Bias Current (fA) 100pA 10pA 1pA 100 0 200 35050 100 150 250 300 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, +15VDC, unless otherwise noted. APPLICATIONS INFORMATION NON-STANDARD PINOUT The OPA129 uses a non-standard pinout to achieve lowest possible input bias current. The negative power supply is connected to pin 5—see Figure 1. This is done to reduce the leakage current from the V- supply (pin 4 on conventional op amps) to the op amp input terminals. With this new pinout, sensitive inputs are separated from both power supply pins.FIGURE 1. Offset Adjust Circuit. OFFSET VOLTAGE TRIM The OPA129 has no conventional offset trim connections. Pin 1, next to the critical inverting input, has no internal connection. This eliminates a source of leakage current and allows guarding of the input terminals. Pin 1 and pin 4, next to the two input pins, have no internal connection. This allows an optimized circuit board layout with guarding—see “circuit board layout.” Due to its laser-trimmed input stage, most applications do not require external offset voltage trimming. If trimming is required, the circuit shown in Figure 1 can be used. Power supply voltages are divided down, filtered and applied to the non-inverting input. The circuit shown is sensitive to varia- tion in the supply voltages. Regulation can be added, if needed. GUARDING AND SHIELDING Ultra-low input bias current op amps require precautions to achieve best performance. Leakage current on the surface of circuit board can exceed the input bias current of the ampli- fier. For example, a circuit board resistance of 10 12Ω from a power supply pin to an input pin produces a current of 15pA—more than one-hundred times the input bias current of the op amp. To minimize surface leakage, a guard trace should com- pletely surround the input terminals and other circuitry connecting to the inputs of the op amp. The DIP package should have a guard trace on both sides of the circuit board. The guard ring should be driven by a circuit node equal in potential to the op amp inputs—see Figure 2. The substrate, pin 8, should also be connected to the circuit board guard to assure that the amplifier is fully surrounded by the guard potential. This minimizes leakage current and noise pick-up. Careful shielding is required to reduce noise pickup. Shield- ing near feedback components may also help reduce noise pick-up. Triboelectric effects (friction-generated charge) can be a troublesome source of errors. Vibration of the circuit board, input connectors and input cables can cause noise and drift. Make the assembly as rigid as possible. Attach cables to avoid motion and vibration. Special low noise or low leak- age cables may help reduce noise and leakage current. Keep all input connections as short possible. Surface-mount com- ponents may reduce circuit board size and allow a more rigid assembly. OPA129 VOUT VIN R F R IN 2 0.1µF220Ω 470kΩ 470kΩ