OPA124UA/2K5

OPA124 TI1 | Alldatasheet

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Technical content

l LOW NOISE: 6nV/√Hz (10kHz) l LOW BIAS CURRENT: 1pA max l LOW OFFSET: 250 µV max l LOW DRIFT: 2µV/°C max l HIGH OPEN-LOOP GAIN: 120dB min l HIGH COMMON-MODE REJECTION: 100dB min l AVAILABLE IN 8-PIN PLASTIC DIP AND 8-PIN SOIC PACKAGES APPLICA TIONS l PRECISION PHOTODIODE PREAMP l MEDICAL EQUIPMENT l OPTOELECTRONICS l DATA ACQUISITION l TEST EQUIPMENT OPA124

DESCRIPTION

The OPA124 is a precision monolithic FET opera- tional amplifier using a Difet (dielectrical isolation) manufacturing process. Outstanding DC and AC per- formance characteristics allow its use in the most critical instrumentation applications. Bias current, noise, voltage offset, drift, open-loop gain, common-mode rejection and power supply re- jection are superior to BIFET and CMOS amplifiers. Difet fabrication achieves extremely low input bias currents without compromising input voltage noise performance. Low input bias current is maintained over a wide input common-mode voltage range with unique cascode circuitry. This cascode design also allows high precision input specifications and reduced susceptibility to flicker noise. Laser trimming of thin- film resistors gives very low offset and drift. Compared to the popular OPA111, the OPA124 gives comparable performance and is available in an 8-pin PDIP and 8-pin SOIC package. BIFET ® National Semiconductor Corp., Difet® Burr-Brown Corp. Low Noise Precision Difet ® OPERATIONAL AMPLIFIER Substrate Output Trim(1) +V CC Noise-Free Cascode(2) Trim(1) +In –In –V CC 2kΩ 2kΩ 2kΩ 10kΩ 10kΩ NOTES: (1) Omitted on SOIC. (2) Patented. 2kΩ OPA124 Simplified Circuit International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1993 Burr-Brown Corporation PDS-1203C Printed in U.S.A. March, 1998 OPA124 SBOS028

At VCC = ±15VDC and TA = +25°C, unless otherwise noted. OPA124U, P OPA124UA, PA OPA124PB PARAMETER CONDITION MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT NOISE Voltage, f fO = 100Hz(4) 15 40 [[ [[ nV/√Hz fO = 1kHz(4) 81 5 [[ [[ nV/√Hz fO = 10kHz(5) 68 [[ [[ nV/√Hz fB = 10Hz to 10kHz(5) 0.7 1.2 [[ [[ µVrms fB = 0.1Hz to 10Hz 1.6 3.3 [[ [[ µVp-p Current, fB = 0.1Hz to 10Hz 9.5 15 [[ [[ fAp-p fO = 0.1Hz thru 20kHz 0.5 0.8 [[ [[ fA/√Hz OFFSET VOLTAGE (1) Input Offset Voltage V CM = 0VDC ±200 ±800 ±150 ±500 ±100 ±250 µV vs Temperature T A = TMIN to TMAX ±4 ±7.5 ±2 ±4 ±1 ±2 µV/°C Supply Rejection V CC = ±10V to ±18V 88 110 90 [ 100 [ dB vs Temperature T A = TMIN to TMAX 84 100 86 [ 90 [ dB BIAS CURRENT (1) Input Bias Current V CM = 0VDC ±1 ±5 ±0.5 ±2 ±0.35 ±1p A OFFSET CURRENT (1) Input Offset Current V CM = 0VDC ±1 ±5 ±0.5 ±1 ±0.25 ±0.5 pA IMPEDANCE Differential 10 13 || 1 [[ Ω || pF Common-Mode 10 14 || 3 [[ Ω || pF VOLTAGE RANGE Common-Mode Input Range ±10 ±11 [[ [[ V Common-Mode Rejection V IN = ±10VDC 92 110 94 [ 100 [ dB vs Temperature T A = TMIN to TMAX 86 100 [[ 90 [ dB OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R L ≥ 2kΩ 106 125 [[ 120 [ dB FREQUENCY RESPONSE Unity Gain, Small Signal 1.5 [[ MHz Full Power Response 20Vp-p, R L = 2kΩ 16 32 [[ [[ kHz Slew Rate V O = ±10V, RL = 2kΩ 1 1.6 [[ [[ V/µs THD 0.0003 [[ % Settling Time, 0.1% Gain = –1, R L = 2kΩ 6 [[ µs 0.01% 10V Step 10 [[ µs Overload Recovery, 50% Overdrive (2) Gain = –1 5 [[ µs RATED OUTPUT Voltage Output R L = 2kΩ± 11 ±12 [[ [[ V Current Output V O = ±10VDC ±5.5 ±10 [[ [[ mA Output Resistance DC, Open Loop 100 [[ Ω Load Capacitance Stability Gain = +1 1000 [[ pF Short Circuit Current 10 40 [[ [[ mA POWER SUPPLY Rated Voltage ±15 [[ VDC Voltage Range, Derated ±5 ±18 [[ [[ VDC Current, Quiescent I O = 0mADC 2.5 3.5 [[ [[ mA TEMPERATURE RANGE Specification T MIN and TMAX –25 +85 [[ [[ °C Storage –65 +125 [[ [[ °C θ Junction-Ambient: PDIP 90 [[ °C/W SOIC 100 [[ °C/W [ Specification same as OPA124U, P NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up. For performance at other temperatures see Typical Performance Curves. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (3) For performance at other temperatures see Typical Performance Curves. (4) Sample tested, 98% confidence. (5) Guaranteed by design.

S Output Offset Trim Offset Trim –In +In S Top View SOIC Substrate S Output NC NC –In +In S NC = No Connect The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PACKAGE/ORDERING INFORMATION BIAS OFFSET PACKAGE TEMPERATURE CURRENT DRIFT PRODUCT PACKAGE DRAWING NUMBER (1) RANGE pA, max µV/°C, max OPA124U 8-Lead SOIC 182 –25 °C to +85°C 5 7.5 OPA124P 8-Pin Plastic DIP 006 –25 °C to +85°C 5 7.5 OPA124UA 8-Lead SOIC 182 –25 °C to +85°C2 4 OPA124PA 8-Pin Plastic DIP 006 –25 °C to +85°C2 4 OPA124PB 8-Pin Plastic DIP 006 –25 °C to +85°C1 2 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS (1) NOTES: (1) Stresses above these ratings may cause permanent damage. (2) Packages must be derated based on θJA = 90°C/W for PDIP and 100°C/W for SOIC. (3) For supply voltages less than ±18VDC, the absolute maximum input voltage is equal to +18V > VIN > –VCC – 6V. See Figure 2. (4) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE –50 –25 0 25 50 75 100 125 Temperature (°C) 100 0.1 0.01 fO = 1kHz Voltage Noise (nV/√Hz) Current Noise (fA/√Hz) TYPICAL PERFORMANCE CURVES At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. INPUT CURRENT NOISE SPECTRAL DENSITY Frequency (Hz) 100101 10k 100k 1M 100

0.1 Current Noise (fA/√Hz)

INPUT VOLTAGE NOISE SPECTRAL DENSITY Frequency (Hz) 10k 100k 1M100101 100 U, P PB Voltage Noise (nV/√Hz) TOTAL (1) INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE 100 Frequency (Hz) 1k 10k 100k1010.1 100 R S = 10MΩ R S = 1MΩ R S = 100kΩ R S = 100Ω PB NOTE: (1) Includes contribution from source resistance. Voltage Noise (nV/√Hz) TOTAL (1) INPUT VOLTAGE NOISE (PEAK-TO-PEAK) vs SOURCE RESISTANCE 100 Voltage Noise (µVp-p) NOTE: (1) Includes contribution from source resistance. Source Resistance (Ω ) 105 106 107 108 109 1010 PB fB = 0.1Hz to 10Hz TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT 1kHz vs SOURCE RESISTANCE 100 100 1k 10k 100k 1M 10M 100M Source Resistance ( )Ω Resistor Noise Only OPA124PB + Resistor E O R S Voltage Noise, EO (nV/√Hz)

vs INPUT COMMON-MODE VOLTAGE –15 Common-Mode Voltage (V) –10 –5 0 5 10 15 Common-Mode Rejection (dB) 120 110 100 BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE –15 –10 –5 0 5 10 15 0.1

0.01 Bias Current (pA)

0.1 0.01 Offset Current (pA) Common-Mode Voltage (V) Bias Current Offset Current OPEN-LOOP FREQUENCY RESPONSE Frequency (Hz) 10 100 1k 10k 100k 1M 10M Voltage Gain (dB) 140 120 100 Phase Margin ≈ 65° –45 –90 –135 –180 Phase Shift (Degrees) Gain COMMON-MODE REJECTION vs FREQUENCY Frequency (Hz) 10 100 1k 10k 100k 1M 10M Common-Mode Rejection (dB) 140 120 100 POWER SUPPLY REJECTION vs FREQUENCY Frequency (Hz) 10 100 1k 10k 100k 1M 10M Power Supply Rejection (dB) 140 120 100 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. BIAS AND OFFSET CURRENT vs TEMPERATURE –50 Ambient Temperature (°C) –25 0 25 50 75 100 125 100 0.1 0.1 0.01 Offset Current (pA)

SMALL SIGNAL TRANSIENT RESPONSE Time (µs) –20 –40 –60 Output Voltage (mV) 23 4 LARGE SIGNAL TRANSIENT RESPONSE Time (µs) 05 0 –10 –15 Output Voltage (V) 20 30 40 MAXIMUM UNDISTORTED OUTPUT VOLTAGE vs FREQUENCY 100k Frequency (Hz) 1k 10k 1M Output Voltage (Vp-p) OPEN-LOOP GAIN vs TEMPERATURE 140 130 120 110 100 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) Voltage Gain (dB) GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE Gain Bandwidth (MHz) Slew Rate (V/µs) 5 1 01 52 0 Supply Voltage (±VCC ) GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) Gain Bandwidth (MHz) Slew Rate (V/µs) TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VCC = ±15VDC, unless otherwise noted.

INPUT OFFSET VOLTAGE WARM-UP DRIFT –10 –20 Time From Power Turn-On (Minutes) Offset Voltage Change (µV) 0 123456 SUPPLY CURRENT vs TEMPERATURE –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) Supply Current (mA) SETTLING TIME vs CLOSED-LOOP GAIN Closed-Loop Gain (V/V) 10 100 1k 100 Settling Time (µs) 0.1%0.01% TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK 150 –75 –150 Time From Thermal Shock (Minutes) Offset Voltage Change (µV) – 1 012345 +25°C +85°C PB U, P TA = +25°C to TA = +85°C Air Environment

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) OPA124P OBSOLETE PDIP P 8 TBD Call TI Call TI OPA124PA OBSOLETE PDIP P 8 TBD Call TI Call TI OPA124PA2 OBSOLETE PDIP P 8 TBD Call TI Call TI OPA124PB OBSOLETE PDIP P 8 TBD Call TI Call TI OPA124U ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UA ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UAE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UAG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2009 Addendum-Page 1

information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2009 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2009 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA124U/2K5 SOIC D 8 2500 346.0 346.0 29.0 OPA124UA/2K5 SOIC D 8 2500 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2009 Pack Materials-Page 2

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