OP50

Op50_1.PDF

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• Manufacturer or author: Joyce Arivella
• PDF pages: 11

Technical content

| . . 3, P| DEVICES Operational Amplifier “i , 3 = 5) FEATURES ORDERING INFORMATIONt orvenne © Excellent TCV0g oo .eeccccecceceresecese ODAC Mae 95 OP-soay SSCL : OO HIGNCMAR ees ccccceerecseseresees $2668 Min 100 OP-50BY" MIL © Low Noise I Saewh/He @ t= tot, —100_OP-sofy_Ino__ sbecesseeeesscesee ee SSMWA/ HE @ f= thitz, . Fer devious procossodin tte comptence e MiL-STO-B89,eda/4H9 fer bat © Drives Capacitive Loads up to 10nF CerDtP, plaatic DIP, and TO-can packages. ‘emperaiue i © On-Board Thermal Shutdown Circuit i » Avaitable i te Form ; GENERAL DESCRIPTION } NNE The OP-50 eliminates the need for an output butter in appli- i PIN CONNECTIONS cations which require high load-driving capability coupled , with premium amplifier performance. The output stage can omy felt drive +50mA into 500 loads. In addition, the output is stable ~ ctl, pms with capacitive loads of up to 10nF. This load driving ability L “@ [>| oe «PIN HERMETIC DIP ‘makes the OP-50 ideal for amplifying small signals tor trans- a 2 (Y-Sutfix) mission through long cables. The amplifier features open- » por loop voltage gain of over 10 million with common-mode ed Bs sore: rejection and power supply rejection of greater than 12608 ronan nT (WE grades). SIMPLIFIED SCHEMATIC exrennat cckateantion ped i Pe | a iH fiji Ure iG gt 1 || ap Le, eS |: ee} [Lol io) [¢) poe Esti om % He Jone YY ry [te \\ \\ ® ® Ww H wea Y 1 ad ! y ! Pare jo rama ! c ant “ veo" -*MOTE SEPARATE SUPPLIES FOR OUTPUT STAGE. Manulactured under the following patents: 4.471.321 and 4,503,381. ote

b OP-50 ‘The OP-50is stable for closed-loop gains above 50, andcan —_Athermat-shutdown circuit protects the OP-50 from overdis- beexternally compensated for closed-loop gainsin therange —_sipation. When the die temperature reaches approximately of 5 to 50. The amplifier is designed for use in high-gain 165°C, the output stage automatically shuts down. The and/or high-output-current applications. For example, an amplifier input stage remains fully operational, thereby pro- OF-07 coupled with an output butter can be replaced by a _tecting the signal source trom any loading changes caused single OP-50 amplifier. by a complete shutdown. lon-implanted superbeta transistors, combined with a pat- ented inputblascurrentcanceliation clrcult,provideaninput + COMPENSATION FOR GAINS BETWEEN § AND 50 bias currento! only SnAand inputoftset currentot ind. Over The OP-SO.can be compensated for inverting gains between the full military temperature range, input bias current and 8 8d SO using a series resistor and capacitor. These values input otfeet current for an A-grade device does not exceed cA? be Adjusted to minimize overshoot for a given applica- SnA and 3nA. respectively. Input offset voltages are trimmed tion. The recommended compensation is: toa maximum of 25uV (A/E grades) and 100yV (B/F grades) using PMI's zener-zapping technique. This low offset elimi- GAIN RANGE Rc Ce nates the need for an offset trimpot in most applications. “Tenens SSCS ZAve = 20 eon Tn Low voltage-noise, typically 4.5nV/\\/Hz at 1kHz, isachieved 205 Aya. S $0 ska inf in the OP-50 with minimum sacrifice of input protection. Aver? 50 No compensation required t Overioad protection is provided by input resistors of 2500. and emitter-base diodes. The input resistors provide current ~— COMPENSATION limit protection against differentia! inputs of up to +10V; and the diodes prevent avalanche breakdown which could ' degrade the Ip. fos. and matching of the input stage transis- &e: tors. External resistors can be added to the input to guard a against higher input voltages; however, the added resistors ue 1 will degrade noise voltage performance. When minimum ' noise voltage is required, source resistance should be kept below a few hundred ohms. Separate output-stage power supply pins are provided on the OP-50 to allow control of device power dissipation and out- put voltage swing. The maximum voltage which may be applied aurose the power supply pins is +18V. The guaran. ABSOLUTE MAXIMUM RATINGS (Note 1) teed specifications are based on operating both stages at Supply Vonage (Note 2) sesesenonnnveeeecenscencennnoesessen swe IBV N1SV: however, there is minimal effect on DC performance PU VOHE® oer nnnnnntetnnnnnnenesenes SUPPRY Vottage when the main amplifier is operated at +15V and the output Diflerentil Input Voltage (Note 3) «re vornrsnnrnns 8 1OV Stage is operated ata ceduced voltage. When operating both ifferential input Current (Note 2) snnnnnnennmneerce OFA the main amplifier and the output stage at the same voltages, Output Short Great Duration nonce Indefinite Decoupling capacitors are recommended between the power OPerating Temperature Range . . supply pins and analog ground. It is necessary to use decou- OP-SOA, B -.scsscssessneesereesnnnerseneessesereseersees GO"C 10, +128°C pling capacitors on each power supply pin when operating OP-50E, F erenenmmnnrnernnnninnnnns 25°C 10 485°C the output stage at supply voltages less than the amplifier Lead Temperature (Soldering, 60 sec) smn 300°C. supply voltage, Do not operate the output-stage negative Junction Temperate (7) wn n-n-vnewe- 85 C to +150C power supply pin at a more negative voltage than the nega- PACKAGE TYPE e, NOTES) Oe units H tive supply pin (V-). — 14-Piq Hermetic DIP (Y) LJ 2 “cw A thermally-symmetric die layout, which differs from other os opamp designs by the positioning of more devices along the +, absolute ratings apply to both DICE and packaged parts, uniess otherwise i center line, provides the OP-50 with a thermal drift of less toed. than 0.3n¥/°C. This layout feature is critical to the mainte- 2 Sevohy anager applion to all power sunt one “ should nance of high open-loop gain when driving large-current connected toa voiage mare negative . loads and diesipating hundreds of milliwatts in the device, __* Tne OF-27% woum wo proces oy 2500 sere eaten tr Pere ' The use of a heatsink is recommended to reduce internal Dotted te odomA, * temperature rise when operating at high output power levels. 4. @,, 0 pected for wore! case mounting condiions, Ie. @,, is specified for ‘The use of standard dual-in-line package heatsinks will help vice in socket tor CorDIP package. to dissipate heat to the environment. Other techniques, such as the use of external voltage-dropping resistors, allow heat to be dissipated outside of the package. See Figure, “Driving 5 5012 Loads”, in the applications section. t : *

ELECTRICAL CHARACTERISTICS at V+ = +Vop = +15V, V- =-Vop = -15V, Ta = 25°C, no compensation. unless otherwise ; noted. I ee ; OP-6OA/E OP-50B/F PARAMETER svmeot__CONOTTIONS ton ve ax tm TAX unr ‘put Otfest votage You =o = © Ww Input Bias Current ‘e =n 3s = #0 nA Input Otteat Current los = mt =o 3 7A input voltage Range wa CMR 2 10048 2 mS v R, 2 8000 23 me om Quapat Vonage Sete Yo 2 500 (Note 1) ts ao ws m0 y Vi = WVop= 45¥, Ves Vop=-V Cutout Wohegs Swing Yo R= S000 oe as na - y A=son ee re H erry Slow Rate sn R= Seon 2 30 2 300 = Vs c= Ane conn Man Vou" 210¥ mw wo a ry Rejection Rao Powe Sy rm yetevesty Doe Peiection Ratio Large-Sian oe No Vo £10V, Ry = tkh. a 1% 1% = va Mottage Gain NNO Gain-Bandwiath Product cow ‘Avex = 60 (Note 2) cr 3s 8 ez Soerge tafe Ap 100K0, so ts no 8 = ow “Range sojust i Input Noiee Voltage ow 1=0.tHr to 10H = ow = en Wee t= 10H = 85 8s - ss 6s Noise Voltage Density “ FEI (ote 3) = 8 8 = BB whe Noise Current vw 1=0.0H2 19 10H = 2 = 2 Pape T= 1ooHe - 0 = =o = = Noise Current Deity ‘ tome ~ os oe , uencent Supply ley No Load - 2% 33 - 2 33 mA Curent Poative Current uit tise ‘Quiput shorted t Ground os wo oo 8 2 ma ( Negative Current Limit “lee Output shores o Ground os wo os 120 an Ditterontial- Mode re , rapa Reuwtnes Pwo 20 - - 2 = un Common-Moge | na Anes _ - ~» - a Gu t ; Avazs a Cepective Lead cn Re = S800 (Note 2) wo - = w - = oF Capability Co= Ant ‘Setting 10 0.01%, Vo= 20Vp-p i ‘Settiing-Time & Aver = 600 - ww - - » - “ t \\ mores: 1. Guaranteed by current limit teat. i 2. Guaranteed by design 3. Sample tested.

: | oe ELECTRICAL CHARACTERISTICS at V+ = +Vop= +15V, V- = -Vop=-15V, -25°C $ Tas +85°C, no compensation, unless otherwise noted. esse . OP-SOE OP-SOF PARAMETER srmeoL__ CONDTIONS tan TYP MAK wn TYP MAX uwiTs Input Otteat Vonage Vos. =» 4 =» ww Input Ottoet Votage Ont TCVos (ea 1) — om a3 - os 14 wee Input Bias Current Ie 27 - 2 oA Input Offset Current oe = 02s = 02, on Input Offset “ Current Drift Telos ros 7-8 parc Input Bias Current Orit Tey 7? 7 pare nput Voltage Range NR ‘CMAR > 10068. ans Ere v Output Voltage Swing Vo R, 25000 a2 ta He 34 v ‘Common-Mode non cMAR Vou 210¥ cs ws w= cy Power Supply “ _ _ eae Psa Vg- #8V 10 215V 05 125 os 125 ay Quescent Supply lev No Load - 2 4 - 2 4 mA orm Vour = £10, ‘Open-Loap Gain Avo mri (Note?) 4B vv notes: 1. TCVog tested on € grade, guaranteed by design on F grade specification : 2. Guaranteed by design. ELECTRICAL CHARACTERISTICS at Vt = 1Vop= 1 15V, V- =-Vop=-15V. -55°C < Tas +125°C, no compensation. unless otherwise noted. piciiadieinesitdtsia oo SEED OP-S0A OP-50B PARAMETER SyMBOL CONDITIONS tn TP ax we TYP Max ours Input Offeet Voltage Yos =» ee) w veuneieim TCVos — as a3 - 0 1 wee Input Bias Current 'e - 2 8 - #2 == oA ‘ Input Otteet Current los = 05 3 - 05 A Jagat Offest _ _ _ _ ‘Current Dritt Telos 3 s parc Input Bias Current Det bhithd Fe aie input Voluge Range WR ‘MRA 2 10008, ms = sO - v : Output vonage Swing Y% R.> soon Te ee es v Common-Mode eto cMAR Vous ™ #100 —_ wm mw a fr) Power Supply aection Ratio PSRR Vg 28V to 215 - 05 125 — 08 128 ww Ounces Buea ler tio Lose - ow 4 - mo. ma Burret Vo= 210¥, _ _ Open-Loop Gain Avo Rerun’ (woe? 4 0 «0 vin NOTE: 1. Tested at +128°C, guaranteed by design at -85°C.

[Cr i | DICE CHARACTERISTICS ' — = - | fF gaen7* 2tg or ' - . p Wf Ny 1. NONINVERTING INPUT | | oy af a 4 Loe. rs 2. INVERTING INPUT AS : ‘ ‘het 6. ourpuT | —_ 4 ' i a 1. “Wop | { the bt , ave - bee j 10. +¥op | ~ ob a NU 11. COMPENSATION | an oo, 12. COMPENSATION b. wee t TT 13. NULL ve of. Lat 14, NULL oa) pol oreners : 18. V- (OPTIONAL BONDING PAD)" ee ee) Ces CT) Bee ne DIE SIZE 0.140 X 0.111 inch, 16,539 0g. mie (2.78 X 262 mm, 10.66 99. mom) WAFER TEST LIMITS at V+ = +Vop= +15V, V- = -Vop = -15V. Ta = 25°C. no compensation, unless otherwise noted. Pie i sets SSDS OP-50G PARAMETER symsou CONDITIONS uit ‘UNITS: Input Oftsat Voltage Vos a Input Bias Current lp 210 AAMAX Input Oftect Current tos 3 nA MAX Output Voltage Swing Yo R, 2 $0001 213 vMIN V+ = +Vop = 45V, V- = -Vop = “BV Output Voltage Swing Yo A, = S000 +38 vMIN A= son 225 Common-Mode a Rabo MAR Vou = £10V _ v0 48 MIN owe SPP PsRA Ven 8V 10 18V tt AV MAX ie No Yo 210.8, = tet 1s VAN MIN Positive Current Limit ee ‘Output shorted to Ground _ Cy AMIN Negative Current Limit als. ‘Output shorted to Ground 60 mAMIN (Quiescent Supply lw No Load 33 mA MAX NOTE: Electrical teats are performed at wafer probe to the limite shown. Due to variations in assembly methods and normal yal loss. yield alter packaging 's nor quaranteed for standard product dice. ‘Consult factory to negotiate specifications based on dice lot qualification through sample fot assembly and testing

TYPICAL ELECTRICAL CHARACTERISTICS at V+ = +Vop= + 15V. V- =-Vop=~ 15V. Ta = 25°C, no compensation, unless otherwise noted. pedeinshelhneinatte a ne UU EEE SSE OP-50G PARAMETER syMBOu CONDITIONS TYPICAL UNITS RL 2 2Ki ‘Siew Rate sa Rc = S60t1 3 vine Ge=aror ‘Noise Voltage Density * lee s ove Input Noise Vonage One-9 120.142 to 10H2 0.12 ee Noise Current Density in ee . os anal Capacitive Load Ava 2S Ceoubilty q R= S801 0 oF ee &e a NOISE TEST CIRCUIT (0.1 TO 10Hz) eur tons. : wean x 7 eal pecTnum os ao me ates i 1 7 ad T ‘ fal So OSF + fth ri > ea ‘i i 1 = = 2 = o-w + BURN-IN CIRCUIT OFFSET NULLING CIRCUIT yan = [ng Ne our S—courrut = ; 2 y a fm a ' ¥ we 7 -~ a ALU RFAISTOWRS ARE 1H METAL PIL ra

! a TYPICAL PERFORMANCE CHARACTERISTICS INPUT OFFSET VOLTAGE INPUT BIAS CURRENT INPUT BIAS CURRENT ve TEMPERATURE ve SUPPLY VOLTAGE vs COMMON-MODE VOLTAGE a “ET | : CPA FEA RSS Pest ee a EA . COONS i HPCE SS APRA ECE eer to ee ee “Ss ee es Cr er er ee ey ° . ry wow ian naouettan a . a Spaaron SeuenaTone “Pe TTT) LT TT Ts “AA AAA “TTT Ty LT | Pa “eC Cece POU Pipe oe RSSESN POUTTAL ER Ti ot Coo ! MNT CC Be HH : coe) “CA EE Ce eee CAPACITIVE LOAD FREQUENCY raequency : “om aN “Cn ire a ' as COMIN eee st A i ap NOT fs CNS] fc ENR Es TANT an i! a oS PH CNT =f} —-NIN POG 0 0 Rc | ol al CT-N ry : fh » i abs. e Ny at UU a a i i i ee Tate wore eeteclineee tong eons eterna loge

TYPICAL PERFORMANCE CHARACTERISTICS. PSAR vs SUPPLY CURRENT SUPPLY CURRENT FREQUENCY vs TEMPERATURE vs SUPPLY VOLTAGE a “he TTT | toa SING CLEP ETT , = PPX RT ose Li PONS a eet ‘ ix POO jE = wt NA [| t— ON =a id MCC } PANE HHH w+ TIN TY wT TTT TT ' “CoCr SC Trt SCL TT | 5 ewmere me rs °F amrvarenen SHORT-CIRCUIT CURRENT CURRENT NOISE DENSITY VOLTAGE NOISE DENSITY « ve TEMPERATURE » ve FREQUENCY \\e we FREQUENCY FH JE eS ae aa ari) ari mri Meee NE 7. NOT TT “ i | HN ag MU TET ett TENT i” AMM: 0 RU i TTC COOCOT SS Ay ai, S40 A Rammer A ete mm oa A fe es TOTAL HARMONIC TOTAL HARMONIC DISTORTION DISTORTION OTO tHz vs FREQUENCY va LOAD RESISTANCE NOISE VOLTAGE DENSITY "Tram ] “CTT ee] i cst @ COMM | i Ht CO ae | a om OS NE ont | PA “ i_UIAR ont So Bevowvennn | Fen} oS : [eee vet feet i a

TYPICAL PERFORMANCE CHARACTERISTICS GAIN, PHASE SHIFT CLOSED-LOOP GAIN OUTPUT VOLTAGE SWING ' ww vs FREQUENCY » . vs FREQUENCY vs LOAD RESISTANCE Tm”: Wl Joo sn 80 A =e ll TT TIAN 4 Com i En} —Y . Pa i 0 wii Nill il All COR. ENG ig St Cre ies Ten “iii he” ee an Sill HH IH aa eee eA AU) AM ae ai sc) a OUTPUT VOLTAGE SWING SMALL-SIGNAL OVERSHOOT MAXIMUM OUTPUT SWING 14 ve LOAD RESISTANCE . vs CAPACITIVE LOAD » vs FREQUENCY ! Y= a ss) Coen |= CS CONES | : TOU C «= CMT Tg ies i, Cote TTT IN ii ees = HARA WT LL A: Ce ee ' en ee a a Ni PTR =| Citic * ITN OUTPUT IMPEDANCE pen = oo eens anvimmtne , i cziie eat emt on CUE ' CASAC Ht oe COO

TCVos TEST CIRCUIT overdriving of the long-talled transistor pair and stop satura~ ' tion of the output transistor. Power supply voltage is set to wen £5V to lower the quiescent power dissipation and minimize thermal feedback due to output stage dissipation. Operating : from +5V supplies also reduces the OP-50 rise and fall times as the output slews over a reduced voltage range. This, in vow | tum, reduces the output response time. It is common practice with voltage comparators to ground ° ‘one input terminal and to use @ single-ended input. The | % historic reason is poor common-mode rejection on the input bore stage. In contrast, the OP-50 has very high common-mode f ial Lt rejection and is capable of detecting microvolt level differ- wv ‘ences in the presence of large common-mode signals. svemiay TPE SHE RESEETORS The comparator is not fast, but it is very sensitive and can detect signal differences as low as 0.3uV. With large input overdrives, the circuit responds in approximately 3us. If sharp transitions are needed, the use of a TTL Schmitt- APPLICATIONS INFORMATION trigger input is recommended. A table of Response Time vs. Input Overdrive is shown below. HIGH-SENSITIVITY VOLTAGE COMPARATOR ‘Acomparatorcapeble of resolving asubmicrovoltditierence — ipyt OVERDRIVE 100mv 10m tm 100,V _10,V signal is shown in Figure 1. The OP-60, operating without arg feedback, drives a second gain stage which generates a TTL- Posi Doiay : wart { compatible output signal. Schottky-clamp diodes prevent Negative Output Delay 1.88 Sus S0ue 38048 4Sms i r” a0 oFTucowarmer a ; on + { : s by | 25 = ow FIGURE 1: HIGH-SENSITIVITY VOLTAGE COMPARATOR: -10-

INTEGRATOR AND UNITY-GAIN BUFFER Figure 2 shows a method of obtaining unity-gain in a butfer wags KTS configuration. The R1 and C1 network provides input com- pensation to circumvent the minimum gain requirement. 8 Figure 3 shows the same technique applied in the inverting mode to form a high precision integrator. | rane ora sare na Voerorrry ©'our iH at “wi ws = 6 Your “| ‘ od i = orn romano CURRENT rm VOLTAGE COMPLIANCE, 111.2 @ yy 204 FIGURE 2: UNITY GAIN BUFFER Sai aenvauttlor caRdnvecoas, se ‘ FIGURE 4: 20mA CURRENT SOURCE A ORIVING SON LOADS wo—w E Tne OP-50.can provide up to SOMA into a 5011 load and up to c | oseur 26mA into a 00M load. The outputs stable driving capacitive wT om, 4 toads of up to 10nF. ar 4 amr Applications that make use of the high output current capa- m8 bility of the OP-50 will cause increased power dissipation in “ the amplifier. To reduce internal dissipation in these applica- . tions, external voltage dropping resistors can be connected in series with the output-stage power supply pins. As shown in Figure 5, 1300 resistors can be attached to pin 7 (-Vop) and FIGURE 3: INTEGRATOR to pin 10 (+Vop). To maintain stability and specified perfor- mance levels, 0.047yF decoupling capacitors should be used 20mA CURRENT SOURCE as indicated from pin 7 and pin 10 to ground. The 20mA current source expioits the high output current ' ‘and high linearity capabilities of the OP-50. Five precision w resistors and a trim potentiometer are required in this circult ry configuration, known as the Howland Current Pump. The o trim potentiometer is used to balance the resistive feedback mot <a Toor dividers. This maximizes the current-source output impe- > .* dance. Compensation is selected for a voltage gain of 10. ovo Compliance is better than +11V at an output current of 20mA. wo | 0 ‘and the trimmed output resistance is typically 2MN with id and A, < 500M. The transter function is given by: 18 ost ort one Neu = VINOHEED 0.1 Amps 0-18

101 NOTE:

IREEIHTORS Rt ANO.R2 REDUCE 1¢ POWER DISSIPATION. ‘Vin (oir) is the differential input voltage. For the resistor : values shown in Figure 4, the maximum Vin (or) is 200mV. FIGURE §: DRIVING 5011 LOADS