OP497FS

OP497 AD | Alldatasheet

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REV.D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a OP497 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Precision Picoampere Input Current Quad Operational Amplifier

FEATURES

Low Offset Voltage: 50 /H9262V max Low Offset Voltage Drift: 0.5 /H9262V//H11543C max Very Low Bias Current 25/H11543C: 100 pA max –55/H11543C to +125/H11543C: 450 pA max Very High Open-Loop Gain: 2000 V/mV min Low Supply Current (per Amplifier): 625 /H9262A max Operates from /H115502 V to /H1155020 V Supplies High Common-Mode Rejection: 120 dB min

APPLICATIONS

Strain Gage and Bridge Amplifiers High Stability Thermocouple Amplifiers Instrumentation Amplifiers Photo-Current Monitors High Gain Linearity Amplifiers Long-Term Integrators/Filters Sample-and-Hold Amplifiers Peak Detectors Logarithmic Amplifiers Battery-Powered Systems GENERAL DESCRIPTION The OP497 is a quad op amp with precision performance in the space-saving, industry standard 16-lead SOlC package. Its com- bination of exceptional precision with low power and extremely low input bias current makes the quad OP497 useful in a wide variety of applications. Precision performance of the OP497 includes very low offset, under 50 µV, and low drift, below 0.5 µV/°C. Open-loop gain exceeds 2000 V/mV ensuring high linearity in every application. Errors due to common-mode signals are eliminated by the OP497’s common-mode rejection of over 120 dB. The OP497’s power supply rejection of over 120 dB minimizes offset voltage changes experienced in battery-powered systems. Supply current of the OP497 is under 625 µA per amplifier, and it can operate with supply voltages as low as ± 2 V. The OP497 utilizes a superbeta input stage with bias current can- cellation to maintain picoamp bias currents at all temperatures. This is in contrast to FET input op amps whose bias currents start in the picoamp range at 25°C, but double for every 10°C rise in temperature, to reach the nanoamp range above 85°C. Input bias current of the OP497 is under 100 pA at 25°C and is under 450 pA over the military temperature range. Combining precision, low power, and low bias current, the OP497 is ideal for a number of applications, including instru- mentation amplifiers, log amplifiers, photo-diode preamplifiers, and long-term integrators. For a single device, see the OP97; for a dual device, see the OP297. PIN CONNECTIONS 16-Lead Wide Body SOIC (S-Suffix) – + NC = NO CONNECT OUT A –IN A +IN A +IN B –IN B OUT B OUT D –IN D +IN D +IN C –IN C OUT C NCNC – + –+ OP497 14-Lead Plastic Dip (P-Suffix) 14-Lead Ceramic Dip (Y-Suffix) OUT A –IN A +IN A +IN B –IN B OUT B OUT D –IN D +IN D +IN C –IN C OUT C – + –+ – + –+ OP497 VS = /H1155015V VCM = 0V 1000 100 –75 –50 –25 0 25 50 75 100 125 INPUT CURRENT – PA TEMPERATURE – C –IB +IB IOS Input Bias, Offset Current vs. Temperature

REV. D–2– OP497–SPECIFICATIONS(@ VS = 15 V, TA = 25/H11543C, unless otherwise noted.) A F C/G Parameter Symbol Condition Min Typ Max Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage Vos 20 50 40 75 80 150 µV –40°C ≤ +85°C 70 150 120 250 –55°C ≤ +125°C 40 100 80 150 140 300 Average Input Offset Long-Term Input Offset Voltage Stability 0.1 0.1 0.1 µV/Mo Input Bias Current I B VCM = 0 V 30 100 40 150 60 200 pA –40° ≤ TA ≤ +85°C 60 200 80 300 –55° ≤ TA ≤ +125°C 80 450 110 600 130 600 Average Input Bias Current Drift TC IB –40° ≤ TA ≤ +85°C 0.3 0.3 Input Offset Current Ios V CM = OV 15 100 30 150 50 200 pA –40° ≤ TA ≤ +85°C 50 200 80 300 –55° ≤ TA ≤ +125°C 35 400 60 600 90 600 Average Input Offset Current Drift T CIOS 0.2 0.3 0.4 pA/ °C Input Voltage Range 1 IVR + 13 +14 +13 tl4 +13 +14 V TMIN – TMAX +13 +13.5 +13 +13.5 +13 +13.5 Common-Mode Rejection CMR V CM = ± 13 V 120 140 114 135 114 135 dB TMIN – TMAX 114 130 108 120 108 120 Large Signal Voltage Gain A VO VO = ± 10 V, RL = 2 kΩ 2000 6000 1500 4000 1200 4000 V/mV –40° ≤ TA ≤ +85°C 800 2000 800 2000 –55° ≤ TA ≤ +125°C 1200 4000 1000 3000 800 3000 Input Resistance Differential Mode R IN 30 30 30 M Ω Input Resistance Common Mode R INCM 500 500 500 G Ω Input Capacitance C IN 33 3 p F OUTPUT CHARACTERISTICS Output Voltage Swing V O RL = 2 kΩ± 13 ± 13.7 ± 13 ± 13.7 ± 13 ± 13.7V RL = 10 kΩ± 13 ± 14 ± 13 ± 14 ± 13 ± 14 TMIN – TMAX RL = 10 kΩ± 13 ± 13.5 ± 13 ± 13.5 ± 13 ± 13.5 Short Circuit I SC ± 25 ± 25 ± 25 mA POWER SUPPLY Power Supply PSRR Vs = ± 2 V to ±20 V 120 140 114 135 114 135 dB Rejection Ratio Vs = ±2.5 V to ± 20 V TMIN – TMAX 114 130 108 120 108 120 Supply Current I SY No Load 525 625 525 625 525 625 µA (per Amplifier) T MIN – TMAX 580 750 580 750 580 750 Supply Voltage Range V S Operating Range ± 2 ± 20 ± 2 ± 20 ± 2 ± 20 V TMIN – TMAX ± 2.5 ± 20 ± 2.5 ± 20 ± 2.5 ± 20 DYNAMIC PERFORMANCE Gain Bandwidth Product GBW 500 500 500 kHz Channel Separation CS V O = 20 Vp-p, fo = 10 Hz 150 150 150 dB NOISE PERFORMANCE Voltage Noise e n p-p 0.1 Hz to 10 Hz 0.3 0.3 0.3 µV/p-p Voltage Noise Density e n = 10 Hz 17 17 17 nV/ √Hz en = 1 kHz 15 15 15 nV/ √Hz Current Noise Density i n = 10 Hz 20 20 20 fA/ √Hz NOTE 1Guaranteed by CMR Test. Specifications subject to change without notice.

REV. D OP497 –3– ORDERING GUIDE Temperature Package Package Model Range Description Option OP497AY* –55°C to +125°C 14-Lead Cerdip Q-14 OP497CY* –55°C to +125°C 14-Lead Cerdip Q-14 OP497FP –40 °C to +85°C 14-Lead Plastic DIP N-14 OP497FS –40 °C to +85°C 16-Lead SOIC R-16 OP497GP –40 °C to +85°C 14-Lead Plastic DIP N-14 OP497GS –40 °C to +85°C 16-Lead SOIC R-16 *Not for new design; obsolete April 2002. For a military processed devices, please refer to the Standard Microcircuit Drawing (SMD) available at www.dscc.dla.mil/ programs.milspec./default.asp. SMD Part Number ADI Part Number 5962–9452101M2A* OP497BRC 5962–9452101MCA OP497BY *Not for new designs; obsolete April 2002. DICE CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS 1 Storage Temperature Range Operating Temperature Range Junction Temperature Package Type /H9258JA 3 /H9258JC Unit 14-Pin Cerdip (Y) 94 10 °C/W 14-Pin Plastic DIP (P) 76 33 °C/W 16-Pin SOIC (S) 92 23 °C/W NOTES 1Absolute Maximum Ratings apply to both DICE and packaged parts, unless otherwise noted. 2For supply voltages less than ± 20 V, the absolute maximum input voltage is equal to the supply voltage. 3HIA is specified for worst-case mounting conditions, i.e., /H9258JA is specified for device in socket for cerdip, P-DIP packages; /H9258JA is specified for device soldered to printed circuit board for SOIC package. OP497 2k/H9024 V1 20V p–p @ 10Hz CHANNEL SEPARATION = 20 log V /100002 50/H9024 50k/H9024 OP497 Channel Separation Test Circuit CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP497 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

REV. D OP497 –4– –Typical Performance Characteristics (25/H11543C, Vs = 15 V, unless otherwise noted.) 100 –80 –100 806040200–20–40–60 INPUT OFFSET VOLTAGE – /H9262V PERCENTAGE OF UNITS TA = 25/H11543C VS = 15V VCM = 0V TPC 1. Typical Distribution of Input Offset Voltage TCVOS – /H9262V//H11543C PERCENTAGE OF UNITS 0 0.8 0.1 VS = /H1155015V VCM = 0V TPC 4. Typical Distribution of TCVOS /H115503 /H115501 /H115502 432 TIME AFTER POWER APPLIED – Minutes DEVIATION FROM FINAL VALUE – /H9262V TA = 25/H11543C VS = /H1155015V VCM = 0V TPC 7. Input Offset Voltage Warm-Up Drift 100 –80 –100 806040200–20–40–60 INPUT BIAS CURRENT – pA PERCENTAGE OF UNITS TA = 25/H11543C VS = 15V VCM = 0V TPC 2. Typical Distribution of Input Bias Current VS = /H1155015V VCM = 0V 1000 100 –75 –50 –25 0 25 50 75 100 125 INPUT CURRENT – pA TEMPERATURE – /H11543C –IB +IB IOS TPC 5. Input Bias, Offset Current vs. Temperature 10 100 1k 10k 100k 1M 10M 10000 1000 100 SOURCE RESISTANCE – /H9024 EFFECTIVE OFFSET VOLTAGE – /H9262V –55 C T 125 CA T = +25 CA BALANCED OR UNBALANCED VS = 15V VCM = 0V TPC 8. Effective Offset Voltage vs. Source Resistance INPUT OFFSET CURRENT – pA PERCENTAGE OF UNITS 50403020 TA = 25/H11543C VS = 15V VCM = 0V TPC 3. Typical Distribution of Input Offset Current –10 –15 1050–5 COMMON-MODE VOLTAGE – Volts INPUT BIAS CURRENT – pA TA = 25 C VS = /H1155015V –IB +IB TPC 6. Input Bias Current vs. Common-Mode Voltage 100 1k 10k 100k 1M 10M 100 0.1 SOURCE RESISTANCE – /H9024 EFFECTIVE OFFSET VOLTAGE – /H9262V/ /H11543C 100M BALANCED OR UNBALANCED VS = 15V VCM = 0V TPC 9. Effective TCVOS vs. Source Resistance

REV. D –5– OP497 1 10 100 1000 100 FREQUENCY – Hz 1000 VOLTAGE NOISE DENSITY – nV/ Hz CURRENT NOISE DENSITY – fA / Hz CURRENT NOISE VOLTAGE NOISE TA = 25/H11543C VS = 2V TO 20V TPC 10. Voltage Noise Density vs. Frequency 100 –40 10M –20 100 1M100k10k 225 180 135 FREQUENCY – Hz OPEN-LOOP GAIN – dB PHASE SHIFT – DEG GAIN PHASE VS = /H1155015V CL = 30pF RL = 1M/H9024 TA = 25/H11543C TPC 13. Open-Loop Gain, Phase vs. Frequency 160 101 100 120 140 100k10k1k100 FREQUENCY – Hz COMMON - MODE REJECTION – dB VS = /H1155015V TA= 25/H11543C TPC 16. Common-Mode Rejection vs. Frequency 0.1 0.01 SOURCE RESISTANCE – /H9024 TOTAL NOISE DENSITY – /H9262V/ Hz TA = 25/H11543C VS = /H115502V TO /H1155020V 102 103 104 105 106 107 1kHz 10Hz TPC 11. Total Noise Density vs. Source Resistance LOAD RESISTANCE – k/H9024 OPEN - LOOP GAIN – V/ MV VS = /H1155015V VO = /H1155010V 10000 1000 100 11 0 2 0 TA = –55/H11543C TA = +25C TA = +125/H11543C TPC 14. Open-Loop Gain vs. Load Resistance 160 101 100 120 140 100k10k1k100 FREQUENCY – Hz POWER SUPPLY REJECTION – dB –PSR +PSR VS = /H1155015V TA = 25/H11543C TPC 17. Power Supply Rejection vs. Frequency 100 1s5mV VS = 15V TA = 25/H11543C NOISE VOLTAGE – 100mV/DIV 02 4 681 0 TIME – Secs TPC 12. 0.1 Hz to 10 Hz Noise Voltage 15–10–15 10 50–5 OUTPUT VOLTAGE – V DIFFERENTIAL INPUT VOLTAGE – 10/H9262V/ DIV RL = 2k/H9024 VS = /H1155015V VCN = /H1155010V TA= +125/H11543C TA= +25/H11543C TA= –55/H11543C TPC 15. Open-Loop Gain Linearity FREQUENCY – Hz 100k 100 10k OUTPUT SWING – Vp-p VS= /H1155015V TA= 25/H11543C AVCL= +1 1%THD RL = 10k/H9024 TPC 18. Maximum Output Swing vs. Frequency

REV. D OP497 –6– /H1155020 1.0 0.5 /H1155050 1.5 –1.5 –1.0 –0.5 /H1155015/H1155010 SUPPLY VOLTAGE – V INPUT COMMON-MODE VOLTAGE – Volts (REFERRED TO SUPPLY VOLTAGES) +VS –VS TA = 25/H11543C TPC 19. Input Common-Mode Voltage Range vs. Supply Voltage 700 200 /H1155020 500 300 /H115505 400 600 /H1155015/H1155010 NO LOAD SUPPLY VOLTAGE – V SUPPLY CURRENT (PER AMPLIFIER) – /H9262A +125 C +25 C –55 C TPC 22. Supply Current (per Amplifier) vs. Supply Voltage LOAD CAPACITANCE – pF 10k 100 OVERSHOOT – % VS = /H1155015V TA = 25 C AVCL = +1 VOUT = 100mV p–p TPC 25. Small-Signal Overshoot vs. Capacitance Load LOAD RESISTANCE – /H9024 10k 100 OUTPUT SWING – Vp-p VS = /H1155015V TA = 25/H11543C AVCL= +1 1%THD fO = 1kHz TPC 20. Maximum Output Swing vs. Load Resistance 1000 0.001 100k 0.01 0.1 100 10k1k100 AV = +1 VS = 15V TA = 25 C TPC 23. Closed-Loop Output Impedance vs. Frequency /H1155020 1.0 0.5 /H1155050 1.5 –1.5 –1.0 –0.5 /H1155015/H1155010 SUPPLY VOLTAGE – V OUTPUT VOLTAGE SWING – V (REFERRED TO SUPPLY VOLTAGES) +VS –VS TA = 25/H11543C RL = 10k/H9024 TPC 21. Output Voltage Swing vs. Supply Voltage –35 –20 –30 –25 –15 TIME FROM OUTPUT SHORT – Mins SHORT CIRCUIT CURRENT – mA TA = +125 C TA = +25 C TA = –55 C VS = /H1155015V OUTPUT SHORTED TO GROUND TA = +125 C TA = –55 C TA = +25 C TPC 24. Short-Circuit Current vs. Time Temperature –IN +IN 2.5k/H9024 VOUT 2.5k/H9024 TPC 26. Simplified Schematic Showing One Amplifier

Figure 9. A Simple Bridge Conditioning Amplifier Using

7 VOUTI O

Figure 10. Squaring Amplifier

7 VOUTIO

Figure 11. Square-Root Amplifier

REV. D OP497 –11– * Node assignments * noninverting input * inverting input * positive supply * negative supply * output *SUBCKT OP497 1 2 99 50 27 * INPUT STAGE AND POLE AT 6 MHz RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 6.782E8 R2 7 3 6.782E8 R3 5 99 542.57 R4 6 99 542.57 CIN 7 8 3E-12 C2 5 6 24.445E-12 I1 4 50 0.1E-3 IOS 7 8 15E-12 EOS 9 7 POLY(1) 16 21 40E-6 1 Q 1 581 0 Q X Q 2 691 1 Q X R5 10 4 25.374 R6 11 4 25.374 D 1 89D X D 2 98D X EREF98 0 21 0 1 *GAIN STAGE AND DOMINANT POLE AT 0.11 Hz R7 1 98 2.1703E9 C3 2 98 666.67E-12 G1 98 12 5 V1 99 13 1.275 V2 11 9 1.275 D3 12 13 DX D4 14 12 DX *COMMON-MODE GAIN NETWORK WITH ZERO AT 50 MHz RCM1 15 16 1E6 CCM 15 16 3.18E-9 RCM2 16 98 1 ECM 15 98 3 21 177.83E-3 * NEGATIVE ZERO AT 1.8 MHz E1 17 98 12 21 1E6 R8 17 18 1E6 C4 17 18 –88.419E-15 R9 18 98 1 * POLE AT 6 MHz G2 98 19 18 21 1E-6 R15 20 98 1E6 C8 20 98 26.526E-15 * POLE AT 1.8 MHz G6 98 20 19 21 1E-6 R20 20 98 1E6 C10 20 98 88.419E-15 * OUTPUT STAGE R16 99 21 160 k R17 21 50 160 k ISY 99 50 331E-6 V3 23 22 1.9 D5 20 23 DX V4 22 24 1.9 D6 24 20 DX D7 99 25 DX G4 25 50 20 22 5E-3 D9 50 25 DY D8 99 26 DX G5 26 50 22 20 5E-3 D10 50 26 DY G6 22 99 99 20 5E-3 R18 99 22 200 G7 50 22 20 50 5E-3 R19 22 50 200 L1 22 27 0.1E-6 * MODELS USED .MODEL QX NPN (BF = 1.25E6) .MODEL DX (IS = 1E-15) .MODEL DZ D(IS = 1E-15 BV = 50) .ENDS OP497 Table I. OP497 SPICE Net-List

–12– C00309–0–2/02(D) PRINTED IN U.S.A.

Revision History

11/01—Data Sheet changed from REV. C to REV. D. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Ceramic DIP (Y-Suffix) PIN 1 14 8 0.005 (0.13) MIN 0.098 (2.49) MAX 0.310 (7.87) 0.220 (5.59) 0.200 (5.08) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) MIN 0°–15° 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37) 0.785 (19.94) MAX SEATING PLANE 14-Lead Epoxy DIP (P-Suffix) PIN 1 14 8 7 0.325 (8.25) 0.300 (7.62) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.92) 0.022 (0.558) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) MIN 0°–15° 0.015 (0.38) 0.008 (0.20) 0.280 (7.11) 0.240 (6.10) 0.015 (0.381) MIN 0.795 (20.19) 0.725 (18.41) 16-Lead Wide-Body SOIC (S-Suffix) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.050 (1.27) BSC 16 9 8 1 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40)PIN 1 0.4133 (10.50) 0.3977 (10.00) 0.0125 (0.32) 0.0091 (0.23) 8/H11543 0/H11543 0.0291 (0.74) 0.0098 (0.25) /H11547 45/H11543 0.0500 (1.27) 0.0157 (0.40)