OP491

OP191 AD | Alldatasheet

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Tel: 617/329-4700 Fax: 617/326-8703 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a OP191/OP291/OP491 GENERAL DESCRIPTION The OP191, OP291 and OP491 are single, dual and quad micropower, single-supply, 3 MHz bandwidth amplifiers fea- turing rail-to-rail inputs and outputs. All are guaranteed to operate from a 3 volt single supply as well as ± 5 volt dual supplies. Fabricated on Analog Devices’ CBCMOS process, the OP191 family has a unique input stage that allows the input voltage to safely extend 10 volts beyond either supply without any phase inversion or latch-up. The output voltage swings to within millivolts of the supplies and continues to sink or source current all the way to the supplies. Applications for these amplifiers include portable telecom equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezo electric, and resistive transducers. The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and maintain high signal-to-noise ratios. The OP191/OP291/OP491 are specified over the extended industrial (–40°C to +125°C) temperature range. The OP191 single and OP291 dual amplifiers are available in 8-pin plastic DIPs and SO surface mount packages. The OP491 quad is available in 14-pin DIPs and narrow 14-pin SO packages. Consult factory for OP491 TSSOP availability. Micropower Single-Supply Rail-to-Rail Input/Output Op Amps OP191/OP291/OP491 PIN CONFIGURATIONS 8-Lead Narrow-Body SO 8-Lead Epoxy DIP (S Suffix) (P Suffix) NC = NO CONNECT OP191 OUTA NC NCNC –INA +INA OP191 8-Lead Narrow-Body SO 8-Lead Epoxy DIP (S Suffix) (P Suffix) OP291 OUTB –INB +INB +VOUTA –INA +INA OP291 14-Lead Epoxy DIP 14-Lead SO (P Suffix) (S Suffix) OP491 OUTD –IND +IND +INC –INC OUTC OUTA –INA +INA +INB –INB OUTB OP491 OUTD –IND +IND +INC –INC OUTC OUTA –INA +INA +INB –INB OUTB 14-Lead TSSOP (RU Suffix) OP491

FEATURES

Single-Supply Operation: 2.7 V to 12 V Wide Input Voltage Range Rail-to-Rail Output Swing Low Supply Current: 300 µ A/Amp Wide Bandwidth: 3 MHz Slew Rate: 0.5 V/ µ s Low Offset Voltage: 700 µ V No Phase Reversal

APPLICATIONS

Industrial Process Control Battery Powered Instrumentation Power Supply Control and Protection Telecom Remote Sensors Low Voltage Strain Gage Amplifiers DAC Output Amplifier

OP191/OP291/OP491–SPECIFICATIONS ELECTRICAL SPECIFICATIONS Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage OP191G V OS 80 500 µV –40 ≤ TA ≤ +125°C1 m V OP291/OP491G V OS 80 700 µV –40 ≤ TA ≤ +125°C 1.25 mV Input Bias Current I B 30 50 nA –40 ≤ TA ≤ +125°C7 0 n A Input Offset Current I OS 0.1 8 nA –40 ≤ TA ≤ +125°C1 6 n A Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 2.9 V 70 90 dB –40 ≤ TA ≤ +125°C6 5 8 7 d B Large Signal Voltage Gain A VO RL = 10 kΩ , VO = 0.3 V to 2.7 V 25 70 V/mV –40 ≤ TA ≤ +125°C 50 V/mV Offset Voltage Drift ΔVOS/ΔT 1.1 µV/°C Bias Current Drift ΔIB/ΔT 100 pA/ °C Offset Current Drift ΔIOS/ΔT 20 pA/ °C OUTPUT CHARACTERISTICS Output Voltage High V OH RL = 100 kΩ to GND 2.95 2.99 V –40°C to +125°C 2.90 2.98 V RL = 2 kΩ to GND 2.8 2.9 V –40°C to +125°C 2.70 2.8 V Output Voltage Low V OL RL = 100 kΩ to V+ 4.5 10 mV –40°C to +125°C3 5 m V RL = 2 kΩ to V+ 40 75 mV –40°C to +125°C 130 mV Short Circuit Limit I SC Sink/Source ± 8.75 ± 13.5 mA Open Loop Impedance Z OUT f = 1 MHz, AV = 1 200 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V S = 2.7 V to 12 V 80 110 dB –40°C ≤ TA ≤ +125°C 75 110 dB Supply Current/Amplifier I SY VO = 0 V 200 350 µA –40°C ≤ TA ≤ +125°C 330 480 µA DYNAMIC PERFORMANCE Slew Rate +SR R L = 10 kΩ 0.4 V/ µs Slew Rate –SR R L = 10 kΩ 0.4 V/ µs Full-Power Bandwidth BW P 1% Distortion 1.2 kHz Settling Time t S To 0.01% 22 µs Gain Bandwidth Product GBP 3 MHz Phase Margin θO 45 Degrees Channel Separation CS f = 1 kHz, R L = 10 kΩ 145 dB NOISE PERFORMANCE Voltage Noise e n p-p 0.1 Hz to 10 Hz 2 µV p-p Voltage Noise Density e n f = 1 kHz 35 nV/ √Hz Current Noise Density i n 0.8 pA/ √Hz Specifications subject to change without notice. (@ VS = +3.0 V, VCM = 0.1 V, VO = 1.4 V, TA = +25°C unless otherwise noted) REV. 0–2–

REV. 0 –3– ELECTRICAL SPECIFICATIONS(@ VS = +5.0 V, VCM = 0.1 V, VO = 1.4 V, TA = +25°C unless otherwise noted) Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage OP191 V OS 80 500 µV –40 ≤ TA ≤ +125°C 1.0 mV OP291/OP491 V OS 80 700 µV –40 ≤ TA ≤ +125°C 1.25 mV Input Bias Current I B 30 50 nA –40 ≤ TA ≤ +125°C6 0 n A Input Offset Current I OS 0.1 8 nA –40 ≤ TA ≤ +125°C1 6 n A Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 4.9 V 70 93 dB –40 ≤ TA ≤ +125°C6 5 9 0 d B Large Signal Voltage Gain A VO RL = 10 kΩ , VO = 0.3 V to 4.7 V 25 70 V/mV –40 ≤ TA ≤ +125°C 50 V/mV Offset Voltage Drift ΔVOS/ΔT –40 ≤ TA ≤ +125°C 1.1 µV/°C Bias Current Drift ΔIB/ΔT 100 pA/ °C Offset Current Drift ΔIOS/ΔT 20 pA/ °C OUTPUT CHARACTERISTICS Output Voltage High V OH RL = 100 kΩ to GND 4.95 4.99 V –40°C to +125°C 4.90 4.98 V RL = 2 kΩ to GND 4.8 4.85 V –40°C to +125°C 4.65 4.75 V Output Voltage Low V OL RL = 100 kΩ to V+ 4.5 10 mV –40°C to +125°C3 5 m V RL = 2 kΩ to V+ 40 75 mV –40°C to +125°C 155 mV Short Circuit Limit I SC Sink/Source ± 8.75 ± 13.5 mA Open Loop Impedance Z OUT f = 1 MHz, AV = 1 200 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V S = 2.7 V to 12 V 80 110 dB –40 ≤ TA ≤ +125°C 75 110 dB Supply Current/Amplifier I SY VO = 0 V 220 400 µA –40 ≤ TA ≤ +125°C 350 500 µA DYNAMIC PERFORMANCE Slew Rate +SR R L = 10 kΩ 0.4 V/ µs Slew Rate –SR R L = 10 kΩ 0.4 V/ µs Full-Power Bandwidth BW P 1% Distortion 1.2 kHz Settling Time t S To 0.01% 22 µs Gain Bandwidth Product GBP 3 MHz Phase Margin θO 45 Degrees Channel Separation CS f = 1 kHz, R L = 10 kΩ 145 dB NOISE PERFORMANCE Voltage Noise e n p-p 0.1 Hz to 10 Hz 2 µV p-p Voltage Noise Density e n f = 1 kHz 35 nV/ √Hz Current Noise Density i n 0.8 pA/ √Hz NOTES +5 V specifications are guaranteed by +3 V and ± 5 V testing. Specifications subject to change without notice. OP191/OP291/OP491

Specifications subject to change without notice. Figure 1. Input and Output with Inputs Overdriven by 5 V

REV. 0 –5– ABSOLUTE MAXIMUM RATINGS 1 Storage Temperature Range Operating Temperature Range Junction Temperature Range Package Type θJA 2 θJC Units 8-Pin Plastic DIP (P) 103 43 °C/W 8-Pin SOIC (S) 158 43 °C/W 14-Pin Plastic DIP (P) 76 33 °C/W 14-Pin SOIC (S) 120 36 °C/W 14-Pin TSSOP (RU) 180 35 °C/W NOTES 1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket for P-DIP packages; θJA is specified for device soldered in circuit board for TSSOP and SOIC packages. WAFER TEST LIMITS Parameter Symbol Conditions Limit Units Offset Voltage V OS ± 300 µV max Input Bias Current I B 50 nA max Input Offset Current I OS 8n A Input Voltage Range V CM V– to V+ V min Common-Mode Rejection Ratio CMRR V CM = 0 V to +2.9 V 70 dB min Power Supply Rejection Ratio PSRR V = 2.7 V to +12 V 80 dB min Large Signal Voltage Gain A VO RL = 10 kΩ 50 V/mV min Output Voltage High V OH RL = 2 kΩ to GND 2.8 V min Output Voltage Low V OL RL = 2 kΩ to V+ 75 mV max Supply Current/Amplifier I SY VO = 0 V, RL = ∞ 350 µA max NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. (@ VS = +3.0 V, VCM = 0.1 V, TA = +25°C unless otherwise noted) ORDERING GUIDE Temperature Package Package Model Range Description Option OP191GP –40 °C to +125°C 8-Pin Plastic DIP N-8 OP191GS –40 °C to +125°C 8-Pin SOIC SO-8 OP191GBC +25 °C DICE OP291GP –40 °C to +125°C 8-Pin Plastic DIP N-8 OP291GS –40 °C to +125°C 8-Pin SOIC SO-8 OP291GBC +25 °C DICE OP491GP –40 °C to +125°C 14-Pin Plastic DIP N-14 OP491GS –40 °C to +125°C 14-Pin SOIC SO-14 OP491HRU –40 °C to +125°C 14-Pin TSSOP RU-14 OP491GBC +25 °C DICE OP191 Die Size 0.047 × 0.066 Inch, 3,102 Sq. Mils. Substrate (Die Back- side) Is Connected to V+. Transistor Count, 74. 1 8 7 8 7 1 8 7 OP291 Die Size 0.070 × 0.070 Inch, 4,900 Sq. Mils. Substrate (Die Back- side) Is Connected to V+. Transistor Count, 146 DICE CHARACTERISTICS 2 1 14 13 9876 OP491 Die Size 0.070 × 0.110 Inch, 7,700 Sq. Mils. Substrate (Die Back- side) Is Connected to V+. Transistor Count, 290.

Figure 3. OP291 Input Offset Volt- Figure 6. Input Offset Current

40 VS = +3V

Figure 9. Open-Loop Gain & Phase Figure 2. OP291 Input Offset Voltage Figure 5. Input Bias Current vs. Figure 8. Output Voltage Swing Figure 4. Input Offset Voltage vs. Figure 7. Input Bias Current vs. Figure 10. Open-Loop Gain vs.

Figure 11. Closed-Loop Gain vs. Figure 14. PSRR vs. Frequency, Figure 17. Supply Current vs.

40 CMRR

Figure 12. CMRR vs. Frequency, Figure 15. PSRR vs. Temperature, Figure 18. Maximum Output Swing Figure 13. CMRR vs. Temperature, Figure 16. Slew Rate vs. Tempera- Figure 19. Voltage Noise Density,

Figure 22. Input Offset Voltage vs. Figure 25. Input Bias Current vs. Figure 28. Open-Loop Gain vs. Figure 20. OP291 Input Offset Volt- Figure 23. Input Bias Current vs. Figure 26. Output Voltage Swing vs. Figure 21. OP291 Input Offset Volt- Figure 24. Input Offset Current vs.

40 VS = +5V

Figure 27. Open-Loop Gain & Phase

Figure 29. Closed-Loop Gain vs. Figure 32. PSRR vs. Frequency, Figure 35. Short Circuit Current vs. Figure 30. CMRR vs. Frequency, Figure 33. OP291 Slew Rate vs. Figure 36. Channel Separation, Figure 31. CMRR vs. Temperature, Figure 34. OP491 Slew Rate vs.

4 PARTS

Figure 37. Maximum Output Swing

Figure 38. Maximum Output Swing Figure 41. Input Offset Current vs. Figure 44. Open-Loop Gain & Phase Figure 39. Input Offset Voltage vs. Figure 42. Input Bias Current vs. Figure 45. Open-Loop Gain vs. Figure 40. Input Bias Current vs. Figure 43. Output Voltage Swing vs. Figure 46. Closed-Loop Gain vs.

Figure 47. CMRR vs. Frequency, Figure 50. OP291/OP491 PSRR vs. Figure 48. CMRR vs. Temperature, Figure 51. Slew Rate vs. Figure 49. PSRR vs. Frequency, Figure 52. Output Impedance vs. Figure 54. Large Signal Transient Figure 53. Large Signal Transient

2.5 V references require at least a minimum operating supply

ture coefficient. Lower tempco resistors are recommended. Figure 61. A +2.5 V Reference that Operates on a Single generate a digitally controlled voltage with a wide output range. Figure 62. +5 V Only, 12-Bit DAC Swings Rail-to-Rail amplifies the output signal to provide a rail-to-rail output swing. adjusted by altering the value of the resistors. Figure 63. A High-Side Load Current Monitor

60 Hz power line interference in portable patient monitoring

Figure 66. A +3 V Single-Supply, 50 Hz/60 Hz Active Notch matching of the capacitors and resistors in the twin-T section. tors produces satisfactory results. be configured with a pair of OP291s as illustrated in Figure 67. above 0 V, the output of amplifier A1 follows the input signal. signal is below 0 V, the output voltage of A1 is forced to 0 V. rectified version of the input signal is available at V OUTB. Figure 67. Single-Supply Half-Wave and Full-Wave

REV. 0–18– * OP491 SPICE Macro-model Rev. A, 5/94 * ARG/ADI * Copyright 1994 by Analog Devices * Refer to “README.DOC” file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * Node assignments * noninverting input * inverting input * positive supply * negative supply * output .SUBCKT OP491 1 2 99 50 45 * INPUT STAGE I1 99 7 8.06E-6 Q 1 647 Q P Q 2 537 Q P D1 3 99 DX D2 4 99 DX D 3 34D X D 4 43D X R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) –0.08E-3 1 IOS 3 4 50E-12 GB1 3 98 (21,98) 50E-9 GB2 4 98 (21,98) 50E-9 CIN 1 2 1E-12 * 1ST GAIN STAGE EREF 98 0 (39,0) 1 G1 98 9 (6,5) 31.667E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) –0.52 1 EC2 11 50 POLY(1) (39,50) –0.52 1 D5 9 10 DX D6 11 9 DX * 2ND GAIN STAGE AND DOMINANT POLE AT 1.25 Hz G2 98 12 (9,39) 8E-6 R8 12 98 276.311E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * COMMON-MODE STAGE ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 10 * POLE AT 2.5 MHz G3 98 18 (12,39) 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * BIAS CURRENT-VS-COMMON-MODE VOLTAGE EP 97 0 (99,0) 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 (15,17) 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 (20,0) 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 (POLY(1) (99,98) -0.765 1 * POLE AT 100 MHz G6 98 40 (18,39) 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * OUTPUT STAGE RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 (99,40) 24E-3 G8 50 45 (40,50) 24E-3 G9 98 60 (45,40) 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=66.667) .ENDS

REV. 0 –19– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Narrow-Body SO (S Suffix) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0040 (0.10) 0.1968 (5.00) 0.1890 (4.80) 14-Lead Narrow-Body SO (S Suffix) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 14 8 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) 0.3444 (8.75) 0.3367 (8.55) 0.0098 (0.25) 0.0040 (0.10) 8-Lead Epoxy DIP (P Suffix) PIN 1 0.280 (7.11) 0.240 (6.10) SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 14-Lead Epoxy DIP (P Suffix) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.795 (20.19) 0.725 (18.42) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC PIN 1 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 814 14-Lead TSSOP (RU Suffix) PIN 1 (6.40) (0.65) 0.043 0.0040 (0.10) 0.1968 (5.00) (0.13) 0.005 (1.10) 0.026 0.173 (4.40)

0.251 COPLANARITY

(0.076) MAX 0.003

PRINTED IN U.S.A. C1970–10–10/94 –20–