OP467ARC/883C

OP467_07 AD | Alldatasheet

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Technical content

Rev. F | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

5/07—Rev. E to Rev. F 3/04—Rev. D to Rev. E 4/01—Rev. C to Rev. D

Rev. F | Page 3 of 20 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

@ VS = ±15.0 V , TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 0.2 0.5 mV −40°C ≤ TA ≤ +85°C 1 mV Input Bias Current IB VCM = 0 V 150 600 nA VCM = 0 V, −40°C ≤ TA ≤ +85°C 150 700 nA Input Offset Current IOS VCM = 0 V 10 100 nA VCM = 0 V, −40°C ≤ TA ≤ +85°C 10 150 nA Common-Mode Rejection CMR VCM = ±12 V 80 90 dB CMR VCM = ±12 V, −40°C ≤ TA ≤ +85°C 80 88 dB Large Signal Voltage Gain AVO RL = 2 kΩ 83 86 dB RL = 2 kΩ, −40°C ≤ TA ≤ +85°C 77.5 dB Offset Voltage Drift ΔVOS/ΔT 3.5 μV/°C Bias Current Drift ΔIB/ΔT 0.2 pA/°C Long-Term Offset Voltage Drift1 ΔVOS/ΔT 750 μV OUTPUT CHARACTERISTICS Output Voltage Swing VO RL = 2 kΩ ±13.0 ±13.5 V POWER SUPPLY2 Power Supply Rejection Ratio PSRR ±4.5 V ≤ VS ≤ ±18 V 96 120 dB −40°C ≤ TA ≤ +85°C 86 115 dB Supply Current ISY VO = 0 V 8 10 mA VO = 0 V, −40°C ≤ TA ≤ +85°C 13 mA Supply Voltage Range VS ±4.5 ±18 V DYNAMIC PERFORMANCE Gain Bandwidth Product GBP AV = +1, CL = 30 pF 28 MHz Slew Rate SR VIN = 10 V step, RL = 2 kΩ, CL = 30 pF AV = +1 125 170 V/μs AV = −1 350 V/μs Full-Power Bandwidth BWρ VIN = 10 V step 2.7 MHz Settling Time tS To 0.01%, VIN = 10 V step 200 ns Phase Margin θ0 45 Degrees Input Capacitance Common Mode 2.0 pF Differential 1.0 pF NOISE PERFORMANCE Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 0.15 μV p-p Voltage Noise Density eN f = 1 kHz 6 nV/√Hz Current Noise Density iN f = 1 kHz 0.8 pA/√Hz 1 Long-term offset voltage drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at 125°C, with an LTPD of 1.3. 2 For proper operation, the positive supply must be sequenced ON before the negative supply.

Rev. F | Page 4 of 20 @ VS = ±5.0 V , TA = 25°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 0.3 0.5 mV −40°C ≤ TA ≤ +85°C 1 mV Input Bias Current IB VCM = 0 V 125 600 nA VCM = 0 V, −40°C ≤ TA ≤ +85°C 150 700 nA Input Offset Current IOS VCM = 0 V 20 100 nA VCM = 0 V, −40°C ≤ TA ≤ +85°C 150 nA Common-Mode Rejection CMR VCM = ±2.0 V 76 85 dB CMR VCM = ±2.0 V, −40°C ≤ TA ≤ +85°C 76 80 dB Large Signal Voltage Gain AVO RL = 2 kΩ 80 83 dB RL = 2 kΩ, −40°C ≤ TA ≤ +85°C 74 dB Offset Voltage Drift ΔVOS/ΔT 3.5 μV/°C Bias Current Drift ΔIB/ΔT 0.2 pA/°C OUTPUT CHARACTERISTICS Output Voltage Swing VO RL = 2 kΩ ±3.0 ±3.5 V POWER SUPPLY Power Supply Rejection Ratio PSRR ±4.5 V ≤ VS ≤ ±5.5 V 92 107 dB −40°C ≤ TA ≤ +85°C 83 105 dB Supply Current ISY VO = 0 V 8 10 mA VO = 0 V, −40°C ≤ TA ≤ +85°C 12 mA DYNAMIC PERFORMANCE Gain Bandwidth Product GBP AV = +1 22 MHz Slew Rate SR VIN = 5 V step, RL = 2 kΩ, CL = 39 pF AV = +1 90 V/μs AV = −1 90 V/μs Full-Power Bandwidth BWρ VIN = 5 V step 2.5 MHz Settling Time tS To 0.01%, VIN = 5 V step 280 ns Phase Margin θ0 45 Degrees NOISE PERFORMANCE Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 0.15 μV p-p Voltage Noise Density eN f = 1 kHz 7 nV/√Hz Current Noise Density iN f = 1 kHz 0.8 pA/√Hz

Rev. F | Page 5 of 20 WAFER TEST LIMITS1 @ VS = ±15.0 V , TA = 25°C, unless otherwise noted. Table 3. Parameter Symbol Conditions Limit Unit Offset Voltage VOS ±0.5 mV max Input Bias Current IB VCM = 0 V 600 nA max Input Offset Current IOS VCM = 0 V 100 nA max Input Voltage Range2 ±12 V min/max Common-Mode Rejection Ratio CMRR VCM = ±12 V 80 dB min Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 96 dB min Large Signal Voltage Gain AVO RL = 2 kΩ 83 dB min Output Voltage Range VO RL = 2 kΩ ±13.0 V min Supply Current ISY VO = 0 V, RL = ∞ 10 mA max 1 Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 2 Guaranteed by CMR test.

1 Absolute maximum ratings apply to both DICE and packaged parts, unless

2 For proper operation, the positive supply must be sequenced ON before the

3 For supply voltages less than ±18 V, the absolute maximum input voltage is

equal to the supply voltage. soldered in a circuit board for surface-mount packages. soldered in circuit board for the SOIC package. Figure 5. 0.111 Inch × 0.100 Inch DIE Size, 11,100 sq. mils,

ground or to the supplies may destroy the device. maximum junction temperature. TJ and TA are junction and ambient temperatures, respectively. PD is device internal power dissipation. θJA is the packaged device thermal resistance given in the data sheet. feedback resistor with noninverting input tied to the ground plain. performance, follow the high frequency layout technique. ground, avoid running any traces on this layer. with stray capacitance, forms a high frequency resonance circuit. (ESR) increases with frequency making them less effective. very close to the device pin, further reducing the stray inductance. operation if it is not selected properly. Figure 40. Recommended Power Supply Bypass them, which also improves the channel separation significantly.

Figure 45. Instrumentation Amplifier Settling Time to 0.01% for a

10 V Step Input (Negative Slope)

Figure 46. Instrumentation Amplifier Settling Time to 0.01% for a

10 V Step Input (Positive Slope)

Figure 47. Settling Time Measurement Circuit

2 MHz BIQUAD BAND-PASS FILTER

Figure 49. When the bandwidth of the op of the three op amps causes the loop to oscillate. as with any other high speed circuit. alter the circuit performance, or worse, cause oscillation. Figure 48. 2 MHz Biquad Filter Figure 49. Biquad Filter Response

Rev. F | Page 17 of 20 OP467 SPICE MARCO-MODEL * Node assignments noninverting input inverting input positive supply n e g a t i v e s u p p l y output . SUBCKT OP467 1 2 99 50 27 * INPUT STAGE I1 4 5 10E–3 CIN 1 2 1E–12 IOS 1 2 5E–9 Q1 5 2 8 QN Q2 6 7 9 QN R3 99 5 185 . 681 R4 99 6 185 . 681 R5 8 4 180 . 508 R6 9 4 180 . 508 EOS 7 1 POLY (1) (14,20) 50E–6 1 EREF 98 0 (20,0) 1 * GAIN STAGE AND DOMINANT POLE AT 1.5 kHz R7 10 98 3 . 714E6 C2 10 98 28 . 571E–12 G1 98 10 (5,6) 5 . 386E–3 V1 99 11 1 . 6 V2 12 50 1 . 6 D1 10 11 DX D2 12 10 DX RC 10 28 1 . 4E3 CC 28 27 12E–12 * COMMON-MODE STAGE WITH ZERO AT 1.26 kHz ECM 13 98 POLY (2) (1, 20) (2,20) 0 0. 5 0 . 5 R8 13 14 1E6 R9 14 98 25 . 119 C3 13 14 126 . 721E–12 *POLE AT 400E6 R10 15 98 1E6 C4 15 98 0 . 398E–15 G2 98 15 (10,20) 1E–6 * OUTPUT STAGE ISY 99 50 –8 . 183E–3 RMP1 99 20 96 . 429E3 RMP2 20 50 96 . 429E3 RO1 99 26 200 RO2 26 50 200 L1 26 27 1E–7 GO1 26 99 (99,15) 5E–3 GO2 50 26 (15,50) 5E–3 G4 23 50 (15,26) 5E–3 G5 24 50 (26,15) 5E–3 V3 21 26 50 V4 26 22 50 D3 15 21 DX D4 22 15 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * MODELS USED . MODEL QN NPN (BF=33.333E3) . MODEL DX D . MODEL DY D (BV=50) . ENDS OP467