OP42ARC

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| ANALOG High Speed, Fast Settling FEATURES 58V/us slew rate and is internally compensated for unity-gain Fast operation. OP-42 speedis achieved with a supply current of less © SlOW Rate nresnsenssosesnnneerntenneneeieenenntieenee 5OV/uS Min than 6mA. Unity-gain stability, a wide full-power bandwidth of * Settling-Time (0.01%) weresssiccseresseesenssseeseneee 118 Max 900KHz, and a fast settling-time of 800nsto 0.01% make the OP- Precise Equal attention was given to both speed and precision in the OP- © Offset Voltage oo... 750RV Max — the need for external nulling in many circuits. The OP-42's ° PIN CONNECTIONS Excellent Radiation Hardness Available in Die Form 32 ; Ne 22222 8 ORDERING INFORMATION ' EN) 3} 3} NULL 1 Te TT nc. [a] [is] n.c. Terre PACKAGE OPERATING w Ts] “ Vog MAX CERDIP PLASTIC SO LCC TEMPERATURE ne. fi] [a] ne. aN? Sour (mV) 70-99 &-PIN &PIN &-PIN 20-CONTACT RANGE +P] our 4.0 OP42AJ* OPAZAZ* — — = OPA2ARC/B3 MIL we [a] [ref we. “ms Smee

0.75 OP42EJ OP4zEZ - - - IND Eifel Ife v- (ease)

15 OP42FJ OP42FZ - - - IND gigig

50 - ~__opaeap opazcs —- XiND e223 0-99 = Fos dovicos procsesedin tal compiance to MuS1D-200 aualeeeate ran (u-Suftix) Jevices processed in total compliance to MIL-STD-883, add/883 after part 20-CONTACT LCC number. Consult factory for 883 data sheet. RC-Sufti t Burn-in is available on commercial and industrial temperature range parts in (RC-Suffix) in 8-PIN CERDIP cerdip, plastic dip, and TO-can packages. nu Ff [a] we. Suffix) GENERAL DESCRIPTION “St By EPOXY MINI-DIP on [} our (P-Suffix) The OP-42 is a fast precision JFET-input operational amplifier. vf] fe] wow Similar in speed to the OP-17, the OP-42 offers a symmetric &PINSO (S-Suffix) SIMPLIFIED SCHEMATIC ov a ° -No tet a ——ov nou not -1-

common-mode rejection of 88dB minimum over a #11V input Operating Temperature Range voltage range is exceptional for a high-speed amplifier. High OP42A (J, Z) vosesscssseesersnsesesessertesssnreecerseeee —B5°C to +125°C CMR combined with a minimum 500V/mV gain into 10kQ load OP42E, F (J, Z) csvcsesssonsseesscesseescnsssnsecessmeeeeee “25°C to +85°C ensure excellent linearity in both noninverting and inverting gain OPA2G oescsseeccsssseeescnssesesesnsneesesseesesssnsesenente 40°C to +85°C configurations. The low input bias and offset currents provided Junction Temperature «0... eeeeseeees “65°C to +175°C sample and hold circuits, peak detectors, and log amplifiers. Excellent radiation hardness characteristics make the OP-42 oT, 0Oor aoa ideal for military and aerospace applications. PACKAGE TYPE Oia(NOTE 3) %\\o UNITS The OP-42 conforms to the standard 741 pinout with nullingto =§ TO99@) SB V-. The OP-42 upgrades the performance of circuits using the ®PinHermoticDIP(@) 1486 CW D544, AD611, AD711, and LF400 by direct replacement. In 8-Pin Plastic DIP(P)__ 08M circuits without nulling, the OP-42 offers an upgrade for designs 20-ContactLOC (ACTS) 9B 8B using the OP-16, OP-17, LT1022, LT1056, and HA2510. 2 Pin$O(S) SB NOTES: 1. Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. ABSOLUTE MAXIMUM RATINGS (Note 1) 2. For supply voltages less than =20V, the absolute maximum input voltage is ELECTRICAL CHARACTERISTICS at V, = =15V, T, = +25°C, unless otherwise noted. OP-42E OP-42F OP-42G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN. TYP MAX MIN TYP MAX UNITS Offset Voltage Vos - 03 075 - 04 15 - 15 50 mv OiisetVotage Vos Input Bias Current Ip Vow = OV 7, =25°C 80 © 200 = 430 250 = 130 250 pA Anput Bias Current ta Vom OV TR Input Offset Current los Vey = OV 7, =25°C = 4 40 = Cr) - 6 60 pA . Not 12. 125 12.5 Input Voltage Range ive (Note 1) en " - a1 - ced - v EE Common-Mode CMR VayesttV a 80 92 - so 92 a8 Rejection ow Power-Supply Vg = 210V _ _ 5 _ R Rejection Ratio PSR io'az0v s # we 8 80 VN R= 10k 500 900 - 500 900 - 500 900 \\arge Sina! Ay Re=aKe YorstY 00 260 200 26002 ~ 200 2600 - ~—Vimv ‘ottage Gain Reta 1" 100170 ~ 100 © 170 - 100 170 - Output Voltage ne! , +128 125 1125 ‘swing Vo R= tke a5 05 - a5 715 - a5 18 - v Short-Circuit Output Shorted . +33 +33 +9 Current Limit 'se to Ground 320 2g “80 70 2g 280 320 og 70 ms No Load Supply Current 1 - 51 60 - 81 65 - 51 65 mA sy Vo = 0V Slew Rate sR 5058 - 4050 = 40. 50 - Vius Full-Power Bandvetth Bw, (Note 2) 79 900 800800 - 600 800 - kHz Gain-Bandwidth rocuet GBW fg = 10kHz - 10 - - 10 - - 0 = MHz Settling -Time , twass 0.01% - 08 10 - 09 12 - 09 12 us Sh Overload Recovery _ _ _ - vine ton - 700 - 700 700 ns Phase Margin 4 db Gain - 47 - - 47 - - 47 = degrees Phase Margin OSB GaN ES Gain Margin Areo nena edad - Fy - - 9 - - 9 - “B Phase Sri Capacitive Load Unity-Gain Stable _ _ Drive Capability oo (Note 4) too 300 a too 800 too PF -2- I

ELECTRICAL CHARACTERISTICS at V, = =15V, T, = +25°C, unless otherwise noted. Continued OP-42E OP-42F OP-42G PARAMETER SYMBOL CONDITIONS MIN. TYP MAX MIN. TYP MAX MIN TYP MAX — UNITS Differential Input impedance Zn - 10'%I[6 - = 10" 16 - ~ 10°76 - — QlipF Open-Loop Output Resistance Fo ed - — ee ~ a Voltage Noise Crop O-tHZt0 10Hz - 2 - - 2 ~ - 2 = Wy 1p = 10Hz — 38 = — 38 - - 6 - Voltage Noise fo = 100Hz - 6 - - 16 - - 6 - a Density % f= tkHz - 13 - - 13 - - 43 - wWWez Current Noise Density iy fy = thHz - 0.007 - = 0.007 - = 0.007 - pAWHE External Vg . ‘Trim Range Root = 20k2 - 4 - - ‘ - - 4 - mv Long-Term Yoni - 5 - - 5 - = 5 = _pVimonth Supply Voltage Range Vg 28215220 28215220 28 215 220 v NOTES: 3. Settling-time is sample tested for A and E grades. Test circuit is shown in 1. Guaranteed by CMR test. Figure 4, Sottling-time for F grade is guaranteed but not tested. 2. Guaranteed by slow-rate test and formula BW, = SR/(2n10Vpeq,)- 4. Guaranteed but not tested. ELECTRICAL CHARACTERISTICS at V, = +15V, T, = +25°C, unless otherwise noted. OP-42A PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Ofset Voltage Vos = 03 1.0 mv Input Bias Current le Voy = OV T,= 28°C - 80 200 pA Input Offset Current los Vow = OV )= 25°C = 4 40 pA Input Voltage Range IVR (Note 1) att Ne - v Common-Mode ze - B Rejection coMR Vom=2t1¥ 86 96 d Power-Supply i Vg = #10V _ ° 40 uN Rejection Ratio PSAR to220V " i R, = 10ka 500 ‘900 = eae re No R=2Ka Yossiey 200 260 - Vimy fokege Gain Rota = 100 170 - Output Voltage . W125 _ ‘song Vo R= 1ka a5 ved v ‘Short-Circuit Output Shorted +33 mA Current Limit 'se to Ground 320 -28 360 No Load ‘Supply Current 1 Me - 64 60 mA SY Vo = 0V — Slew Rate SR 45 52 = Vins Full-Power - kHz Bandwiath Bw, Mote 2) 700 850 Gain-Bandwicth . - 1 - MHz Product cew fo = 10kHz 0 10V Step 0.01% . ; Settling -Time , biden 08 1.0 # ‘Overload Recovery _ Time tor - 700 ns Phase Margin % Odb Gain - 47 - degrees

ELECTRICAL CHARACTERISTICS at V, = +15V, T, = 25°C, unless otherwise noted. Continued OP-42A PARAMETER SYMBOL CONDITIONS MIN Tye MAX UNITS 180° Open-Loop Gain Margin Aveo Phase Shift - 9 - a8 Capacitive Load Unity-Gain Stable Drive Capability CG (Note 4) 100 300 - pF Differential Input 42 Impedance Zn - 10'7|I6 - QtIpF Open-Loop Output Resistance Ro 7 50 7 2 Voltage Noise en pp 0.1Hz to 10Hz - 2 - ery fo = 10Hz = 38 - Voltage Noise fg = 100H2 - 16 - j Density nm fo = 1kHz - 43 - avis fy = 10kHz - 12 - ‘Current Noise A Density i, fo = 1kHz - 0.007 - pAK/Hz External V, Trim Range Foot = 20ka - 4 - mv Long-Term - 5 = a¥/month Vos Drift ‘Supply Voltage Range Vs 28 215 220 Vv NOTES: ‘3. Settling-time is sample tested for A and E grades. Test circuit is shown in 1. Guaranteed by CMR test. Figure 4. Settling-time for F grade is guaranteed but not tested. 2. Guaranteed by slew-rate test and formula BW, = SA/(2x10V pe q4)- 4, Guaranteed but not tested. ELECTRICAL CHARACTERISTICS at V, = +15V, -25°C < T, = 85°C for E/F grades, and -40°C = T, = +85°C for G grade, unless otherwise noted. OP.42E OP-42F OP-42G PARAMETER SYMBOL CONDITIONS ‘MIN TYP MAX MIN TYP MAX MIN TYP MAX ‘UNITS Offset Voltage Vo: s. - 04 1.2 - 06 25 = 2.0 6.0 mv Oftset Voltage Temperature TCVg5 - 4 10 - 8 - - 8 - avec Coefficient Input Bias Current A (Note 1) - 06 12 - 06 20 - 06 20 nA 412.5 412.5 412.5 Input Voltage Range = VR. (Note 2) ao - es at eo - v Common-Mode Rejection cMR Vom =211V 86 96 = 80 94 - 80 94 - dB Power-Supply V, = 210V . _ . Rejection Ratio PSAR to220V > * s .* wn Large-Signal RL = 10kQ (Note 1) 200 =500 = 200 500 - 200 500 - vimv Voltage Gain Avo R= 2kQ Yo =210V 100 «(160 = 100 160 = 100 160 - Output Voltage _ 412.3 412.3 _ 412.3 _ Swing Vo RL =2ka 210 5 - ano 5 a0 73 v Short-Circuit Output Shorted _ Curcent Limit 'sc to Ground nae 8 ~ 360 38 260 ma No Load ‘Supply Current 4, - 564 6.0 - 51 65 - 51 65 mA sy Vo = 0V Slew Rate SR R, = 2ko 45 (57 - 40 80 40 50 - vis Capacitive Load Unity-Gain Stable _ _ 1 _ a Drive Capability c (Note 3) 100 250 100 250 j00 250 pl NOTES: 2. Guaranteed by CMR test. 1.T, = 85°C for E/F/G Grades; T, = 125°C for A grade. 3. Guaranteed but not tested. -4-

ELECTRICAL CHARACTERISTICS at V, = +15V, -55°C = T, s 125°C for A grade, unless otherwise noted. OP-42A\\ PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Offset Voltage Vos = 08 2.0 mv Offset Voltage Temperature TCVo5 - 4 10 wre Coefficient Input Bias Current ' (Note 1) - 6 20 nA Input Offset Current los (Note 1) = 02 1.0 nA Input Voltage Range IvR (Note 2) at we - v ‘Common-Mode oleston cur Vow=2ttV 80 94 - 4B Power-Supply Vg =210V . Rejection Ratio PEAR to 220V 10 80 wn Large-Signal R= 10kQ (Note 1) 160 360 - Voltage Gain No RL =2k@ Vo =210V 80 410 - vin Output Voltage . +123 - ‘owing Vo A, = 2k 211.0 ie v Shori-Circult ‘Output Shorted Current Limit 'sc to Ground 36 - 260 ma No Load Supply Current ley vec ov - 5: 60 mA Siew Rate SR R, = 2k 40 52 = Vins Capacitive Load Unity-Gain Stable - 7 Drive Capability oO (Note 3) 100 280 p NOTES: q1 y = 85°C for E/F Grades; a = 125°C for A grade. 2. Guaranteed by CMA test. 3. Guaranteed but not tested.

— — 1. OFFSET VOLTAGE NULL Un fee all Ls] 2. INVERTING INPUT Eee | Rigel gl 3, NONINVERTING INPUT beeline (ees | a 4. NEGATIVE SUPPLY Stel Sas 5. OFFSET VOLTAGE NULL (ee FS" | arn aS NE = |= eS 6. AMPLIFIER OUTPUT =| Si es a fe f= Sena ib 7. POSITIVE SUPPLY Cee — ep rr ra lel Cor eee 3: DIE SIZE 0.098 0.070 inch, 6860 sq. mils (2.49 x 1.78 mm, 4.43 sq. mm) WAFER TEST LIMITS at Vs = +15V, Tj = 25°C, unless otherwise noted. OP-42N PARAMETER SYMBOL CONDITIONS LuiMIT UNITS Offset Voltage Vos 1s mv MAX Input Bias Current ly Vom = OV 250 pA MAX Input Offset Current los Vom = OV 50 pA MAX Input Voltage Range IVR (Note 1) =n V MIN Common-Mode Rejection CMR _ Vom =211V, _ 80 __ 98 MIN Power-Supply a . Rejection Ratio PSRR Vs = $10V to +20V_ 50 piv MAX , R= 10k0 500 Large-Sianel Avo Ay = 2k0 200 Wmv MIN oltage Gein Rp=1kn 100 Output Voltage Swing Yo Aya 1k 18 v Min Short-Circuit Output Shorted 4 #20/+ Current Limit 'so to Ground 0/60 mA MIN/MAX No Load ‘Supply Current Isy Vo=0v 65 mA MAX Slew Rate SR 40 Vins MIN Capacitive Load Unity-Gain Stable Drive Capability co (Note 2) 0 pF MIN NOTES: 4. Guaranteed by CMR test, 2. Guaranteed but not tested. Electrical tests are pertormed at wafer probe to the limits shown. Due to varlations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing BURN-IN CIRCUIT soko 43V0 )-> “ 10k. aw od -6-

TYPICAL PERFORMANCE CHARACTERISTICS OPEN-LOOP GAIN, PHASE COMMON-MODE POWER-SUPPLY REJECTION vs FREQUENCY REJECTION vs FREQUENCY vs FREQUENCY [TTT Tq = [1.4 [=| nary 100 1k = 10k 100k 1M 10M «(100M ary 100 tk 10k 100k 1M “0 100 tk 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) SLEW RATE vs SLEW RATE vs DIFFERENTIAL SLEW RATE vs TEMPERATURE INPUT VOLTAGE CAPACITIVE LOAD a & 30 zo = eto OPT Cee po ee eee Zen CoS * y ie cee YT EES ‘Spy eo 250 es 80 TSO es "902 0a 06 0a 10 ary 100 200 300 “00 SETTLING-TIME DISTORTION CLOSED-LOOP GAIN is STEP SIZE vs FREQUENCY vs FREQUENCY * 7 . L1J T SSS SS 7 ,, rd Sheer yee “feces } a oe ey ae ie = i / “TL pee a / ' 2 40 eT PTA) & Srey = =§ apt tae NT PCO NC NC oP SST een Es Sosa op xem TOT ce ee = al os | SECA AG], Retico io

TYPICAL PERFORMANCE CHARACTERISTICS CLOSED-LOOP SMALL-SIGNAL OUTPUT IMPEDANCE MAXIMUM OUTPUT SWING OVERSHOOT vs vs FREQUENCY vs FREQUENCY LOAD CAPACITANCE . . ‘fest fff sl =6-f&ee, to iS my TL pe 8 = || 1 5 50 Loe Pata EA i |e i 8 LH CLS TITIAN =” =-Z == SFY eee Nu * es Lssea lll TIS ; SS OUTPUT SWING vs SUPPLY CURRENT SUPPLY CURRENT vs LOAD RESISTANCE vs TEMPERATURE SUPPLY VOLTAGE = To cee Ae [Sem LT ge Ee HEE PCMAG) fs EEEEEEER eFC eb

7 CESSES EPCCOBSRO

i. : E 7 NATIT F a HH a Loe TN SEPP See TYPICAL DISTRIBUTION OF TYPICAL DISTRIBUTION OFFSET VOLTAGE INPUT OFFSET VOLTAGE OF TCVosg WARM-UP DRIFT oer “sy Tes e Le Ab py 3 “HET SE) EF PENSE i ‘ = "ARE SET Ho) EAE {oS doe LS -8-

TYPICAL PERFORMANCE CHARACTERISTICS BIAS CURRENT vs BIAS CURRENT vs BIAS CURRENT JUNCTION TEMPERATURE COMMON-MODE VOLTAGE WARM-UP DRIFT Ee, LE SSS) SSS ESE S| ——— fy ee ee OFFSET CURRENT vs OPEN-LOOP GAIN vs ouTPuT CURRENT vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE ‘eo ON TEMPER m0 So=-=——_ ann “ety 2,,.[/]/ |] tj iw 2° SS Pp AY eH EN CCP —— e mM Be He EFPEPPES) “DEPT Cr JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) VOLTAGE NOISE DENSITY vs FREQUENCY ~ PUTT Te] ETA TIC TCT F us| | FA RST RL : eeu ae So UN

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FIGURE 4: Settling-Time Test Fixture 16209 sv ° ae o OUTPUT one (ro score x RL aX ZS 0% b anare ‘tk 1M Ao V uF Onn W ‘oka + | = kn we fig (TERNAL) oan, Vv aN anaes $15K0 SCHOTTKY DiopEs DED Zz ARE NEWLETT-PACKARD H5062-2095 {C1 Is COMLINEAR CLEZ00K1 - é {G25 Pal OPsiey iv FIGURE 5: OP-42 Settling-Characteristics optimal settling speed. Compensation is achieved with ca- pacitor C in Figure 6. C must be adjusted to account for the

7 DAC’s output capacitance, the op amp’s input capacitance,

i positive EDGE and any stray capacitance at the inputs. With a bipolar DAC, i an additional shunt resistor may be used to optimize — NX 0.01% ERROR BAND response. This technique is described in PMI's application BR note AN-24. a a FIGURE 6: DAC Output Amplifier Circuit ° tus tue 254s c ‘ 200 H PMrs4e en H ee 0.01% ERROR BAND: } \\ V H Highest speed is achieved using bipolar DACs such as PMI's. ° ™ aus tue DAC-08, DAC-10 or DAC-312. The output capacitances of these converters are up to an order of magnitude lower than their CMOS counterparts, resulting in substantially faster DAC OUTPUT AMPLIFIER settling-times. The high output impedance of bipolar DACs . . allows the output amplifier to operate in a true current-to- gre cre 's an excellent choice fore pac output ample voltage mode, with a noise gain of unity, thereby retaining the ' b 4 igh sp i" nd fas} for f he ale chanous i stout amplifier's full bandwidth. Offset voltage has minimal effect ions between codes, even for full-scale changes in outpu on linearity with bipolar converters level. The DAC output capacitance appears at the opera- : tional amplifier inputs, and must be compensated to ensure CMOS digital-to-analog converters have higher output ca- pacitances and lower output resistances than bipolar DACs. -11-

This results in slower settling-times, higher sensitivity to 0.1uF capacitor. Compensation for the OP-42's input capac- offset voltages and a reduction in the output amplifiers itance is provided by Cc. The circuit may be operated at any bandwidth. These trade-offs must be balanced against the gain, in the usual op amp configurations. CMOS DAC's advantages in terms of interfacing capability, power dissipation, accuracy levels and cost. Using the inter- : Hi r it : ~ fer nal feedback resistor which is present on most CMOS con- FIGURE 8: gh-Current Output Buffer — verters, the gain applied to offset voltage varies between 4/3 v8 | and 2, depending upon output code. Contributions to linear- © cae | ity error will be as much as 2/3Vog. In a 10-volt 12-bit system, | this may add up to an additional 1/5LSB DNL with the | OP-42E. Amplifier bandwidth is reduced by the same gain factor SY applied to offset voltage, however the OP-42’s 10MHz gain- OF bandwidth product results in no reduction of the CMOS con- anette 1 verter’s multiplying bandwidth Si saa Individual DAC data-sheets should be consulted for more Vin © Y nt complete descriptions of the converters and their circuit © Your applications. b ae ‘ka 02 FIGURE 7: DAC Output Amplifier Response (PM-7545 DAC) 5 Ej 2Ne910 Ls \\ / ) . 7 5 om ro our ime Re -Bv Pr rset Bot oe yea = 1+ BB oF RY AND R2 ARE 1-60, SEE TEXT. DRIVING A HIGH-SPEED ADC FIGURE 9: Output Buffer Large-Signal Response The OP-42's open-loop output resistance is approximately 502. When feedback is applied around the amplifier, output Lsv] resistance decreases in proportion to open-loop gain divided by closed-loop gain (Ayoi/Avc.). Output impedance in- creases as open-loop gain rolls-off with frequency. High- ' speed analog-to-digital converters require low source impe- dances at high frequency. Output impedance at 1MHz is typically 50 for an OP-42 operating at unity-gain. If lower —— output impedances are required, an output buffer may be e placed at the output of the OP-42. Aye =*8 RL 750 HIGH-CURRENT OUTPUT BUFFER The circuit in Figure 8 shows a high-current output stage for the OP-42. Output current is limited by R1 and R2. For good tracking between the output transistors Q1, Q2 and their DRIVING CAPACITIVE LOADS biasing diodes D1 and D2, thermal contact must be maine Best performance will always be achieved by minimizing tained between the transistor and its associated diode. If input and load capacitances around any high-speed ampli- good thermal contact is not maintained, R1 and R2 must be fier. However, the OP-42 is guaranteed capable of driving a increased to 5-60 in orderto prevent thermal runaway. Using 4999 capacitive load over its full operating temperature 52 resistors, the circuit easily drives a 750 load (Figure 9). range while operating at any gain including unity. Typically, Output resistance is decreased and heavier loads may be an OP-42 will drive more than 250pF at any temperature. driven by decreasing A1 and Re Supply decoupling does affect capacitive load driving ability. Base current and biasing for Q1 and Q2 are provided by two Extra care should be given to ensure good decoupling when current sources, the MAT-02 and the JFET. The 2k potenti- driving capacitive loads, and a larger decoupling capacitor ometer in the JFET current source should be trimmed for between 1uF and 10uF should be placed in parallel with the optimum transient performance. The case of the MAT-02 usual decoupling capacitor on each supply. should be connected to V-, and decoupled to ground with a -12-

Large capacitive loads may be driven utilizing the circuit FIGURE 10: Compensation for Large Capacitive Loads shown in Figure 10. R1 and C1 introduce a small amount of feedforward compensation around the amplifier to counter- ve act the phase lag induced by the output impedance and load ? uF capacitance. At DC and low frequencies, R1 is contained an within the feedback loop. At higher frequencies, feedforward or compensation becomes increasingly dominant, and R1's ri effect on output impedance will become more noticeable. Vin © Rt When driving very large capacitances, slew-rate will be von © Your limited by the short-circuit current limit. Although the un- a loaded slew-rate is insensitive to variations in temperature, ka tor == 2 Saka the output current limit has a negative temperature coeffi- OF cient, and is asymmetrical with regards to sourcing and sink- an ing current. Therefore, slew-rate into excessive capacities V will decrease with increasing temperature, and will lose a symmetry. 200F ay COMPUTER SIMULATIONS Ro an Many electronic design and analysis programs include mod- ae els for op amps which calculate AC performance from the Vv location of poles and zeros. As an aid to designers utilizing such a program, major poles and zeros of the OP-42 are listed below. Their location will vary slightly between production AUTOZEROING OFFSET VOLTAGE lots. Typically, they will be within 215% of the frequency Figure 11 describes a circuit for automatic offset voltage and listed. Use of this data will enable the designer to evaluate drift correction. The OP-41 is used in a servo loop to force the gross circuit performance quickly, but should not supplant OP-42 output equal to the OP-41's offset voltage. Thus, the rigorous characterization of a breadboarded circuit. OP-42's effective input offset is held below 104V (1mV/Ayo. POLES ZEROS = 100) despite any temperature variations. This circuit will be 20Hz 1MHz most advantageous in high-gain applications. oan Feedback is accomplished using the OP-42’s null pins, leav- ing both inputs free for other purposes. In the application FIGURE 11: OP-41 Servo Amplifier Provides Offset Correction pF ox. 11 © 1000 2.0 Meo ot mot on Mo cy Nana Ins 0 wae Ns weoKe, 5000pF 10k Vv Vo ousv < Vv ENABLE © 0x0 ai0 a8 =F: q Vv news gL, ALL LINES HIGH TO ZENO OFFSETS 2na9078 Vv 2nz369 “ev -13-

shown, the OP-42 has seven multiplexed inputs, while the the OP-41 servo amplifier. A charge is developed across Cy eighth input provides a ground reference. Nulling is accomp- to compensate for the OP-42’s offset voltage. When another lished by addressing the grounded channel. This address channel is addressed, J1 turns off, and the correction charge should be held for at least 200us. After this time, the address is maintained across Cy by the OP-41. Droopis exceptionally may be changed to another channel. The MUX-08 ENABLE low — only 1.3uV/s at 25°C. A correction range of more than pin must be high during the entire nulling cycle. During this 4mvV allows nulling of minor system offsets as well as the time, JFET switch J1 turns on, completing feedback around OP-42's offset voltage. -14-