OP3693

OPA3693_07 BURR-BROWN | Alldatasheet

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Technical content

/C0066/C0117/C0114/C0114/C0262/C0066/C0114/C0111/C0119/C0110 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0102/C0114/C0111/C0109 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115

FEATURES

DESCRIPTION

APPLICATIONS

75 Cable/c87

Triple, Ultra-Wideband, Fixed-Gain, VIDEO BUFFER with Disable 650MHz BANDWIDTH +2) The OPA3693 provides an easy to use, broadband, triple, fixed-gain buffer amplifier. Depending on the FIXED GAIN OF or external connections, the internal resistor network OUTPUT VOLTAGE SWING: 4.1V may be used to provide either a fixed gain of ULTRA-HIGH SLEW RATE: 2500V/ µ s video buffer or a gain of or voltage buffer. The 3RD-ORDER INTERCEPT: 40dBm OPA3693 offers a slew rate (2500V/ µ and bandwidth 800MHz) normally associated with a 50MHz) much higher supply current. A new output stage LOW POWER: 130mW/channel architecture delivers high output current with a LOW DISABLED POWER: 0.4mW/channel minimal headroom and crossover distortion. This combination of (ADC) input driver. MULTIPLE LINE VIDEO DISTRIBUTION AMPLIFIER (DA) The OPA3693 13mA/channel supply current is PORTABLE INSTRUMENTS precisely trimmed at +25 This trim, along with a BROADBAND VIDEO LINE DRIVERS low temperature drift, gives lower system power over temperature. System power can be further reduced ADC BUFFERS using the optional disable control pin. Leaving this HIGH-FREQUENCY ACTIVE FILTERS pin open, or holding it HIGH, gives normal operation. If pulled LOW, the OPA3693 supply current drops to less than 130 µ A/channel. This power-saving feature, along with exceptional single +5V operation, make the OPA3693 ideal for portable applications. The OPA3693 is available in an SSOP-16 package. FEATURE SINGLES DUALS TRIPLES Voltage OPA690 OPA2690 OPA3690 Feedback Current OPA691 OPA2691 OPA3691 Feedback Fixed Gain OPA692 OPA3692 Fixed Gain OPA693 >900MHz OPA695 OPA2695 OPA3695 Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) T op□View SSOP 300/c87 300/c87 300/c87 300/c87 300/c87 300/c87 /c45 IN□A /c45 IN□B /c45 IN□C +IN□A DIS□B DIS□C +IN□B +IN□C 9 /c45 VS +VS +VS /c45 VS DIS□A OUT□C OUT□B OUT□A OPA3693 CH□A CH□B CH□C OPA3693 SBOS353 DECEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA, PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER QUANTITY OPA3693IDBQ Rail, OPA3693 SSOP-16 DBQ C to +85 C OP3693 OPA3693IDBQR Tape and Reel, 2500 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com Power Supply 6.5V DC Internal Power Dissipation See Thermal Analysis Differential Input Voltage 1.2V Input Common-Mode Voltage Range V S Storage Temperature Range C to +125 C Lead Temperature (soldering, 10s) +300 C Peak +150 C Maximum Junction Temperature, T J Continuous Operation, Long-Term Reliability +140 C Human Body Model (HBM) 1500V ESD Rating Charge Device Model (CDM) 1000V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these and any other conditions beyond those specified is not supported. Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS: V S OPA3693 SBOS353 DECEMBER 2006 Boldface limits are tested at +25 At G IN grounded) and R L 100 Ω unless otherwise noted. OPA3693IDBQ TYP MIN/MAX OVER TEMPERATURE TEST C to C to MIN/ LEVEL PARAMETER CONDITIONS +25 C +25 C (2) +70 C (3) +85 C (3) UNITS MAX (1) AC PERFORMANCE Small-Signal Bandwidth O 1.0V PP G 800 MHz typ C G 650 500 480 470 MHz min B G 650 500 480 470 MHz min B Bandwidth for 0.2dB Gain Flatness V O 1.0V PP 320 120 110 105 MHz min B Peaking at a Gain of V O 1.0V PP 4.3 5.3 5.7 dB max B Large-Signal Bandwidth V O PP 380 MHz typ C Slew Rate V O Step 2500 2200 2100 2000 µ s min B Rise-and-Fall Time V O 0.5V Step 0.6 0.8 0.8 0.9 ns max B V O Step 1.2 1.3 1.3 1.4 ns max B Settling Time to 0.02% V O Step ns typ C Settling Time to 0.1% V O Step ns typ C Harmonic Distortion f 10MHz, V O PP 2nd-Harmonic R L 100 Ω dBc max B R L 500 Ω dBc max B 3rd-Harmonic R L 100 Ω dBc max B R L 500 Ω dBc max B Input Voltage Noise f 1MHz 1.8 2.7 2.9 nV/ Hz max B Noninverting Input Current Noise f 1MHz pA/ Hz max B Inverting Input Current Noise (internal) f 1MHz pA/ Hz max B Differential Gain NTSC, R L 150 Ω 0.03 typ C NTSC, R L 37.5 Ω 0.03 typ C Differential Phase NTSC, R L 150 Ω 0.01 deg typ C NTSC, R L 37.5 Ω 0.1 deg typ C Crosstalk channels driven) f 10MHz dBc typ C DC PERFORMANCE (4) Gain Error G 0.7 typ C G 0.6 1.0 1.1 1.2 max A G R s Ω 0.5 0.9 1.0 1.1 max B Internal R F and R G Maximum 300 341 345 347 Ω max A Minimum 300 264 260 258 Ω min A Input Offset Voltage V CM 0.6 3.5 3.7 4.0 mV max A Average Offset Voltage Drift V CM µ C max B Noninverting Input Bias Current V CM +15 µ A max A Average Noninverting Input Bias Current Drift V CM 170 170 nA/ C max B Inverting Input Bias Current (internal) V CM µ A max A Average Inverting Input Bias Current Drift V CM nA/ C max B (1) Test levels: (A) 100% tested at +25 Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature ambient for +25 C specifications. (3) Junction temperature ambient at low temperature limits; junction temperature ambient +27 C at high temperature limit for over temperature specifications. (4) Current is considered positive out of pin. Submit Documentation Feedback

www.ti.com OPA3693 SBOS353 DECEMBER 2006 ELECTRICAL CHARACTERISTICS: V S (continued) Boldface limits are tested at +25 At G IN grounded) and R L 100 Ω unless otherwise noted. OPA3693IDBQ TYP MIN/MAX OVER TEMPERATURE TEST C to C to MIN/ LEVEL PARAMETER CONDITIONS +25 C +25 C (2) +70 C (3) +85 C (3) UNITS MAX (1) INPUT Common-Mode Input Voltage Range (CMIR) 3.4 3.3 3.2 3.2 V min B Noninverting Input Impedance 300 1.2 k Ω pF typ C OUTPUT Voltage Output Swing No Load 4.1 3.9 3.9 3.8 V min A 100 Ω Load 3.8 3.7 3.7 3.7 V min A Current Output: Sinking, Sourcing V O 100 mA min A Closed-Loop Output Impedance G +2, f 100kHz 0.18 Ω typ C DISABLE (Disabled LOW) Power-Down Supply Current (+V S V DIS All Channels 390 600 650 665 µ A typ A Disable Time V IN 0.25V DC µ s typ C Enable Time V IN 0.25V DC ns typ C Off Isolation G +2, 10MHz dB typ C Output Capacitance in Disable pF typ C Turn-On Glitch G +2, V IN 100 mV typ C Turn-Off Glitch G +2, V IN mV typ C Enable Voltage 3.3 3.5 3.6 3.7 V min A Disable Voltage 1.8 1.7 1.6 1.5 V max A Control Pin Input Bias Current DIS V DIS Each Channel 130 143 149 µ A max A POWER SUPPLY Specified Operating Voltage V typ C Minimum Operating Voltage 1.75 1.8 1.9 V min B Maximum Operating Voltage V max A Maximum Quiescent Current V S 42.2 43.5 mA max A Minimum Quiescent Current V S 37.5 34.8 mA min A Power-Supply Rejection Ratio PSRR) Input-Referred, f 100kHz dB typ A TEMPERATURE RANGE Specification: IDBQ to +85 C typ C Thermal Resistance, θ JA Junction-to-Ambient DBQ SSOP-16 C/W typ C Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS: V S +5V OPA3693 SBOS353 DECEMBER 2006 Boldface limits are tested at +25 At G IN grounded) and R L 100 Ω to V S /2, unless otherwise noted. OPA3693IDBQ TYP MIN/MAX OVER TEMPERATURE TEST C to C to MIN/ LEVEL PARAMETER CONDITIONS +25 C +25 C (2) +70 C (3) +85 C (3) UNITS MAX (1) AC PERFORMANCE (see Figure 29) Small-Signal Bandwidth O 0.5V PP G 600 MHz typ C G 500 400 390 380 MHz min B G 450 C Bandwidth for 0.2dB Gain Flatness V O 0.5V PP 280 110 100 MHz min B Peaking at a Gain of V O 0.5V PP 2.2 2.9 3.9 4.2 dB max B Large-Signal Bandwidth V O PP 425 MHz typ C Slew Rate Step 1500 1200 1100 1000 µ s min B Rise-and-Fall Time V O 0.5V Step 0.8 ns typ C V O Step 1.0 ns typ C Settling Time to 0.02% V O Step ns typ C Settling Time to 0.1% V O Step ns typ C Harmonic Distortion f 10MHz, V O PP 2nd-Harmonic R L 100 Ω to V S dBc max B R L 500 Ω to V S dBc max B 3rd-Harmonic R L 100 Ω to V S dBc max B R L 500 Ω to V S dBc max B Input Voltage Noise f 1MHz 1.8 2.7 2.9 nV/ Hz max B Noninverting Input Current Noise f 1MHz pA/ Hz max B Inverting Input Current Noise (internal) f 1MHz pA/ Hz max B DC PERFORMANCE (4) Gain Error G 0.8 typ C G 0.6 1.2 1.3 1.4 max A G R s Ω 0.5 1.1 1.2 1.3 max B Internal R F and R G Maximum 300 341 345 347 Ω max A Minimum 300 264 260 258 Ω min A Input Offset Voltage V CM V S 0.6 3.5 4.0 4.2 mV max A Average Offset Voltage Drift V CM V S µ C max B Noninverting Input Bias Current V CM V S µ A max A Average Noninverting Input Bias Current Drift V CM V S 170 170 nA/ C max B Inverting Input Bias Current (internal) V CM V S µ A max A Average Inverting Input Bias Current Drift V CM V S nA/ C max B (1) Test levels: (A) 100% tested at +25 Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature ambient for +25 C specifications. (3) Junction temperature ambient at low temperature limits; junction temperature ambient +14 C at high temperature limit for over temperature specifications. (4) Current is considered positive out of pin. Submit Documentation Feedback

www.ti.com OPA3693 SBOS353 DECEMBER 2006 ELECTRICAL CHARACTERISTICS: V S +5V (continued) Boldface limits are tested at +25 At G IN grounded) and R L 100 Ω to V S /2, unless otherwise noted. OPA3693IDBQ TYP MIN/MAX OVER TEMPERATURE TEST C to C to MIN/ LEVEL PARAMETER CONDITIONS +25 C +25 C (2) +70 C (3) +85 C (3) UNITS MAX (1) INPUT Least Positive Input Voltage 1.6 1.7 1.8 1.8 V max B Most Positive Input Voltage 3.4 3.3 3.2 3.2 V min B Noninverting Input Impedance 300 1.2 k Ω pF typ C OUTPUT Most Positive Output Voltage No Load 4.2 4.0 V min A R L 100 Ω Load to V S 4.0 3.9 V min A Least Positive Output Voltage No Load 0.8 1.0 V max A R L 100 Ω Load to V S 1.0 1.1 V max A Current Output Sourcing, Sinking V O V S 100 mA min A Closed-Loop Output Impedance G +2, f 100kHz 0.18 Ω typ C DISABLE (Disabled LOW) Power-Down Supply Current (+V S V DIS All Channels 400 550 -600 -625 µ A typ C Disable Time µ s typ C Enable Time ns typ C Off Isolation G +2, 10MHz dB typ C Output Capacitance in Disable pF typ C Turn-On Glitch G +2, V IN V S 100 mV typ C Turn-Off Glitch G +2, V IN V S mV typ C Enable Voltage 3.3 3.5 3.6 3.7 V min B Disable Voltage 1.8 1.7 1.6 1.5 V max B Control Pin Input Bias Current DIS V DIS Each Channel 130 143 149 µ A typ C POWER SUPPLY Specified Single-Supply Operating Voltage V typ C Minimum Operating Voltage +3.5 +3.6 +3.8 V min B Maximum Single-Supply Operating Voltage +12 +12 +12 V max A Maximum Quiescent Current V S +5V 34.5 36.5 39.2 mA max A Minimum Quiescent Current V S +5V 34.5 28.1 27.2 mA min A Power-Supply Rejection Ratio (+PSRR) Input-Referred dB typ C TEMPERATURE RANGE Specification: IDBQ to +85 C typ C Thermal Resistance, θ JA Junction-to-Ambient DBQ SSOP-16 C/W typ C Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS: /c451 /c452 /c453 /c454 /c455 /c456 Frequency□(Hz) 10M 1G100M Normalized□Gain□(dB) G□=□+1V/V G□=□+2V/V G□= 1V/V/c45 /c451 Frequency□(MHz) 0 800100 200 300 400 500 600 700 Gain□(dB) V =□2VO PP V =□1VO PP V =□7VO PP V =□4VO PP 0.2 0.1 /c45 0.1 /c45 0.2 /c45 0.3 /c45 0.4 Frequency□(MHz) 0 500100 200 300 400 Normalized□Gain□(dB) R =□100 /c87L R =□75 /c87L R =□200 /c87L R =□150 /c87L 1.00 0.75 0.50 0.25 /c45 0.25 /c45 0.50 /c45 0.75 /c45 1.00 Deviation□from□Linear□Phase□( ) /c176 0 100 50 150 200 Frequency□(MHz) G□=□+1 G□= 1/c45 G□=□+2 RL =□100/c87 /c451 /c452 /c453 Time□(20ns/div) Output□Voltage□(V) Large□Signal Small□Signal /c451 /c452 /c453 Time□(20ns/div) Output□Voltage□(V) Large□Signal Small□Signal OPA3693 SBOS353 DECEMBER 2006 At G IN grounded) and R L 100 Ω unless otherwise noted. NONINVERTING SMALL-SIGNAL NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE FREQUENCY RESPONSE Figure Figure FREQUENCY RESPONSE FLATNESS vs LOAD DEVIATION FROM LINEAR PHASE Figure Figure GAIN OF PULSE RESPONSE GAIN OF PULSE RESPONSE Figure Figure Submit Documentation Feedback

www.ti.com /c45 60 /c45 65 /c45 70 /c45 75 /c45 80 /c45 85 Load□Resistance□( )/c87 50 500100 Harmonic□Distortion□(dBc) 2nd-Harmonic 3rd-Harmonic G□=□+2V/V V =□2VO PP /c45 60 /c45 65 /c45 70 /c45 75 /c45 80 /c45 85 /c45 90 Supply□Voltage□(/c177 V) Harmonic□Distortion□(dBc) G□=□+2V/V V =□2VO PP 2nd-Harmonic 3rd-Harmonic /c45 40 /c45 50 /c45 60 /c45 70 /c45 80 /c45 90 /c45 100 Output□Voltage□(V )PP 0.5 51 Harmonic□Distortion□(dBc) 2nd-Harmonic 3rd-Harmonic G□=□+2V/V R =□100L /c87 /c45 60 /c45 65 /c45 70 /c45 75 /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 Frequency□(MHz) 0.5 501 10 Harmonic□Distortion□(dBc) 2nd-Harmonic 3rd-Harmonic G□=□+2V/V R =□100 V =□2V L O PP /c87 /c45 50 /c45 55 /c45 60 /c45 65 /c45 70 /c45 75 /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 Frequency□(MHz) 0.1 501 10 Harmonic□Distortion□(dBc) 2nd-Harmonic 3rd-Harmonic G□=□+1V/V R =□100 V =□2V L O PP /c87 /c45 65 /c45 70 /c45 75 /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 Frequency□(MHz) 0.1 501 10 Harmonic□Distortion□(dBc) 2nd-Harmonic 3rd-Harmonic G□= 1V/V R =□100 V =□2V /c45 L O PP /c87 OPA3693 SBOS353 DECEMBER 2006 TYPICAL CHARACTERISTICS: (continued) At G IN grounded) and R L 100 Ω unless otherwise noted. 10MHz HARMONIC DISTORTION vs 10MHz HARMONIC DISTORTION vs LOAD RESISTANCE SUPPLY VOLTAGE Figure Figure 10MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE G HARMONIC DISTORTION vs FREQUENCY Figure Figure 10. G HARMONIC DISTORTION vs FREQUENCY G HARMONIC DISTORTION vs FREQUENCY Figure 11. Figure 12. Submit Documentation Feedback

www.ti.com Frequency□(MHz) 0 25050 100 150 200 Intercept□Point□(+dBm) 300/c87 OPA3693 PI 300/c87 50/c87 PO 500/c87 R =□500 /c87L 300/c87 50/c871/3 OPA3693 PI 300/c87 50/c87 PO 50/c87 R =□100 /c87L 100 Current□Noise□(pA/ ) /c214Hz Voltage□Noise□(nV/ ) /c214Hz 100 1k 10k 100k 1M 10M Frequency□(MHz) 22pA//c214Hz Inverting□Current□Noise□(internal) Noninverting□Current□Noise Voltage□Noise 17.8pA//c214Hz 1.8nV//c214Hz /c453 /c456 /c459 Gain□to□Capacitive□Load□(dB) 10 100 1000 Frequency□(MHz) G□=□+2 Optimized□RS C =□100pFL C =□10pFL C =□50pFL C =□20pFL R ( ) /c87 S 1 10 100 Capacitive□Load□(pF) G□=□+2 <□0.5dB□Peaking OPA3693 RS VIN VO CL 1k/c87300/c87 50/c87 300/c87 1k is□optional/c87 0 4 62 10 12 20 14 16 188 Time□(2ns/div) Input/Output□(5mV/div) /c45 5 /c45 10 /c45 15 /c45 20 G□=□+2 RL =□100/c87 2V 0V/c174 Output□Step See□Figure□36 Input Output /c45 20 /c45 30 /c45 40 /c45 50 /c45 60 /c45 70 /c45 80 /c45 90 /c45 100 Gain□(dB) 10 100 1000 Frequency□(MHz) G□=□+2 RL =□100/c87 V =□0VDIS Forward□and□Reverse See□Figure□42 OPA3693 SBOS353 DECEMBER 2006 TYPICAL CHARACTERISTICS: (continued) At G IN grounded) and R L 100 Ω unless otherwise noted. 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT INPUT VOLTAGE vs CURRENT NOISE DENSITY Figure 13. Figure 14. SMALL-SIGNAL FREQUENCY RESPONSE vs RECOMMENDED R S vs CAPACITIVE LOAD CAPACITIVE LOAD Figure 15. Figure 16. SETTLING TIME DISABLED FEEDTHROUGH vs FREQUENCY Figure 17. Figure 18. Submit Documentation Feedback

www.ti.com Frequency□(Hz) 1k 10k 100k 1M 10M 100M Power-Supply□Rejection□Ratio□(dB) +PSRR /c45PSRR 0.1 Frequency□(Hz) 10k 100M100k 1M 10M Output□Impedance□( ) /c87 1/3 OPA3693 300/c87 +5V /c45 5V 300/c87 50/c87 ZO 140 135 130 125 120 115 110 105 T emperature□( C)/c176 /c45 50 /c45 25 0 25 50 75 100 125 Supply□Current□(mA) Output□Current□(mA) Supply□Current Left□Scale Sinking□Output□Current Right□Scale Sourcing□Output□Current Right□Scale /c45 1 /c45 2 /c45 3 /c45 4 /c45 5 V (V) O /c45 250 /c45 200 /c45 150 /c45 100 /c45 50 0 250 20015010050 I (mA)O 1W□Internal□Power□Boundary Single-Channel 1W□Internal Power□Boundary Single-Channel

100 Load□Line/c87

50 Load□Line/c87

20 Load□Line/c87

Time□(50ns/div) Input/Output□(V) /c45 2 /c45 4 /c45 6 G□=□+2 R =□100 /c87L See□Figure□42 Input Output Time□(50ns/div) Input/Output□(V) /c45 2 /c45 4 /c45 6 G□= 1/c45 R =□100 /c87L See□Figure□44 InputOutput OPA3693 SBOS353 DECEMBER 2006 TYPICAL CHARACTERISTICS: (continued) At G IN grounded) and R L 100 Ω unless otherwise noted. PSRR vs FREQUENCY CLOSED-LOOP OUTPUT IMPEDANCE Figure 19. Figure 20. OUTPUT VOLTAGE AND CURRENT LIMITATIONS SUPPLY AND OUTPUT CURRENT vs TEMPERATURE Figure 21. Figure 22. NONINVERTING OVERDRIVE RECOVERY INVERTING OVERDRIVE RECOVERY Figure 23. Figure 24. Submit Documentation Feedback

www.ti.com 1.0 0.5 /c45 0.5 /c45 1.0 Ambient□T emperature□( C)/c176 /c45 50 /c45 25 0 25 50 75 100 125 Input□Offset□V oltage□(mV) /c45 8 /c45 16 Input□Bias□Currents□( A)/c109 VIO IB+ I (internal)B/c45 Input/Output□Range□( V) /c177 Supply□Voltages□( V)/c177 Input Output Time□(500ns/div) V /V (V) DI S OUT /c45 1 /c45 2 /c45 3 G□=□+2 V =□1VIN DC R =□100 /c87LSee□Figure□36 VOUT VDIS dG 0.12 0.10 0.08 0.06 0.04 0.02 Number□of□150 Loads/c87 1 2 3 4 dP dP dG/dP□(%/ ) /c176 OPA3693 Video□In Video□Loads /c45 5V +5V DIS Optional 1.0k/c87 Pull-Down 75/c87 No□Pull-Down With□1.0k□Pull-Down dG /c4510 /c4520 /c4530 /c4540 /c4550 /c4560 /c4570 Frequency□(Hz) 10M 1G100M Return□Loss□(dB) G□= 1 See□Figure□44 /c45 G□=□+2 See□Figure□42 /c4510 /c4520 /c4530 /c4540 /c4550 /c4560 /c4570 Frequency□(Hz) 10M 1G100M Return□Loss□(dB) G□=□+2 See□Figure□42 without□Trim□Capacitor with□Trim□Capacitor OPA3693 SBOS353 DECEMBER 2006 TYPICAL CHARACTERISTICS: (continued) At G IN grounded) and R L 100 Ω unless otherwise noted. COMMON-MODE INPUT AND OUTPUT SWING vs TYPICAL DC DRIFT OVER TEMPERATURE SUPPLY VOLTAGE Figure 25. Figure 26. COMPOSITE VIDEO dG/dP LARGE-SIGNAL DISABLE/ENABLE RESPONSE Figure 27. Figure 28. INPUT RETURN LOSS vs FREQUENCY (S11) OUTPUT RETURN LOSS vs FREQUENCY (S22) Figure 29. Figure 30. Submit Documentation Feedback

www.ti.com /c4540 /c4550 /c4560 /c4570 /c4580 /c4590 Frequency□(MHz) 0 1001 10 Crosstalk□(dB) Input-Referred OPA3693 SBOS353 DECEMBER 2006 TYPICAL CHARACTERISTICS: (continued) At G IN grounded) and R L 100 Ω unless otherwise noted. ALL HOSTILE CROSSTALK Figure 31. Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS: +5V /c451 /c452 /c453 /c454 /c455 /c456 Frequency□(Hz) 1M 1G10M 100M Normalized□Gain□(dB) V =□1VO PP G□=□+2V/V G□= 1/c45 V/V G□=□+1V/V /c45 1 /c45 2 /c45 3 /c45 4 /c45 5 /c45 6 Frequency□(MHz) 0 1000100 200 300 400 500 600 700 800 900 Gain□(dB) G□=□+2V/V R =□100L /c87 V =□1VO PP V =□2VO PP V =□3VO PP 0.2 0.1 /c45 0.1 /c45 0.2 /c45 0.3 /c45 0.4 Frequency□(MHz) 0 300100 200 Normalized□Gain□(dB) R =□100 /c87L R =□75 /c87L R =□200 /c87L R =□150 /c87L G□=□+2V/V 700 650 600 550 500 450 400 Single-Supply□Voltage□(V) 4 125 6 7 8 9 10 11 Bandwidth□(MHz) G□=□+2V/V V =□0.5V R =□100 O PP L /c87 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Time□(2ns/div) Output□Voltage□(V) Large□Signal Small□Signal 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Time□(2ns/div) Output□Voltage□(V) Large□Signal Small□Signal OPA3693 SBOS353 DECEMBER 2006 At G +2V/V IN grounded) and R L 100 Ω to V S /2, unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE Figure 32. Figure 33. SMALL-SIGNAL BANDWIDTH vs FREQUENCY RESPONSE FLATNESS vs LOAD SINGLE-SUPPLY VOLTAGE Figure 34. Figure 35. GAIN OF PULSE RESPONSE GAIN OF PULSE RESPONSE Figure 36. Figure 37. Submit Documentation Feedback

www.ti.com /c45 55 /c45 60 /c45 65 /c45 70 /c45 75 /c45 80 /c45 85 Frequency□(MHz) 0.5 501 10 Harmonic□Distortion□(dBc) 3rd-Harmonic 2nd-Harmonic G□=□+2V/V R =□100 V =□2V L O PP /c87 /c45 20 /c45 40 /c45 60 /c45 80 /c45 100 /c45 120 Output□Voltage□(V )PP 0.1 101 Harmonic□Distortion□(dBc) G□=□+2V/V R =□100 f□=□10MHz L /c87 3rd-Harmonic 2nd-Harmonic /c45 55 /c45 60 /c45 65 /c45 70 /c45 75 /c45 80 Load□Resistance□( )/c87 50 500100 Harmonic□Distortion□(dBc) 3rd-Harmonic 2nd-Harmonic G□=□+2V/V f□=□10MHz Frequency□(MHz) 0 30050 100 150 200 Intercept□Point□(+dBm) 250 R =□500 /c87L R =□100 /c87L 300/c87 50/c871/3 OPA3693 PI 300/c87 50/c87 PO 50/c87 300/c87 OPA3693 PI 300/c87 50/c87 PO 500/c87 OPA3693 SBOS353 DECEMBER 2006 TYPICAL CHARACTERISTICS: +5V (continued) At G +2V/V IN grounded) and R L 100 Ω to V S /2, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY +2) HARMONIC DISTORTION vs OUTPUT VOLTAGE Figure 38. Figure 39. HARMONIC DISTORTION vs LOAD RESISTANCE 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT Figure 40. Figure 41. Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION WIDEBAND BUFFER OPERATION OPA3693 +5V /c45 5V

50 Load/c87

50 Source/c87

6.8 F/c1090.1 F/c109 +6.8 F/c1090.1 F/c109 VI VO DIS OPA3693 +5V /c45 5V Open 6.8 F/c1090.1 F/c109 +6.8 F/c1090.1 F/c109 VI DIS VO OPA3693 SBOS353 DECEMBER 2006 However, the source must provide the noninverting input bias current required by the input stage to The OPA3693 gives the exceptional ac performance operate. An alternative approach to a gain of of a wideband current-feedback op amp with a highly buffer is described in the Wideband Unity-Gain linear output stage. It R F and R G Buffer section of this data sheet. resistors, making it a simple matter to select a gain of +2V/V, +1V/V, or 1V/V with no external resistors. Requiring only 13mA/ch supply current, the OPA3693 output swings to within of either supply with 650MHz small-signal bandwidth and 250MHz delivering PP into a 100 Ω load. This low output headroom in a very high-speed amplifier gives remarkable single +5V operation. The OPA3693 delivers PP swing with 400MHz bandwidth operating on a single +5V supply. The primary advantage of a current-feedback fixed-gain video buffer (as opposed to a slew-enhanced, low-gain, stable voltage-feedback implementation) is a higher slew rate with lower quiescent power and output noise. Figure shows the dc-coupled, gain of +2V/V, dual power-supply circuit configuration used as the basis for the Electrical Characteristics table and Typical Characteristics curves. For test purposes, the input impedance is set to Ω with a resistor to Figure 42. DC-Coupled, G +2, Bipolar-Supply, ground and the output impedance is set to Ω with Specification and Test Circuit a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched Ω load. For the circuit of Figure the total effective load is 100 Ω 600 Ω 85.7 Ω The disable control line DIS is typically left open to ensure normal amplifier operation. In addition to the usual power-supply decoupling capacitors to ground, a 0.01 µ F capacitor can be included between the two power-supply pins. This optional added capacitor typically improves the 2nd-harmonic distortion performance by 3dB to 6dB. Figure shows the DC-coupled, gain of +1V/V buffer configuration used as a starting point for the gain of +5V Typical Characteristic curves. In this case, the inverting input resistor, R G is left open giving a very broadband gain of +1V/V performance. While the test circuit shows a Ω input resistor, a buffer application is typically transforming from a source that cannot drive a heavy load to a 100 Ω load, such as shown in Figure The noninverting Figure 43. DC-Coupled, G +1V/V, input impedance of the OPA3693 is typically Bipolar-Supply, Specification and Test Circuit 100k Ω 2pF. Driving directly into the noninverting input provides this very light load to the source. Submit Documentation Feedback

www.ti.com OPA3693 +5V DIS 50/c87VO RF 300/c87 RG 300/c87 RM 60.4/c87 6.8 F/c1090.1 F/c109 /c45 5V +6.8 F/c1090.1 F/c109 +5V+VS DIS V /2S 604/c87 100/c87VO VI 604/c87 RG 300/c87 RF 300/c87 1000pF 1000pF +6.8 F/c1090.1 F/c10950 Source/c87 60.4/c87 OPA3693 SBOS353 DECEMBER 2006 Figure shows the DC-coupled, gain of 1V/V in the single +5V Typical Characteristic curves, the buffer configuration used as a starting point for the OPA3693 provides 300MHz bandwidth driving a gain of 1V/V Typical Characteristic curves. The PP swing into a 100 Ω load. The key requirement of input impedance is set to Ω using the parallel broadband single-supply operation is to maintain combination of an external 60.4 Ω resistor and the input and output signal swings within the useable internal 300 Ω R G resistor. The noninverting input is voltage ranges at both the input and the output. tied directly to ground. Since the internal design for The circuit of Figure shows the AC-coupled, gain the OPA3693 is current-feedback, trying to get of +2V/V, video buffer circuit used as the basis for improved dc accuracy by including a resistor on the the Electrical Characteristics table and Typical noninverting input to ground is ineffective. Using a Characteristics curves. The circuit of Figure direct short to ground on the noninverting input establishes an input midpoint bias using a simple reduces both the contribution of the dc bias current resistive divider from the +5V supply (two 604 Ω and noise current to the output error. While the resistors). The input signal is then AC-coupled into external 60.4 Ω is used here to match to the Ω this midpoint voltage bias. The input voltage can source from the test equipment, the maximum input swing to within 1.6V of either supply pin, giving a impedance in this configuration is limited to the 300 Ω 1.8V PP input signal range centered between the R G resistor even with the R M resistor removed. supply pins. The input impedance matching resistor Unlike the noninverting unity gain buffer application, (60.4 Ω used for testing is adjusted to give a Ω removing R M does not strongly impact the dc input match when the parallel combination of the operating point because the short on the biasing divider network is included. The gain resistor noninverting input of Figure provides the dc G is AC-coupled, giving the circuit a dc gain of operating voltage. This application of the OPA3693 +1V/V, which puts the input dc bias voltage (2.5V) on provides a very broadband, high-output, signal the output as well. Again, on a single +5V supply, the inverter. output voltage can swing to within of either supply pin while delivering more than 85mA output current. A demanding 100 Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA3693 can deliver large bipolar output current into this midpoint load with minimal crossover distortion, as illustrated by the +5V supply, 3rd-harmonic distortion plots. Figure 44. DC-Coupled, G 1V/V, Bipolar-Supply Specification and Test Circuit The OPA3693 may be used over a single-supply range of +3.5V to +12V. Though not a rail-to-rail Figure 45. AC-Coupled, G +2V/V, Single-Supply output design, the OPA3693 requires minimal input Specification and Test Circuit and output voltage headroom compared to other very-wideband video buffer amplifiers. As illustrated Submit Documentation Feedback

www.ti.com OPA3693 +5V DIS RO 50/c87VO RF 300/c87 RG 300/c87 RM 50/c87 /c45 5V VI OPA3693 Open V /2S VO 60.4/c87 100/c87 6.8 F/c1090.1 F/c109 VI DIS 1000pF +5VVS WIDEBAND UNITY-GAIN BUFFER WITH /c451 /c452 /c453 /c454 /c455 /c456 Normalized□Gain□(dB) 10 100 1000 Frequency□(MHz) G□=□+1,□Figure□43 G□=□+1,□Figure□47 OPA3693 SBOS353 DECEMBER 2006 While the circuit of Figure shows +5V The input impedance is still set by R M as the single-supply operation, this same circuit may be apparent impedance looking into R G is very high. R M used for single supplies ranging as high as +12V may be increased to show a higher input impedance, nominal. The noninverting input bias resistors are but larger values begin to impact dc output offset relatively low in Figure to minimize output dc voltage. offset as a result of noninverting input bias current. At higher signal-supply voltage, these resistors should be increased to limit the added supply current drawn through this path. Figure shows the AC-coupled, G +1V/V, single-supply specification and test circuit. In this case, the gain setting resistor, R G is simply left open to get a gain of +1V for ac signals. Once again, the noninverting input is dc biased at midsupply, putting that same V S at the output pin. The signal is AC-coupled into this midpoint with an added termination resistor on the source side of the blocking capacitor. Figure 47. Improved Unity-Gain Buffer This circuit creates an additional input offset voltage as the difference in the two input bias currents times the impedance to ground at V I Figure shows a comparison of small-signal frequency response for the unity-gain buffer of Figure compared to the improved approach shown in Figure Figure 46. AC-Coupled, G +1V/V, Single-Supply Specification and Test Circuit IMPROVED FLATNESS As shown in the Typical Characteristic curves, the unity-gain buffer configuration of Figure illustrates a peaking in the frequency response exceeding 2dB. This configuration gives the slight amount of Figure 48. Buffer Frequency Response Comparison overshoot and ringing apparent in the gain of +1V/V pulse response curves. A similar circuit that holds a flatter frequency response, giving improved pulse fidelity, is shown in Figure This circuit removes the peaking by bootstrapping out any parasitic effects on R G Submit Documentation Feedback

www.ti.com HIGH-FREQUENCY ACTIVE FILTERS /c453 /c456 /c459 /c4512 /c4515 /c4518 /c4521 /c4524 Gain□(dB) 1 10 100 1000 Frequency□(MHz) OPA3693 +5V /c45 5V 50/c87 50/c87 22pF 226/c87100/c87 0/c87 Source RG 300/c87 RF 300/c87 22pF VI VO OPA3693 SBOS353 DECEMBER 2006 This type of filter depends on a low output impedance from the amplifier through very high The extremely wide bandwidth of the OPA3693 frequencies to continue to provide an increasing allows a wide range of active filter topologies to be attenuation with frequency. As the amplifier output implemented with minimal amplifier bandwidth impedance rises with frequency, any input signal or interaction in the filter shape. Sallen-Key filters, for noise starts to feed directly through to the output via example, using either a gain of +1V/V or gain of the feedback capacitor. Because the OPA3693 used +2V/V amplifier, may be easily implemented with no in Figure has a 650MHz bandwidth, the active external gain setting elements. In general, given a filter continues to rolloff through frequencies desired filter ω O the amplifier should have at least exceeding 200MHz. Figure shows the frequency 20X that ω O to minimize filter interaction with the response for the filter of Figure where the desired amplifier frequency response. Figure illustrates an 40MHz cutoff is achieved and a 40dB/dec roll-off is example gain of line driver using the OPA3693 held through very high frequencies. that incorporates a 40MHz low-pass Butterworth response with just a few external components. The filter resistor values have been adjusted slightly here from an ideal filter analysis to account for parasitic effects. Figure 50. 40MHz Low-Pass Active Filter Response Figure 49. Line Driver with 40MHz Low-Pass Active Filter Submit Documentation Feedback

www.ti.com HIGH-SPEED INSTRUMENTATION MULTIPLEXED CONVERTER DRIVER LOW-PASS FILTER OPA3693 OPA3693 OPA3693 300/c87300/c87 300/c87 300/c87 300/c87 150/c87 150/c87 300/c87 VOUT /c453 /c456 /c459 /c4512 /c4515 Frequency□(Hz) 1 1G10M 100M Gain□(dB) 20log VOUT |V V/c45 |1 2 OPA3693 SBOS353 DECEMBER 2006 AMPLIFIER The converter driver in Figure multiplexes among Figure shows an instrumentation amplifier based the three input signals. The OPA3693 enable and on the OPA3693. The offset matching between disable times support multiplexing among video inputs makes this configuration an attractive input signals. The make-before-break disable stage for this application. The characteristic of the OPA3693 ensures that the differential-to-single-ended gain for this circuit is output is always under control. To avoid large 2V/V. The inputs are high-impedance, with only switching glitches, switch during the sync or retrace 1.2pF to ground at each input. The loads on the portions of the video signal the two inputs should OPA3693 outputs are equal for the best harmonic be almost equal at these times. The output is always distortion possible. under control, so the switching glitches for two inputs are 20mV. With standard video signals levels at the inputs, the maximum differential voltage across the disabled inputs does not exceed the 1.2V maximum allowed. The output resistors isolate the outputs from each other when switching between channels. The feedback network of the disabled channels forms part of the load seen by the enabled amplifier, attenuating the signal slightly. The circuit in Figure realizes a 7th-order Butterworth low-pass filter with a 3dB bandwidth of 20MHz. This filter is based on the KRC active filter Figure 51. High-Speed Instrumentation Amplifier topology that uses an amplifier with the fixed gain The OPA3693 makes a good amplifier for this type of filter. The component values have been adjusted As shown in Figure the OPA3693 used as an to compensate for the parasitic effects of the op instrumentation amplifier has a 420MHz, 3dB amp. bandwidth. This plot has been made for a PP output signal using a low-impedance differential input source. Figure 52. High-Speed Instrumentation Amplifier Response Submit Documentation Feedback

www.ti.com OPA3693 300/c87300/c87 100/c87V1 OPA3693 300/c87300/c87 100/c87V2 OPA3693 300/c87300/c87 100/c87V3 Selection Logic ADS828 10-Bit 75MSPS

0.1 F/c109

4.99k/c87 0.1 F/c109 4.99k/c87 0.1 F/c109 100pF REFT +3.5V REFB +1.5V +In /c45 In CM +5V OPA3693 300/c87 300/c87 120pF 82pF 220pF 22pF 68pF 47.5/c87 124/c87 OPA3693 300/c87 56pF110/c87 255/c87 300/c87 OPA3693 300/c87 300/c87 180pF48.7/c87 95.3/c87 49.9/c87 VOUT VIN /c45 0 /c45 20 /c45 40 /c45 60 /c45 80 /c45 100 Frequency□(MHz) 1 10003 10 30 100 300 7TH-ORDER□BUTTERWORTH FILTER□RESPONSE Gain□(dB) OPA3693 SBOS353 DECEMBER 2006 Figure 53. Multiplexed Converter Driver Figure 54. 7th-Order Butterworth Filter Submit Documentation Feedback

www.ti.com DESIGN-IN TOOLS DEMONSTRATION BOARDS OPERATING SUGGESTIONS GAIN SETTING OUTPUT CURRENT AND VOLTAGE DRIVING CAPACITIVE LOADS OPA3693 SBOS353 DECEMBER 2006 show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA3693 output drive capabilities, noting that the graph is bounded by a Safe Operating Area of A printed circuit board (PCB) is available to assist in maximum internal power dissipation. Superimposing the initial evaluation of circuit performance using the resistor load lines onto the plot shows that the OPA3693. The fixture is offered free of charge as an OPA3693 can drive 3.4V into Ω or 3.7V into unpopulated PCB, delivered with a user's guide. The Ω without exceeding either the output capabilities summary information for this fixture is shown in or the dissipation limit. A 100 Ω load line (the Table standard test-circuit load) shows full 3.8V output swing capability, as shown in the Typical Table Demonstration Fixture Characteristics ORDERING LITERATURE PRODUCT PACKAGE NUMBER NUMBER The minimum specified output voltage and current OPA3693IDBQ, specifications over temperature are set by SSOP-16 DEM-OPA-SSOP-3C SBOU047 Noninverting worst-case simulations at the cold temperature OPA3693IDBQ, SSOP-16 DEM-OPA-SSOP-3D SBOU046 extreme. Only at cold startup will the output current Inverting and voltage decrease to the numbers shown in the over-temperature min/max specifications. As the The demonstration fixture can be requested at the output transistors deliver power, their junction Texas Instruments web site (www.ti.com) through the temperatures increase, which decreases their V BE s OPA3693 product folder. (increasing the available output voltage swing) and increases their current gains (increasing the available output current). In steady-state operation, the available output voltage and current is always greater than that shown in the over-temperature characteristics since the output stage junction Setting the gain for the OPA3693 is very easy. For a temperatures are higher than the minimum specified gain of +2, ground the IN pin and drive the +IN pin operating ambient. with the signal. For a gain of +1, either leave the IN pin open and drive the +IN pin or drive both the +IN To maintain maximum output stage linearity, no and IN pins (see Figure For a gain of output short-circuit protection is provided. This ground the +IN pin and drive the IN pin with the configuration is not normally a problem, since most input signal. An external resistor may be used in a series matching resistor at the series with the IN pin to reduce the gain. However, output that limits the internal power dissipation if the because the internal resistors F and R G have a output side of this resistor is shorted to ground. tolerance and temperature drift different than the However, shorting the output pin directly to an external resistor, the absolute gain accuracy and adjacent positive power-supply pin, in most cases, gain drift over temperature are relatively poor destroys the amplifier. If additional protection to a compared to the previously described standard gain power-supply short is required, consider a small connections using no external resistor. series resistor in the power-supply leads. Under heavy output loads, this reduces the available output voltage swing. A Ω series resistor in each supply lead limits the internal power dissipation to for The OPA3693 provides output voltage and current an output short while decreasing the available output capabilities that can easily support multiple video voltage swing only 0.5V, for up to 100mA desired loads and/or 100 Ω loads with very low distortion. load currents. Always place the 0.1 µ F power-supply Under no-load conditions at +25 the output decoupling capacitors after these supply-current voltage typically swings to of either supply rail; limiting resistors directly on the device supply pins. the tested swing limit is within 1.2V of either rail. Into a Ω load (the minimum tested load), it is tested to deliver more than 90mA. One of the most demanding, and yet very common, The specifications described above, though familiar load conditions for an op amp is capacitive loading. in the industry, consider voltage and current limits Often, the capacitive load is the input of an separately. In many applications, it is the voltage analog-to-digital converter (ADC), including current, or V-I product, which is more relevant to additional external capacitance, which may be circuit operation. Refer to the Output Voltage and recommended to improve ADC linearity. A Current Limitations plot Figure in the Typical high-speed, high open-loop gain amplifier like the Characteristics The and Y-axes of this graph Submit Documentation Feedback

www.ti.com DISTORTION PERFORMANCE OPA3693 SBOS353 DECEMBER 2006 OPA3693 can be very susceptible to decreased configuration it is just R F (see Figure Also, stability and may give closed-loop response peaking providing an additional supply decoupling capacitor when a capacitive load is placed directly on the (0.01 µ between the supply pins (for bipolar output pin. When the amplifier open-loop output operation) improves the 2nd-order distortion slightly resistance is considered, this capacitive load (3dB to 6dB). introduces an additional pole in the signal path that The OPA3693 has an extremely low 3rd-order can decrease the phase margin. Several external harmonic distortion. This feature also produces a solutions to this problem have been suggested. high two-tone, 3rd-order intermodulation intercept. When the primary considerations are frequency Two graphs for this intercept are given in the in the response flatness, pulse response fidelity, and/or Typical Characteristics one for and one for +5V. distortion, the simplest and most effective solution is The lower curve shown in each graph is defined at to isolate the capacitive load from the feedback loop the Ω load when driven through a Ω matching by inserting a series isolation resistor between the resistor, to allow direct comparisons to RF MMIC amplifier output and the capacitive load. This resistor devices. The higher curve in each graph shows the does not eliminate the pole from the loop response, intercept if the output is taken directly at the output but rather shifts it and adds a zero at a higher pin with a 500 Ω load, to allow prediction of the frequency. The additional zero acts to cancel the 3rd-order spurious level when driving a lighter load, phase lag from the capacitive load pole, thus such as an ADC input. The output matching resistor increasing the phase margin and improving stability. attenuates the voltage swing from the output pin to The Typical Characteristics show a Recommended the load by 6dB. If the OPA3693 drives directly into R S vs Capacitive Load curve Figure to help the the input of a high-impedance device, such as an designer pick a value to give 0.5dB peaking to the ADC, this 6dB attenuation is not taken and the load. The resulting frequency response curves show intercept increases, as shown in the 500 Ω load a 0.5dB peaked response for several selected typical characteristic. capacitive loads and recommended R S The intercept is used to predict the intermodulation combinations. Parasitic capacitive loads greater than spurious levels for two closely-spaced frequencies. If 2pF can begin to degrade the performance of the the two test frequencies (f1 and f2) are specified in OPA3693. Long PCB traces, unmatched cables, and terms of average and delta frequency, f O (f1 f2)/2 connections to other amplifier inputs can easily and Δ f |f2 f1|/2, then the two, 3rd-order, close-in exceed this value. Always consider this effect spurious tones appear at f O Δ The difference carefully, and add the recommended series resistor between two equal test tone power levels and these as close as possible to the OPA3693 output pin (see intermodulation spurious power levels is given by the Board Layout Guidelines section). Δ dBc (IM3 P O where IM3 is the intercept The criterion for setting this R S resistor is a maximum taken from the Typical Characteristics and P O is the bandwidth, flat frequency response at the load power level in dBm at the Ω load for one of the 0.5dB peaking). For the OPA3693 operating at a two closely-spaced test frequencies. For instance, at gain of +2V/V, the frequency response at the output 50MHz, the OPA3693 at a gain of has an pin is very flat to begin with, allowing relatively small intercept of 47dBm at a matched Ω load. If the full values of R S to be used for low capacitive loads. envelope of the two frequencies needs to be PP at this load, this requires each tone to be 4dBm (1V PP The 3rd-order intermodulation spurious tones will then be (47 83dBc below the test tone The OPA3693 provides good distortion performance power level 79dBm). If this same PP two-tone into a 100 Ω load on supplies. Relative to envelope were delivered directly into a lighter 500 Ω alternative solutions, the OPA3693 holds much lower load, the intercept would increase to the 48dBm distortion at higher frequencies 20MHz) than shown in the Typical Characteristics With the same alternative solutions. Generally, until the fundamental output signal and gain conditions, but now driving signal reaches very high-frequency or power levels, directly into a light load with no matching loss, the the 2nd-harmonic dominates the distortion with a 3rd-order spurious tones will then be at least (48 negligible 3rd-harmonic component. Focusing then 92dBc below the 4dBm test tone power levels on the 2nd-harmonic, increasing the load impedance centered on 50MHz 88dBm). We are still using a improves distortion directly. Remember that the total 4dBm for the PP output swing into this 500 Ω load. load includes the feedback network in the While not strictly correct from a power standpoint, noninverting configuration (see Figure this value this does give the correct prediction for spurious is the sum of R F R G while in the inverting level. The class AB output stage for the OPA3693 is Submit Documentation Feedback

www.ti.com GAIN ACCURACY AND LINEARITY 0.0200 0.0175 0.0150 0.0125 0.0100 0.0075 0.0050 0.0025 V (peak-to-peak) O 2 3 4 5 6 7 8 %□Deviation Figure□42□T est□Circuit R =□100 /c87L R =□500 /c87L NOISE PERFORMANCE 700 600 500 400 300 200 100 Gain□(V/V) Number□of□Units Mean□=□1.9883 =□0.0967/c115 4kT RG RG RF RS OPA3693 IBI EO IBN 4kT□=□1.6E 20J/c45 at□290K ERS ENI 4kTRS 4kTRF OPA3693 SBOS353 DECEMBER 2006 much more voltage-swing-dependent on output distortion than strictly power-dependent. To use the 500 Ω intercept curve, use the single-tone voltage swing as if it were driving a Ω load to compute the P O used in the intercept equation. The OPA3693 provides improved absolute gain accuracy and dc linearity over earlier fixed gain of two line drivers. Operating at a gain of +2V/V by tying the IN pin to ground, the OPA3693 shows a maximum gain error of at +25 The dc gain therefore lies between 1.98V/V and 2.02V/V at room temperature. Over the specified temperature ranges, this gain tolerance expands only slightly due to the Figure 56. DC Linearity vs Output Swing and matched temperature drift for R F and R G Achieving Loads this gain accuracy requires a very low impedance ground at IN. Typical production lots show a much tighter distribution in gain than this specification. Figure shows a typical distribution in measured gain at the gain of +2V/V configuration, in this case The OPA3693 offers an excellent balance between showing a slight drop in the mean (0.25%) from the voltage and current noise terms to achieve a low nominal but with a very tight distribution. output noise under a variety of operating conditions. The inverting node noise current (internal) appears at the output multiplied by the relatively low 300 Ω feedback resistor. The input noise voltage (1.8nV/ Hz is extremely low for a unity-gain stable amplifier. This low input voltage noise was achieved at the price of higher noninverting input current noise (17.8pA/ Hz As long as the ac source impedance looking out of the noninverting input is less than 100 Ω this current noise does not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise for the each of the three gain settings available using the OPA3693. Figure shows the op amp noise analysis model with all of the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/ Hz or pA/ Hz Figure 55. Typical +2V/V Gain Distribution The exceptionally linear output stage (as illustrated by the high 3rd-order intermodulation intercept) and low thermal gradient induced errors for the OPA3693 give an extremely linear output over large voltage swings and heavy loads. Figure shows the tested deviation (in of peak-to-peak) from linearity for a range of symmetrical output swings and loads. Below PP for either a 100 Ω or a 500 Ω load, the OPA3693 delivers greater than 14-bit linear output response. Figure 57. Op Amp Noise Model Submit Documentation Feedback

www.ti.com /c177 /c180(NG V )□+□(I R /2 NG) (I R )OS BN S BI F/c180 /c180 /c177 /c180 /c177 /c180 /c109 /c180 /c87 /c180 /c177 /c109 /c180 /c87 /c177 /c177 /c177 /c177 = 7mV 1.75mV 15mV = 23.75mV E =O E +□(I R ) +□4kTRNI BN S S 2 2 NG +□(I R ) +□4kTR NGBI F F 2 2 DISABLE OPERATION E =N E +□(I R ) +□4kTRNI BN S S + 2 2 4kTRF NG I RBI F NG DC ACCURACY AND OFFSET CONTROL 25k/c87 110k/c87 15k/c87 IS Control /c45 VS +VS VDIS OPA3693 SBOS353 DECEMBER 2006 The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation shows the general form for the output noise voltage using the terms shown in Figure where NG noninverting signal gain. Minimizing the resistance seen by the noninverting input also minimizes the output dc error. For Dividing this expression through by noise gain (NG improved dc precision in a wideband low-gain R F G gives the equivalent input-referred spot amplifier, consider the OPA842 where a bipolar input noise voltage at the noninverting input, as shown in is acceptable (low source resistance) or the OPA656 Equation where a JFET input is required. The OPA3693 provides an optional disable feature Evaluating the output noise and input noise that can be used to reduce system power. If the V DIS expressions for the two noninverting gain control pin is left unconnected, the OPA3693 configurations, and with two different values for the operates normally. This shutdown is intended only as noninverting source impedance, gives output and a power-savings feature. Forward path isolation input-referred spot noise voltages of Table when disabled is very good for small signals for gains of or +2. Large-signal isolation is not Table Total Output and Input-Referred Noise ensured. Using this feature to multiplex two or more outputs together is not recommended. Large signals OUTPUT SPOT TOTAL INPUT R S NOISE SPOT NOISE applied to the disabled output stages can turn on CONFIGURATION Ω E O (nV/ Hz E N (nV/ Hz parasitic devices degrading signal linearity for the G Figure 8.3 4.15 desired channel. G Figure 300 Turn-on time is very quick from the shutdown G Figure 7.3 7.3 condition (typically 60ns). Turn-off time strongly G Figure 300 9.2 9.2 depends on the selected gain configuration and load, but is typically µ s for the circuit of Figure The output noise is being dominated by the inverting current noise times the internal feedback resistor. To shutdown, the control pin must be asserted low. This gives a total input-referred noise voltage that This logic control is referenced to the positive supply, exceeds the 1.8nV voltage term for the amplifier as the simplified circuit of Figure shows. itself. A current-feedback op amp such as the OPA3693 provides exceptional bandwidth and slew rate giving fast pulse settling but only moderate dc accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output dc offset for wideband current-feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 58. Simplified Disable Control Circuit Figure using worst-case +25 C input offset voltage and the two input bias currents, gives a In normal operation, base current to is provided worst-case output offset range equal to: through the 110k Ω resistor while the emitter current through the 15k Ω resistor sets up a voltage drop that is inadequate to turn on the two diodes in the Submit Documentation Feedback

www.ti.com Maximum□T =□+85 C□+□(0.654W 80 C/W)□=□137 C/c176J /c180 /c176 /c176 BOARD LAYOUT GUIDELINES THERMAL ANALYSIS OPA3693 SBOS353 DECEMBER 2006 emitter. As V DIS is pulled LOW, additional current is pulled through the 15k Ω resistor, eventually turning on these two diodes µ A). At this point, any further current pulled out of V DIS goes through those All actual a lower junction diodes holding the emitter-base voltage of at temperature than the +137 C computed above. approximately 0V. This shuts off the collector current Compute your actual output stage power to get an out of Q1, turning the amplifier off. The supply accurate estimate of maximum junction temperature, current in the shutdown mode is only that required to or use the results shown here as an absolute operate the circuit of Figure maximum. The shutdown feature for the OPA3693 is a positive supply referenced, current-controlled interface. Open-collector (or drain) interfaces are most Achieving optimum performance with a effective, as long as the controlling logic can sustain high-frequency amplifier such as the OPA3693 the resulting voltage (in the open mode) that appears requires careful attention to PCB layout parasitics at the V DIS pin. That voltage is one diode below the and external component types. Recommendations positive supply voltage applied to the OPA3693. For that will optimize performance include: voltage output logic interfaces, the on/off voltage levels described in the Electrical Characteristics Minimize parasitic capacitance to any ac ground apply only for a +5V positive supply on the for all of the signal I/O pins. Parasitic capacitance on OPA3693. An open-drain interface is recommended the output can cause instability; on the noninverting for shutdown operation using a higher positive supply input, it can react with the source impedance to for the OPA3693 and/or logic families with cause unintentional bandlimiting. To reduce inadequate high-level voltage swings. unwanted capacitance, create a window around the signal I/O pins in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. The OPA3693 does not require heatsinking or airflow Minimize the distance 0.25 from the in most applications. Maximum desired junction power-supply pins to high-frequency 0.1 µ F temperature sets the maximum allowed internal decoupling capacitors. At the device pins, the ground power dissipation as described here. In no case and power plane layout should not be in close should the maximum junction temperature be proximity to the signal I/O pins. Avoid narrow power allowed to exceed +150 and ground traces to minimize inductance between Operating junction temperature J is given by T A the pins and the decoupling capacitors. The P D θ JA The total internal power dissipation D is power-supply connections should always be the sum of quiescent power DQ and additional decoupled with these capacitors. Larger (2.2 µ F to power dissipated in the output stage DL to deliver 6.8 µ decoupling capacitors, effective at lower load power. Quiescent power is simply the specified frequency, should also be used on the supply pins. no-load supply current times the total supply voltage These may be placed somewhat farther from the across the part. P DL depends on the required output device and may be shared among several devices in signal and load but would, for a grounded resistive the same area of the PCB. load, be at a maximum when the output is fixed at a Careful selection and placement of external voltage equal to either supply voltage (for equal components preserve the high-frequency bipolar supplies). Under this worst-case condition, performance of the OPA3693. Use resistors that P DL V S /(4 R L where R L includes feedback have low reactance at high frequencies. network loading. This value is the absolute highest Surface-mount resistors work best and allow a tighter power that can be dissipated for a given R L All overall layout. Metal film and carbon composition actual stage. high-frequency performance. Again, keep their leads Note that it is the power in the output stage and not and PCB trace length as short as possible. Never into the load that determines internal power use wirewound type resistors in a high-frequency dissipation. application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, As a worst-case example, compute the maximum T J always position the series output resistor, if any, as using an OPA3693IDBQ (SSOP-16 package) in the close as possible to the output pin. Because the circuit of Figure operating at the maximum inverting input node is internal for the OPA3693, it is specified ambient temperature of +85 C and driving more robust to layout issues than amplifiers with a grounded 100 Ω load at V S /2. Maximum internal similar speed but external feedback and gain power is: resistors. Other network components, such as Submit Documentation Feedback

www.ti.com INPUT AND ESD PROTECTION External Pin +VCC /c45VCC Internal Circuitry OPA3693 SBOS353 DECEMBER 2006 noninverting input termination resistors, should also Socketing a high-speed part such as the be placed close to the package. Good axial metal OPA3693 is not recommended. The additional lead film or surface-mount resistors have approximately length and pin-to-pin capacitance introduced by the 0.2pF in shunt with the resistor. For resistor values socket can create an extremely troublesome 2.0k Ω this parasitic capacitance can add a pole parasitic network, which can make it almost and/or zero below 400MHz that can effect circuit impossible to achieve a smooth, stable frequency operation. Keep resistor values as low as possible response. Best results are obtained by soldering the consistent with load driving considerations. OPA3693 directly onto the board. Connections to other wideband devices on the PCB may be made with short direct traces or through onboard transmission lines. For short connections, The OPA3693 is built using a very high-speed consider the trace and the input to the next device as complementary bipolar process. The internal junction a lumped capacitive load. Relatively wide traces breakdown voltages are relatively low for these very (50mils to 100mils) should be used, preferably with small geometry devices. These breakdowns are ground and power planes opened up around them. reflected in the Absolute Maximum Ratings table. All Estimate the total capacitive load and set R S from device pins are protected with internal ESD the plot of Recommended R S vs Capacitive Load protection diodes to the power supplies, as shown in Figure Low parasitic capacitive loads 4pF) Figure may not need an R S since the OPA3693 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A Ω environment is normally not necessary on board, and in fact, a higher impedance environment improves Figure 59. Internal ESD Protection distortion, as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace These diodes provide moderate protection to input dimensions, a matching series resistor into the trace overdrive voltages above the supplies as well. The from the output of the OPA3693 is used, as well as a protection diodes can typically support 30mA terminating shunt resistor at the input of the continuous current. Where higher currents are destination device. Remember also that the possible (for example, in systems with 15V supply terminating impedance is the parallel combination of parts driving into the OPA3693), current limiting the shunt resistor and the input impedance of the series resistors may be added on the noninverting destination device; this total effective impedance input. Keep this resistor value as low as possible should be set to match the trace impedance. If the since high values degrade both noise performance 6dB attenuation of a doubly-terminated transmission and frequency response. The inverting input already line is unacceptable, a long trace can be has a 300 Ω resistor from the external pin to the series-terminated at the source end only. Treat the internal summing junction for the op amp. This trace as a capacitive load in this case and set the resistor provides considerable protection for that series resistor value as illustrated in the plot of node. Figure This configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) OPA3693IDBQ ACTIVE SSOP/ QSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA3693IDBQG4 ACTIVE SSOP/ QSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA3693IDBQR ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA3693IDBQRG4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 1

Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant OPA3693IDBQR DBQ 16 MLA 330 12 6.4 5.2 2.1 8 12 PKGORN T1TR-MS P TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) OPA3693IDBQR DBQ 16 MLA 342.9 336.6 28.58 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 2

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