OP292GBC

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Go ANALOG Dual/Quad Single Supply DEVICES Operational Amplifier FEATURES PIN CONNECTIONS Single Supply Operation: 4.5 V to 33 V Input Common Mode Includes Ground 8-Lead Narrow-Body SO 8-Lead Epoxy DIP Output Swings to Ground (S Suffix) (P Suffix) High Slew Rate: 3 V/ps High Gain Bandwidth: 4 MHz Low Input Offset Voltage iy ours HLA le] High Open-Loop Gain al fa] “NA Bhs ours No Phase Inversion a al ana [5 Aa “Ne Low Cost -v[a] alls INE

APPLICATIONS

Mobile Phones 14-Lead Narrow-Body SO 14-Lead Epoxy DIP Servo Controls . (S Suffix) (P Suffix) Modems and Fax Machines Pagers Power Supply Monitors and Controls Gye fa outa [af fia] ouro Battery Operated Instrumentation i iS “INA aha Apa “ino OP492 GENERAL DESCRIPTION Gl i a pe} The OP292/OP492 are low cost general purpose dual and quad i Fy [4] opag2 [in] operational amplifiers designed for single supply applications +INB INC and are ideal for +5 volt systems. (2 ne a jin Fabricated on Analog Devices’ CBCMOS process, the OP292/ ours ay VE oure OP492 series has a PNP input stage that allows the input volt- age range to include ground. A BiCMOS output stage enables the output to swing to ground while sinking current. The OP292/OP492 series is unity-gain stable and features an outstanding combination of speed and performance for single or dual supply operation. The OP292/OP492 provide high slew rate, high bandwidth, with open-loop gain exceeding 40,000 and offset voltage under 800 4.V (OP292) and 1 mV (OP492). With these combinations of features and low supply current, the OP292/OP492 series is an excellent choice for battery operated applications. The OP292/OP492 series performance is specified for single or dual supply voltage operation over the extended industrial tem- perature range (—40°C to + 125°C). SO-8 (OP292) and SO-14. REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

ELECTRICAL CHARACTERISTICS (@ v, = +5 V, Vey = 0V, Vo = +2V, T, = +25°C unless otherwise noted) INPUT CHARACTERISTICS Offset Voltage Vos OP292 O.1 0.8 mV op492 Vos 0.1 1 mV ~40°C = Ty = +85°C 03 1S mV Input Bias Current Is 450 700 nA 40°C = Ty = +85°C 075° 25 BA Input Offset Current los 7 50 nA -40°C = Ty = +125°C 04 1.2 Ba Input Voltage Range | 0 4.0 Vv Common-Mode Rejection Ratio. | CMRR Vem = 0 V t0 4.0V 75 95 dB —40°C = Ty = +85°C 70 93 dB —40°C = T, = +125°C 65 90 dB Large Signal Voltage Gain Avo Ry = 10kQ, Vo =O.1Vw04V | 25 200 VimV =40°C = Ty = +85°C 10 100 VimV -40°C = Ty = +125°C 5 50 Vim Offset Voltage Drift AVos/AT | -40°C = Ty = +125°C 2 10 pyre Long Term Vos Drift AVos/At Note 1 1 nV/Month Bias Current Drift Aly/AT —40°C = Ty = +85°C 6 pArC -40°C = T, = +125°C 400 pArC Offset Current Drift Alos/AT —40°C = Ty = +85°C Ls parC 40°C = Ty = +125°C 2 pArC OUTPUT CHARACTERISTICS Output Voltage Swing High Vour R,, = 100 kQ to GND —40°C = Ty = +125°C 4.0 43 Vv R, = 2kQto GND 3.8 41 v 40°C = Ty = +125°C 37 3.9 v Low Vour R, = 100 KO to V+ 8 20 mV 40°C = Ty = +125°C 12 20 mV Ry = 2 kQ to V+ 280 450 mV —40°C = Ty = +125°C 300-550 mV Short Circuit Current Limit Isc 5 8 mA POWER SUPPLY Power Supply Rejection Ratio PSRR Vy = 4.5 Vt0 430V,Vo=2V | 75 95 dB -40°C = Ty = +125°C 70 90 dB Supply Current Per Amp Igy Vo=2V OP292, OP492 0.8 1.2 mA DYNAMIC PERFORMANCE Slew Rate SR | RL = 10k0 3 Vins 40°C = T, = +125°C 1 2 Vins Gain Bandwidth Product GBP 4 MHz Phase Margin bm 78 Degrees Channel Separation cs fo = 1 kHz 100 dB NOISE PERFORMANCE Voltage Noise ey PP 0.1 Hz to 10 Hz 25 nV pp_ Voltage Noise Density &, f = 1kHz 15 aV/\\ Hz Current Noise Density in 0.7 pA/\\/Hz NOTES ‘Long term offset voltage drift is guaranteed by 1000 hours life test performed on three independent wafer lots at + 125°C with LTPD of 1.3. Specifications subject to change without notice. -2- REV.0

ELECTRICAL CHARACTERISTICS (a v, = «15 v, 1, = +25°C unless otherwise noted) Parameter [Symbol | Conditions Min Typ Max | Units INPUT CHARACTERISTICS Offset Voltage Vos OP292 1.0 2.0 mV 40°C = Ty = +85°C 1.2 2.5 mV 40°C = Ta = +125°C 15 3 mV op492 14 2.5 mV —40°C = Ty = +125°C 2 3 mV Input Bias Current Is 375 700 nA 40°C = Ty = +125°C 0.5 1 HA Input Offset Current los 7 50 nA =40°C = Ty = +85°C 20 100 nA 40°C = Ta = +125°C 04 12 A Input Voltage Range Note 1 -11 ll Vv Common-Mode Rejection Ratio | CMRR Vem = #11 78 100 dB =40°C = Ty = +125°C 75 95 dB Large Signal Voltage Gain Avo R, = 10k9,V, = +10V | 25 120 VimV ~40°C = T, = +85°C 10 78 VimV -40°C = T, = +128°C 5 60 VimV Offset Voltage Drift AVos/AT | 40°C = Ty = +125°C 4 10 BVPC Bias Current Drift Aly/AT —40°C = T, = +125°C 3 parC OUTPUT CHARACTERISTICS Output Voltage Swing Vo R, = 2kQ to GND +n 12.2 Vv R,, = 100 kQ to GND 438 9 +143 Vv =40°C = Ty = +125°C +135 +140 mV Short Circuit Current Limit Ise Short Circuit to GND 8 10.5 mA POWER SUPPLY Power Supply Rejection Ratio PSRR Vy = £2.25 V to +15 V 75 86 dB ~40°C = T, = +125°C 70 83 dB Supply Current Per Amp Isy Vo =0V OP292, OP492 1 l4 mA DYNAMIC PERFORMANCE Slew Rate SR Ry, =10kO 25 4 Vius —40°C = Ty = +125°C 2 3 Vins Gain Bandwidth Product GBP 4 MHz Phase Margin Oa 75 Degrees Channel Separation cs fo = 1 kHz 100 dB NOISE PERFORMANCE Voltage Noise &, PP 0.1 Hz to 10 Hz 25 LV p-p Voltage Noise Density e, f = 1kHz 15 aV/\\/Hz, Current Noise Density i, 0.7 pA Hz NOTES . ‘Input voltage range is guaranteed by CMRR tests. Specifications subject to change without notice. REV.0 -3-

WAFER TEST LIMITS (@ v, = +5. v, Vey = 2.5 V, Ty = +25°C unless otherwise noted) Parameter | Symbol Conditions Limit Units Offset Voltage Vos =600 pV max Input Bias Current Is 700 nA max Input Offset Current los 50 nA max Input Voltage Range! Vea 0/4 V min/V max Common-Mode Rejection CMRR Vem = 0V t04.0V 78 4B min Power Supply Rejection Ratio PSRR V = 44.5 Vt0 +15V 75 4B min Large Signal Voltage Gain Avo Ry = 10K2, Vo = 0.1 V 04 V 25 VimV min Output Voltage Vo Ry, = 2k0 3.8 V min Supply Current per Amp OP292, OP492 Igy Vo = 0V, Ry = Open 12 mA max NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. ‘Guaranteed by CMR test. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS' DICE CHARACTERISTICS Input Voltage? oo... 0.2 ee eee eee HIS Vito +14 V ou” ow ours Storage Temperature Range ee - Operating Temperature Range owe — |e Se f 6 NB OP292/OP492 P, So... ee ee ee eee ee. 40°C to +125°C “ Junction Temperature Range Saye te, Lear Package Type Oya" eo Units _ = | 8-Pin Plastic DIP (P) 103 4B °cw 4 14-Pin Plastic DIP (P) 83 39 scAW 8-Pin SO (S) 158 4B °cw OP292 Die Size 0.040 x 0.057 Inch, 2,280 Sq. Mils 14-Pin SO (S) 120 36 “cw, Substrate Connected to V+, Number of Transistors: Bipolar 47, MOSFET 5. NOTES ‘Absolute maximum ratings apply to both DICE and packaged parts, unless AINA oUTA ourD -IND otherwise noted. 2 1 4 13 2For supply voltages less than +36 V, the absolute maximum input voltage is Let. | we equal to the supply voltage. a Es * B ‘tals Specified for the worst case conslitions, ies 8a is specified for device in i Ka socket for P-DIP package; 8, is specified for device soldered in circuit board Br, ORDERING GUIDE a === —' a ——I WAV Model Temperature Range Package Option vb — = OP292GP —40°C to +125°C N38 wins s —4 eee EE to «nc OP292GS —40°C to +125°C S0-8 Bet ist oe OP492GP —40°C to +125°C N-14 ‘ei el bl al a) OP492GS 40°C to + 125°C SO-14 0P292/492GBC +25°C DICE te ours = oure -INc OP492 Die Size 0.057 x 0.068 Inch, 3,876 Sq. Mils Substrate Connected to V+, Number of Transistors: Bipolar 91, MOSFET 9. -4- REV.0

Figure 7. OP292 Temperature Drift (TCVos) Distribution Figure 10. OP492 Temperature Drift (TCVos) Distribution

100 P <> +

Figure 8. OP292 Open-Loop Gain vs. Temperature @ +5 V Figure 11. OP492 Open-Loop Gain vs. Temperature Figure 9. OP292 Open-Loop Gain vs. Temperature Figure 12. OP492 Open-Loop Gain vs. Temperature

8 NN Fi aX

4 FA N

Figure 19. OP292/OP492 Closed-Loop Gain/Phase vs. Figure 22. OP292/OP492 Closed-Loop Gain/Phase vs.

5 NY] 5 >:

Figure 20. OP292/OP492 CMR vs. Frequency @ +5V Figure 23. OP292/OP492 CMR vs. Frequency @ +15 V

5 PN 2 Po SN

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Figure 21. OP292/OP492 PSR vs. Frequency @ +5 V Figure 24. OP292/OP492 PSR vs. Frequency @ +15 V

Figure 25. OP292/OP492 Voy Swing vs. Temperature Figure 28. OP292/OP492 Vour Swing vs. Temperature

50 Vow = OV Sf 500 ts Vow = OV

8 Y, § [PN

Figure 26. OP292/OP492 Input Bias Current vs. Tempera- Figure 29, OP292/OP492 Input Bias Current vs. Tempera-

60 Ry = 2k 032

Figure 27. OP292/OP492 Channel Separation Figure 30. OP292/OP492 |, Current vs. Common Mode

Figure 38. A 4-Pole Bessel Low Pass Filter Using Sallen- $ Your by two cascading stages of two-pole Sallen-Key filters. . . thermistor’s nonlinearity must be corrected. This is done by for processing. back loop of the first stage amplifier. A constant operating cur- . - . thermistor. For 0°C trim, the decade box is set to 32.650k, and more stable than the feedback type AGC. 0.70 V. put. The circuit also work well with 5 V supply systems.

• OP292 SPICE Macro-model Rev. A, 6/93 * ARG / PMI * Copyright 1993 by Analog Devices * Refer to “README.DOC” file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * Node assignments * joninverting input * inverting input * positive supply * egative supply * [ output . | -SUBCKT OP292. 2 1 99 50 34 * INPUT STAGE AND POLE AT 40 MHz net 99 4 SOE-6 IOS 2 1 10E-9 CIN 1 2 = 3E-12 Qa 5 1 7 QP Q 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 RS 4° 7 966 R6 4 8 966 Cl 5 6 .995E-12 * GAIN STAGE EREF 98 0 (30,0) 1 Gl 98 9 (5,6) SOOE-6 R7 9 98 210.819E3 DI 9 10 DX D2 ul 9 Dx vi 99 «10 (6 v2 ll 50 6 * ZERO/POLE AT 6 MHz/12 MHz El 12 98 (9,30) 2 R8 122013 «21 RO 133° 98 1 C3 12. 13. 26,526E-9 * ZERO AT 15 MHz E2 14 98 (13,30) 1E6 R10 14 15 1E6 Rll 1S 98 1 C4 14 15 10.610E-15 * COMMON MODE STAGE WITH ZERO AT 40 kHz ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 + ~=1E6 R21 21 98 1 cs 20 21 3.979E-12 —14— REV.0

• POLE AT 100 MHz G2 98 16 (15,30) 1 R12 16 98 1 x * OUTPUT STAGE RSI 99 30 1K6 RS2 30 S50 1K6 ISY 99 S50 .44E-3 G 31 50 POLY(1) (16,30) —1.635E-6 4E-6 R16 31 50 «16 DCL. 50 31 DZ 2 99 32 2S0E-6 RCL 33 S50 S6 Mi 32 31 «50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 cC 31 32 ~«14E-12 Q@ 99 32 34 QNA Qt 33. 32,34 QPA Qs 31 33) «50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR= 15 IKR=1.465E-4 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) -MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + MJ=0.407 CJSW=0.SE-9 MJSW=0.33) -MODEL QP PNP(BF=61.5) .MODEL DX D .MODEL DZ D(BV=3.6) -ENDS OP292 REV.0 15-

• OP492 SPICE Macro-model Rev. A, 6/93 * ARG / PMI * Copyright 1993 by Analog Devices * Refer to “README.DOC” file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * Node assignments * oninverting input * jnverting input * ositive supply * egative supply * | [ output . | .SUBCKT OP492, 2. 1 99 50 34 * INPUT STAGE AND POLE AT 40 MHz il 99 4 SOE-6 IOS 2 1 10E-9 EOS 2 3 POLY (1) (21,30) 1.5E-3 75 CIN 1 2 3E-12 Qi Ss 1 7 QP Q 6 3 8 QP R3 5 50 2E3 R4 6 50 253 RS 4 7 966 RO 4 8 966 Cl 5 6 .995E-12 * GAIN STAGE EREF 98 0 (30,0) 1 Gl 98 9 (5,6) SO0E-6 R7 9 98 210.819E3 DI 9 10 DX D2 ll 9 DX VI 99 10 6 v2 11 50.6 * ZEROIPOLE AT 6 MHz/12 MHz El 12. 98 (9,30) 2 R8 122.013 «1 RO 3 98 1 C3 12. 13 26.526E-9 * ZERO AT 15 MHz E2 14 98 (13,30) 1E6 R10 14 1S 1E6 Rll 15 98 1 C4 14 15 10.610E-15 * COMMON MODE STAGE WITH ZERO AT 40 kHz ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 = 1E6 R21 21 98 1 cs 20 21 + 3.979E-12 -16- REV.0

• POLE AT 100 MHz G2 98 16 (15,30) 1 Ri2 16 98 1 6 16 98 1.592E-9 * OUTPUT STAGE RSI 99-30.‘ 1E6 RS2. 30. 50_—«1E6 ISY 99-50. .44B-3 G 31 50 POLY(1) (16,30) —1.635E-6 45-6 R16 31 -50_—«1E6 DCL 30 31 DZ 2 99 32 250E-6 RCL 33 50 56 M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=ISE-9 AS=1S5E-9 cC 3132s 12 Q@ 99 32 34QNA a 33 32 34 QPA @ 31 33 SOQNA -MODEL QNA NPN(S=1.19E-16 BF=253 NF=0.99 VAF= 193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) -MODEL QPA PNP(S=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) -MODEL QP PNP(BF=61.5) .MODEL DX D -MODEL DZ D(BV-3.6) .ENDS OP492 REV.0 -17-

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Dimensions shown in inches and (mm). S0-8 N-8 8-Lead Narrow-Body SOIC 8-Lead Epoxy DIP (S Suffix) (P Suffix) Af ff OC mi i oze0 710 | 0.1574 (4.00) mT 0240 (610) —( ir) os (1092 0225 @25) UHYE! oma ee : 080182 cram so] y >| be Sorenrean oe iasom sree oovoe 20 HTT UI [Hossa 1:35 PAIR A aan oe a | ae as ws ol be 0.160 14.06 (XE Joo 2019 0.00) “2 comes) Senrera coweneats oN a.ozafosss) ‘a 1eo aor0c77) \\SEATING Suremass) 284 Gout) $0-14 N-14 14-Lead Narrow-Body SOIC 14-Lead Epoxy DIP (S Suffix) (P Suffix) AAAR AAA | [" ay] F [ ecseoan TOOUUUD! Saree Soon fy ose (675) 0196.00) oz some c.8) 0195 (4.9) caereas —*| >| be eore a5 *** 5 ao 038 aris 235) CoS yy east iP ss AW 0.014 (0.356) ae) 005 (1.15) PLANE REV.0 -19-

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