OP27AZ883C

OP27GJ8 AD | Alldatasheet

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Rev. F | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

5/06—Rev. E to Rev. F 12/05—Rev. D to Rev. E 9/05—Rev. C to Rev. D 1/03—Rev. B to Rev. C 9/01—Rev. 0 to Rev. A

Rev. F | Page 3 of 20 GENERAL DESCRIPTION (Continued from Page 1) PSRR and CMRR exceed 120 dB. These characteristics, coupled with long-term drift of 0.2 μV/month, allow the circuit designer to achieve performance levels previously attained only by discrete designs. Low cost, high volume production of OP27 is achieved by using an on-chip Zener zap-trimming network. This reliable and stable offset trimming scheme has proven its effectiveness over many years of production history. The OP27 provides excellent performance in low noise, high accuracy amplification of low level signals. Applications include stable integrators, precision summing amplifiers, precision voltage threshold detectors, comparators, and professional audio circuits such as tape heads and micro- phone preamplifiers. The OP27 is a direct replacement for OP06, OP07, and OP45 amplifiers; AD741 types can be directly replaced by removing the nulling potentiometer of the AD741.

Rev. F | Page 4 of 20 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VS = ±15 V , TA = 25°C, unless otherwise noted. Table 1. OP27A/E OP27/G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE1 VOS 10 25 30 100 μV LONG-TERM VOS STABILITY2, 3 VOS/Time 0.2 1.0 0.4 2.0 μV/MO INPUT OFFSET CURRENT IOS 7 35 12 75 nA INPUT BIAS CURRENT IB ±10 ±40 ±15 ±80 nA INPUT NOISE en fO = 10 Hz 3.5 5.5 3.8 8.0 nV/√Hz Voltage Density3 fO = 30 Hz 3.1 4.5 3.3 5.6 nV/√Hz fO = 1000 Hz 3.0 3.8 3.2 4.5 nV/√Hz INPUT NOISE in fO = 10 Hz 1.7 4.0 1.7 pA/√Hz Current Density3 fO = 30 Hz 1.0 2.3 1.0 pA/√Hz fO = 1000 Hz 0.4 0.6 0.4 0.6 pA/√Hz INPUT RESISTANCE Differential Mode5 RIN 1.3 6 0.7 4 MΩ Common Mode RINCM 3 2 GΩ INPUT VOLTAGE RANGE IVR ±11.0 ±12.3 ±11.0 ±12.3 V COMMON-MODE REJECTION RATIO CMRR VCM = ±11 V 114 126 100 120 dB POWER SUPPLY REJECTION RATIO PSRR VS = ±4 V to ±18 V 1 10 2 20 μV/V LARGE SIGNAL VOLTAGE GAIN AVO RL ≥ 2 k Ω, VO = ±10 V 1000 1800 700 1500 V/mV RL ≥ 600 Ω, VO = ±10 V 800 1500 600 1500 V/mV OUTPUT VOLTAGE SWING VO RL ≥ 2 k Ω ±12.0 ±13.8 ±11.5 ±13.5 V RL ≥ 600 Ω ±10.0 ±11.5 ±10.0 ±11.5 V SLEW RATE6 SR RL ≥ 2 kΩ 1.7 2.8 1.7 2.8 V/μs GAIN BANDWIDTH PRODUCT6 GBW 5.0 8.0 5.0 8.0 MHz OPEN-LOOP OUTPUT RESISTANCE RO VO = 0, IO = 0 70 70 Ω POWER CONSUMPTION Pd VO 90 140 100 170 mW OFFSET ADJUSTMENT RANGE RP = 10 kΩ ±4.0 ±4.0 mV 1 Input offset voltage measurements are performed approximately 0.5 seconds after application of power. A/E grades guaranteed fully warmed up. 2 Long-term input offset voltage stability refers to the average trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. 3 Sample tested. 4 See voltage noise test circuit (Figure 31). 5 Guaranteed by input bias current. 6 Guaranteed by design.

Rev. F | Page 5 of 20 VS = ±15 V , −55°C ≤ TA ≤ 125°C, unless otherwise noted. Table 2. OP27A Parameter Symbol Conditions Min Typ Max Unit INPUT OFFSET VOLTAGE1 VOS 30 60 μV AVERAGE INPUT OFFSET DRIFT TCVOS2 TCVOSn3 0.2 0.6 μV/°C INPUT OFFSET CURRENT IOS 15 50 nA INPUT BIAS CURRENT IB ±20 ±60 nA INPUT VOLTAGE RANGE IVR ±10.3 ±11.5 V COMMON-MODE REJECTION RATIO CMRR VCM = ±10 V 108 122 dB POWER SUPPLY REJECTION RATIO PSRR VS = ±4.5 V to ±18 V 2 16 μV/V LARGE SIGNAL VOLTAGE GAIN AVO RL ≥ 2 kΩ, VO = ±10 V 600 1200 V/mV OUTPUT VOLTAGE SWING VO RL ≥ 2 kΩ ±11.5 ±13.5 V 1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. A/E grades guaranteed fully warmed up. 2 The TCVOS performance is within the specifications unnulled or when nulled with RP = 8 kΩ to 20 kΩ. TCVOS is 100% tested for A/E grades, sample tested for G grades. 3 Guaranteed by design. VS = ±15 V , −25°C ≤ TA ≤ 85°C for OP27J, OP27Z, 0°C ≤ TA ≤ 70°C for OP27EP , and –40°C ≤ TA ≤ 85°C for OP27GP , OP27GS, unless otherwise noted. Table 3. OP27E OP27G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT ONSET VOLTAGE VOS 20 50 55 220 μV AVERAGE INPUT OFFSET DRIFT TCVOS1 0.2 0.6 0 4 1.8 μV/°C TCVOSn2 0.2 0.6 0 4 1.8 μV/°C INPUT OFFSET CURRENT IOS 10 50 20 135 nA INPUT BIAS CURRENT IB ±14 ±60 ±25 ±150 nA INPUT VOLTAGE RANGE IVR ±10.5 ±11.8 ±10.5 ±11.8 V COMMON-MODE REJECTION RATIO CMRR VCM = ±10 V 110 124 96 118 dB POWER SUPPLY REJECTION RATIO PSRR VS = ±4.5 V to ±18 V 2 15 2 32 μV/V LARGE SIGNAL VOLTAGE GAIN AVO RL ≥ 2 kΩ, VO = ±10 V 750 1500 450 1000 V/mV OUTPUT VOLTAGE SWING VO RL ≥ 2 kΩ ±11.7 ±13.6 ±11.0 ±13.3 V 1 The TCVOS performance is within the specifications unnulled or when nulled with RP = 8 kΩ to 20 kΩ. TCVOS is 100% tested for A/E grades, sample tested for C/G grades. 2 Guaranteed by design.

Rev. F | Page 6 of 20 TYPICAL ELECTRICAL CHARACTERISTICS VS = ±15 V , TA = 25°C unless otherwise noted. Table 4. Parameter Symbol Conditions OP27N Typical Unit AVERAGE INPUT OFFSET VOLTAGE DRIFT1 TCVOS or Nulled or unnulled 0.2 μV/°C TCVOSn RP = 8 kΩ to 20 kΩ AVERAGE INPUT OFFSET CURRENT DRIFT TCIOS 80 pA/°C AVERAGE INPUT BIAS CURRENT DRIFT TCIB 100 pA/°C INPUT NOISE VOLTAGE DENSITY en fO = 10 Hz 3.5 nV/√Hz e n fO = 30 Hz 3.1 nV/√Hz e n fO = 1000 Hz 3.0 nV/√Hz INPUT NOISE CURRENT DENSITY in fO = 10 Hz 1.7 pA/√Hz i n fO = 30 Hz 1.0 pA/√Hz i n fO = 1000 Hz 0.4 pA/√Hz INPUT NOISE VOLTAGE SLEW RATE enp-p 0.1 Hz to 10 Hz 0.08 μV p-p SR RL ≥ 2 kΩ 2.8 V/μs GAIN BANDWIDTH PRODUCT GBW 8 MHz 1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.

Rev. F | Page 7 of 20 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Supply Voltage ±22 V Input Voltage1 ±22 V Output Short-Circuit Duration Indefinite Differential Input Voltage2 ±0.7 V Differential Input Current2 ±25 mA Storage Temperature Range −65°C to +150°C Operating Temperature Range OP27A (J, Z) −55°C to +125°C OP27E, ( Z) −25°C to +85°C OP27E, (P) 0°C to 70°C OP27G (P , S, J, Z) −40°C to +85°C Lead Temperature Range (Soldering, 60 sec) 300°C Junction Temperature −65°C to +150°C

1 For supply voltages less than ±22 V, the absolute maximum input voltage is

equal to the supply voltage. 2 The inputs of the OP27 are protected by back-to-back diodes. Current limiting resistors are not used in order to achieve low noise. If differential input voltage exceeds ±0.7 V, the input current should be limited to 25 mA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for device in socket for TO, CERDIP , and PDIP packages; θJA is specified for device soldered to printed circuit board for SO package. Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. Table 6. Package Type θJA θJC Unit TO-99 (J) 150 18 °C/W 8-Lead Hermetic DlP (Z) 148 16 °C/W 8-Lead Plastic DIP (P) 103 43 °C/W 8-Lead SO (S) 158 43 °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pr ecautions are recommended to avoid performance degradation or loss of functionality.

Figure 28. Short-Circuit Current vs. Time Figure 29. CMRR vs. Frequency Figure 30. Common-Mode Input Range vs. Supply Voltage Figure 31. Voltage Noise Test Circuit (0.1 Hz to 10 Hz) Figure 32. Open-Loop Voltage Gain vs. Load Resistance

1 SEC/DIV

Figure 33. Low Frequency Noise

Figure 34. PSRR vs. Frequency

Rev. F | Page 14 of 20

APPLICATION INFORMATION

OP27 series units can be inserted directly into OP07 sockets with or without removal of external compensation or nulling components. Additionally, the OP27 can be fitted to unnulled AD741-type sockets; however, if conventional AD741 nulling circuitry is in use, it should be modified or removed to ensure correct OP27 operation. OP27 offset voltage can be nulled to 0 (or another desired setting) using a potentiometer (see Figure 35). The OP27 provides stable operation with load capacitances of up to 2000 pF and ±10 V swings; larger capacitances should be decoupled with a 50 Ω resistor inside the feedback loop. The OP27 is unity-gain stable. Thermoelectric voltages generated by dissimilar metals at the input terminal contacts can degrade the drift performance. Best operation is obtained when both input contacts are maintained at the same temperature. OP27 OUTPUT RP10kΩ 00317-035 Figure 35. Offset Nulling Circuit The input offset voltage of the OP27 is trimmed at wafer level. potentiometer can be used. TCVOS is not degraded (see Figure 35). with a slight degradation (0.1 μV/°C to 0.2 μV/°C) of TCVOS. Figure 36. Offset Voltage Adjustment

• The device must be warmed up for at least five minutes. As shown in the warm-up drift curve, the offset voltage typically changes 4 μV due to increasing chip temperature after power-up. In the 10-second measurement interval, these temperature-induced effects can exceed tens-of- nanovolts.
• For similar reasons, the device has to be well-shielded from air currents. Shielding minimizes thermocouple effects.
• Sudden motion in the vicinity of the device can also feedthrough to increase the observed noise.
• The test time to measure 0.1 Hz to 10 Hz noise should not exceed 10 seconds. As shown in the noise-tester frequency response curve, the 0.1 Hz corner is defined by only one zero. The test time of 10 seconds acts as an additional zero to eliminate noise contributions from the frequency band below 0.1 Hz.
• A noise voltage density test is recommended when measuring noise on a large number of units. A 10 Hz noise voltage density measurement correlates well with a 0.1 Hz to

10 Hz p-p noise reading, since both results are determined

pulsed operation diagram (see Figure 37). parallel with Rf eliminates this problem. Figure 37. Pulsed Operation

performance of other devices in different circuit applications. the vertical scale by the square root of the bandwidth.

1 RS UNMA TCHED

2 RS MATCHED

Figure 38. Noise vs. Source Resistance (Including Resistor Noise) at 1000 Hz At RS < 1 kΩ, the low voltage noise of the OP27 is maintained. error also can be 3× the VOS spec). Figure 39. Peak-to-Peak Noise (0.1 Hz to 10 Hz) as Source Resistance between the previous two figures. Figure 40. 10 Hz Noise vs. Source Resistance (Includes Resistor Noise)

Rev. F | Page 18 of 20 Capacitor C2 and Resistor R2 form a 2 μs time constant in this circuit, as recommended for optimum transient response by the transformer manufacturer. With C2 in use, A1 must have unity- gain stability. For situations where the 2 μs time constant is not necessary, C2 can be deleted, allowing the faster OP37 to be employed. A 150 Ω resistor and R1 and R2 gain resistors connected to a noiseless amplifier generate 220 nV of noise in a 20 kHz bandwidth, or 73 dB below a 1 mV reference level. Any practical amplifier can only approach this noise level; it can never exceed it. With the OP27 and T1 specified, the additional noise degradation is close to 3.6 dB (or −69.5 referenced to 1 mV). REFERENCES 1. Lipshitz, S. R, “On RIAA Equalization Networks, ” JAES, Vol. 27, June 1979, p. 458–481. and Company, 1980. Sams and Company, 1978. February and March, 1980. 5. Otala, M., “Feedback-Generated Phase Nonlinearity in Audio Amplifiers, ” London AES Convention, March 1980, preprint 1976. 6. Stout, D. F., and Kaufman, M., Handbook of Operational Amplifier Circuit Design, New Y ork, McGraw-Hill, 1976.

Rev. F | Page 20 of 20 ORDERING GUIDE Model Temperature Range Package Description Package Option OP27AJ/883C –55° to +125°C 8-Lead Metal Can (TO-99) J-Suffix (H-08) OP27GJ –40° to +85°C 8-Lead Metal Can (TO-99) J-Suffix (H-08) OP27AZ –55° to +125°C 8-Lead CERDIP Z-Suffix (Q-8) OP27AZ/883C –55° to +125°C 8-Lead CERDIP Z-Suffix (Q-8) OP27EZ –25° to +85°C 8-Lead CERDIP Z-Suffix (Q-8) OP27GZ –40° to +85°C 8-Lead CERDIP Z-Suffix (Q-8) OP27EP 0° to +70°C 8-Lead PDIP P-Suffix (N-8) OP27EPZ1 0° to +70°C 8-Lead PDIP P-Suffix (N-8) OP27GP –40° to +85°C 8-Lead PDIP P-Suffix (N-8) OP27GPZ1 –40° to +85°C 8-Lead PDIP P-Suffix (N-8) OP27GS –40° to +85°C 8-Lead SOIC S-Suffix (R-8) OP27GS-REEL –40° to +85°C 8-Lead SOIC S-Suffix (R-8) OP27GS-REEL7 –40° to +85°C 8-Lead SOIC S-Suffix (R-8) OP27GSZ1 –40° to +85°C 8-Lead SOIC S-Suffix (R-8) OP27GSZ-REEL1 –40° to +85°C 8-Lead SOIC S-Suffix (R-8) OP27GSZ-REEL71 –40° to +85°C 8-Lead SOIC S-Suffix (R-8) OP27NBC Die 1 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00317-0-5/06(F)