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a Rail-to-Rail High Output Current Operational Amplifiers OP179/OP279 GENERAL DESCRIPTION The OP179 and OP279 are rail-to-rail, high output current, single-supply amplifiers. They are designed for low voltage applications that require either current or capacitive load drive capability. The OP179/OP279 can sink and source currents of ± 60 mA (typical) and are stable with capacitive loads to 10 nF. Applications that benefit from the high output current of the OP179/OP279 include driving headphones, displays, transform- ers and power transistors. The powerful output is combined with a unique input stage that maintains very low distortion with wide common-mode range, even in single supply designs. The OP179/OP279 can be used as a buffer to provide much greater drive capability than can usually be provided by CMOS outputs. CMOS ASICs and DAC often have outputs that can swing to both the positive supply and ground, but cannot drive more than a few milliamps. Bandwidth is typically 5 MHz and the slew rate is 3 V/µs, making these amplifiers well suited for single supply applications that require audio bandwidths when used in high gain configurations. Operation is guaranteed from voltages as low as 4.5 V, up to 12 V. Very good audio performance can be attained when using the OP179/OP279 in 5 volt systems. THD is below 0.01% with a 600 Ω load, and noise is a respectable 21 nV/√Hz. Supply current is less than 3.5 mA per amplifier. The single OP179 is available in the 5-lead SOT-23-5 package. It is specified over the industrial (–40 °C to +85 °C) tempera- ture range. The OP279 is available in 8-lead TSSOP and SO-8 surface mount packages. They are specified over the industrial (–40 °C to +85°C) temperature range. 8-Lead SOIC and TSSOP SO-8 (S) and RU-8 OP279/H11546IN A V/H11546 +IN A OUT B /H11546IN B +IN B OUT A

FEATURES

Rail-to-Rail Inputs and Outputs High Output Current: /H1155060 mA Single Supply: 5 V to 12 V Wide Bandwidth: 5 MHz High Slew Rate: 3 V/ /H9262s Low Distortion: 0.01% Unity-Gain Stable No Phase Reversal Short-Circuit Protected Drives Capacitive Loads: 10 nF

APPLICATIONS

(RT-5) 4 /H11546IN A+IN A V–OUT A OP179 8-Lead SOIC (S Suffix) OP179 /H11546IN A V/H11546 +IN A OUT A NC NC NC NC = NO CONNECT REV.G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

ELECTRICAL SPECIFICATIONS(@ VS = 5.0 V, VCM = 2.5 V, –40 /H11543C ≤ TA ≤ +85/H11543C unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage OP179 V OS VOUT = 2.5 V ± 5m V OP279 V OS VOUT = 2.5 V ± 4m V Input Bias Current I B VOUT = 2.5 V, TA = 25°C ± 300 nA VOUT = 2.5 V ± 700 nA Input Offset Current I OS VOUT = 2.5 V, TA = 25°C ± 50 nA VOUT = 2.5 V ± 100 nA Input Voltage Range V CM 05 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 5 V 56 66 dB Large Signal Voltage Gain A VO RL = 1 kΩ, 0.3 V ≤ VOUT ≤ 4.7 V 20 V/mV Offset Voltage Drift ∆VOS/∆T4 µV/°C OUTPUT CHARACTERISTICS Output Voltage High V OH IL = 10 mA Source +4.8 V Output Voltage Low V OL IL = 10 mA Sink, T A = 25°C7 5 m V IL = 10 mA Sink 100 mV Short-Circuit Limit I SC TA = 25°C ± 40 mA Output Impedance Z OUT f = 1 MHz, AV = 1 22 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V S = 4.5 V to 12 V 70 88 dB Supply Current/Amplifier I SY VOUT = 2.5 V 3.5 mA Supply Voltage Range V S +4.5 +12 V DYNAMIC PERFORMANCE Slew Rate SR R L = 1 kΩ, 1 nF 3 V/ µs Gain Bandwidth Product GBP 5 MHz Phase Margin φm 60 Degrees Capacitive Load Drive No Oscillation 10 nF AUDIO PERFORMANCE Total Harmonic Distortion THD 0.01 % Voltage Noise Density e n f = 1 kHz 22 nV/ √Hz ELECTRICAL SPECIFICATIONS(@ VS = /H115505.0 V, –40 /H11543C ≤ TA ≤ +85/H11543C unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage OP179 V OS VOUT = 0 ± 5m V OP279 V OS VOUT = 0 ± 4m V Input Bias Current I B TA = 25°C ± 300 nA ± 700 nA Input Offset Current I OS TA = 25°C ± 50 nA ± 100 nA Input Voltage Range V CM –5 +5 V Common-Mode Rejection Ratio CMRR V CM = –5 V to +5 V 56 66 dB Large Signal Voltage Gain A VO RL = 1 kΩ, –4.7 V ≤ VOUT ≤ 4.7 V 20 V/mV Offset Voltage Drift ∆VOS/∆T3 µV/°C OUTPUT CHARACTERISTICS Output Voltage High V OH IL = 10 mA Source +4.8 V Output Voltage Low V OL IL = 10 mA Sink –4.85 V Short Circuit Limit I SC TA = 25°C ± 50 mA Open-Loop Output Impedance Z OUT f = 1 MHz, AV = +1 22 Ω POWER SUPPLY Supply Current/Amplifier I SY VS = ±6 V, VOUT = 0 V 3.75 mA DYNAMIC PERFORMANCE Slew Rate SR R L = 1 kΩ, 1 nF 3 V/ µs Full-Power Bandwidth BW p 1% Distortion kHz Gain Bandwidth Product GBP 5 MHz Phase Margin φm 69 Degrees NOISE PERFORMANCE Voltage Noise e n p-p 0.1 Hz to 10 Hz 2 µV p-p Voltage Noise Density e n f = 1 kHz 22 nV/ √Hz Current Noise Density i n 1 pA/√Hz Specifications subject to change without notice. OP179/OP279–SPECIFICATIONS –2– REV. G

–3–REV. G ABSOLUTE MAXIMUM RATINGS Storage Temperature Range Operating Temperature Range Junction Temperature Range CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP179/OP279 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Package Temperature Range Package Description Package Option Brand Code OP179GRT –40 °C to +85°C 5-Lead SOT-23 RT-5 A2G OP279GS –40 °C to +85°C 8-Lead SOIC SO-8 OP279GRU –40 °C to +85°C 8-Lead TSSOP RU-8 WARNING! ESD SENSITIVE DEVICE Package Types /H9258JA 2 /H9258JC Unit 5-Lead SOT-23 (RT) 256 81 °C/W 8-Lead SOIC (S) 158 43 °C/W 8-Lead TSSOP (RU) 240 43 °C/W NOTES 1The inputs are clamped with back-to-back diodes. If the differential input voltage exceeds 1 volt, the input current should be limited to 5 mA. 2θJA is specified for the worst-case conditions, i.e., θJA is specified for device soldered in circuit board for SOIC packages.

–4– REV. G 160 2.5 –2.5 100 120 140 1.50.5–0.5–1.5 INPUT OFFSET – mV UNITS VS /H11549 5V TA /H11549 25/H11543C 620 /H11547 OP AMPS TPC 1. Input Offset Distribution COMMON-MODE VOLTAGE – Volts OFFSET VOLTAGE – mV 3.0 1.5 0.5 1.0 2.5 2.0 432 VS /H11549 5V TA /H11549 25/H11543C TPC 4. Offset Voltage vs. Common-Mode Voltage 1000 100 600 200 –25 400 –50 800 7550250 TEMPERATURE – /H11543C RL /H11549 2k/H9024 RL /H11549 1k/H9024 OPEN-LOOP GAIN – V/mV VS /H11549 15V 0.3 VOUT 4.7V TPC 7. Open-Loop Gain vs. Temperature VS /H11549 5V VCM /H11549 2.5V 40 100 –25 –50 7550250 TEMPERATURE – /H11543C –ISC SHORT-CIRCUIT CURRENT – mA +ISC TPC 2. Short-Circuit Current vs. Temperature VS /H11549 /H115505V 100 50 100 –25 –50 7550250 TEMPERATURE – /H11543C SHORT-CIRCUIT CURRENT – mA –ISC +ISC TPC 5. Short-Circuit Current vs. Temperature 100 –25 –50 7550250 TEMPERATURE – /H11543C SLEW RATE – V/H11408/H9262s VS /H11549 5V RL /H11549 1k/H9024 CL /H11549 +1nF +EDGE –EDGE TPC 8. Slew Rate vs. Temperature 400 –400 –200 –300 –100 100 200 300 432 +85/H11543C +25/H11543C COMMON-MODE VOLTAGE – Volts INPUT BIAS CURRENT – nA VS /H11549 5V –40/H11543C TPC 3. Input Bias Current vs. Common-Mode Voltage COMMON-MODE VOLTAGE – Volts 0 5 432 BANDWIDTH – MHz VS /H11549 5V TA /H11549 25/H11543C TPC 6. Bandwidth vs. Common-Mode Voltage PHASE GAIN –40 100 1k 10M 1M100k10k 100 –20 –90 135 180 225 –45 FREQUENCY – Hz OPEN-LOOP GAIN – dB PHASE – Degrees 120 270 VS /H115502.5V TA –40/H11543C RL /H11549 2k/H9024 TPC 9. Open-Loop Gain and Phase vs. Frequency –Typical Performance Characteristics

–5–REV. G VS /H11549 5V VCM /H11549 2.5V 6.5 4.0 100 5.5 4.5 –25 5.0 –50 6.0 7550250 TEMPERATURE – /H11543C SUPPLY CURRENT – mA VS /H11549 /H115506V VS /H11549 /H115505V TPC 10. Supply Current vs. Temperature FREQUENCY – Hz POWER SUPPLY REJECTION – dB 120 10 100 10M 1M100k10k1k 100 VS /H115502.5V TA /H11549 25/H11543C –PSRR +PSRR TPC 13. Power Supply Rejection vs. Frequency 10k 10M 1M100k1k FREQUENCY – Hz MAXIMUM OUTPUT SWING – Volts TA /H11549 25/H11543C VS /H11549 /H115505V AVCL /H11549 +1 RL 1k/H9024 TPC 16. Maximum Output Swing vs. Frequency 100 –25 –50 7550250 TEMPERATURE – /H11543C SLEW RATE – V//H9262s VS /H11549 /H115505V RL /H11549 1k/H9024 CL /H11549 +1nF +EDGE –EDGE TPC 11. Slew Rate vs. Temperature 10k 10M1M100k1k FREQUENCY – Hz MAXIMUM OUTPUT SWING – Volts TA /H11549 25/H11543C VS /H11549 /H115502.5V AVCL /H11549 +1 RL 1k/H9024 TPC 14. Maximum Output Swing vs. Frequency –30 1k 10k 100M 10M1M100k –20 –10 FREQUENCY – Hz CLOSED-LOOP GAIN – dB AVCL /H11549 +100 AVCL /H11549 +10 AVCL /H11549 +1 VS /H115502.5V TA /H11549 25/H11543C RL 1k/H9024 TPC 17. Closed-Loop Gain vs. Frequency PHASE GAIN 120 –40 100 1k 10M 1M100k10k 100 –20 270 –90 135 180 225 –45 FREQUENCY – Hz OPEN-LOOP GAIN – dB PHASE – Degrees VS /H115502.5V TA –40/H11543C RL /H11549 2k/H9024 CL /H11549 500pF TPC 12. Open-Loop Gain and Phase vs. Frequency 180 160 140 120 100 10 100 10M 1M100k10k1k TA /H11549 25/H11543C VS /H11549 /H115502.5V OR /H115505V FREQUENCY – Hz IMPEDANCE – /H9024 AVCL /H11549 1 AVCL /H11549 10 OR 100 TPC 15. Closed-Loop Output Impedance vs. Frequency 0 10k 8k6k4k2k LOAD CAPACITANCE – pF OVERSHOOT – % TA /H11549 25/H11543C AVCL /H11549 +1 RL 1k/H9024 VS /H115502.5V VIN /H11549 100mV p-p POSITIVE EDGE AND NEGATIVE EDGE TPC 18. Small Signal Overshoot vs. Load Capacitance

circuit design techniques are used. Figure 1. OP179/OP279 Equivalent Input Circuit TPC 19. Voltage Noise Density vs. TPC 20. Voltage Noise Density vs.

Figure 10. A Single-Supply Direct Access Arrangement for

2.5 V output across R1, it provides a 20 mA drive to the 350 Ω

compression in the application can be measured by the circuit. Figure 11. A Single-Supply, Remote Strain Gage Signal the AMP04’s input to provide differential-mode noise rejection. line driver applications without changing the circuit gain of 1. noninverting, inverting, or differential operation. Figure 12. A Single-Supply, Balanced Line Driver for

–14– REV. G References on Active Filters and Active Crossover Networks RC Active Filters,” IRE Transactions on Circuit Theory , Vol. CT-2, March 1955. Design of Active Filters , McGraw-Hill, 1980. 3. Zumbahlen, H., “Chapter 6: Passive and Active Analog Filtering,” within 1992 Analog Devices Amplifier Applications Guide. 4. Zumbahlen, H., “Speaker Crossovers,” within Chapter 8 of 1993 Analog Devices System Applications Guide. 5. Linkwitz, S., “Active Crossover Networks for Noncoincident Drivers,” JAES, Vol. 24, #1, Jan/Feb 1976. The crossover example frequency of 500 Hz can be shifted lower or higher by frequency scaling of either resistors or capacitors. In configuring the circuit for other frequencies, complementary LP/ HP action must be maintained between sections, and component values within the sections must be in the same ratio. Table II provides a design aid to adaptation, with suggested standard component values for other frequencies. Table II. RC Component Selection for Various Crossover Frequencies R1/C1 (U1A)* Crossover Frequency (Hz) R5/C3 (U1B) 100 160 k Ω/0.01 µF 200 80.6 k Ω/0.01 µF 319 49.9 k Ω/0.01 µF 500 31.6 k Ω/0.01 µF 1 k 16 k Ω/0.01 µF 2 k 8.06 k Ω/0.01 µF 5 k 3.16 k Ω/0.01 µF 10 k 1.6 k Ω/0.01 µF Table notes (applicable for α = 2). For SK stage U1A: R1 = R2, and C1 = C2, etc. ** For MFB stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3.

–15–REV. G R10 16 98 10 C3 15 16 15.915E-12 * ZERO AT 1.5 MHz E1 14 98 (9,39) 1E6 R5 14 18 1E6 R6 18 98 1 C4 14 18 106.103E-15 * BIAS CURRENT-VS-COMMON-MODE VOLTAGE EP 97 0 (99,0) 1 EN 51 0 (50,0) 1 V3 20 21 1.6 V4 22 23 2.8 R12 97 20 530 R13 23 51 1E3 D13 15 21 DX D14 22 15 DX FIB 98 24 POLY(2) V3 V4 0 –1 1 RIB 24 98 10E3 E3 97 25 POLY(1) (99,39) –1.63 1 E4 26 51 POLY(1) (39,50) –2.73 1 D15 24 25 DX D16 26 24 DX * POLE AT 6 MHz G6 98 40 (18,39) 1E 6 R20 40 98 1E6 C10 40 98 26.526E-15 * OUTPUT STAGE RS1 99 39 6.0345E3 RS2 39 50 6.0345E3 RO1 99 45 40 RO2 45 50 40 G7 45 99 (99,40) 25E-3 G8 50 45 (40,50) 25E-3 G9 98 60 (45,40) 25E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 1.711E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 1.54 V6 42 40 1.54 .MODEL DX D() .MODEL DZ D(IS=1E-6) .MODEL QN NPN(BF=300) .ENDS OP179/OP279 Spice Macro Model * OP179/OP279 SPICE Macro Model Rev. A, 5/94 * ARG / ADI * Copyright 1994 by Analog Devices * Refer to “README.DOC” file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * Node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply .SUBCKT OP179/OP279 3 2 99 50 45 * INPUT STAGE AND POLE AT 6 MHz I1 1 50 60.2E-6 Q1 5 2 7 QN Q2 6 4 8 QN D1 4 2 DX D2 2 4 DX R1 1 7 1.628E3 R2 1 8 1.628E3 R3 5 99 2.487E3 R4 6 99 2.487E3 C1 5 6 5.333E-12 EOS 4 3 POLY(1) (16,39) 0.25E-3 50.118 IOS 2 3 5E-9 GB1 2 98 (24,98) 100E-9 GB2 4 98 (24,98) 100E-9 CIN 2 3 1E-12 * GAIN STAGE AND DOMINANT POLE AT 16 Hz EREF 98 0 (39,0) 1 G1 98 9 (5,6) 402.124E-6 R7 9 98 497.359E6 C2 9 98 20E-12 V1 99 10 0.58 V2 11 50 0.47 D5 9 10 DX D6 11 9 DX * COMMON-MODE STAGE WITH ZERO AT 10 kHz ECM 15 98 POLY(2) (3,39) (2,39) 0 0.5 0.5 R9 15 16 1E6

–16– REV. G OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C00290–0–1/02(G) PRINTED IN U.S.A. 8-Lead TSSOP (RU-8) 8 5 0.122 (3.10) 0.114 (2.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 0.0256 (0.65) BSC SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8/H11543 0/H11543 8-Lead Narrow-Body SO (SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 5-Lead SOT-23 (RT-5) 0.0079 (0.200) 0.0035 (0.090) 0.0236 (0.600) 0.0039 (0.100) 10/H11543 0/H115430.0197 (0.500) 0.0118 (0.300) 0.0590 (0.150) 0.0000 (0.000) 0.0512 (1.300) 0.0354 (0.900) SEATING PLANE 0.0571 (1.450) 0.0354 (0.900) 0.1220 (3.100) 0.1063 (2.700) PIN 1 0.0709 (1.800) 0.0590 (1.500) 0.1181 (3.000) 0.0984 (2.500) 1 3 4 5 0.0748 (1.900) REF 0.0374 (0.950) REF NOTE: PACKAGE OUTLINE INCLUSIVE AS SOLDER PLATING.

Revision History

Data Sheet changed from REV. F to REV. G.