OP275

OP275 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Dual Bipolar/JFET, Audio Operational Amplifier OP275* PIN CONNECTIONS 8-Lead Narrow-Body SO 8-Lead Epoxy DIP (S Suffix) (P Suffix) OP275 OUT A –IN A +IN A OUT B –IN B +IN B V+1 4 5 OP275 OUT B –IN B +IN B V+OUT A –IN A +IN A Improved dc performance is also provided with bias and offset currents greatly reduced over purely bipolar designs. Input off- set voltage is guaranteed at 1 mV and is typically less than 200 mV. This allows the OP275 to be used in many dc coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. The output is capable of driving 600 W loads to 10 V rms while maintaining low distortion. THD + Noise at 3 V rms is a low 0.0006%. The OP275 is specified over the extended industrial (–40 °C to +85°C) temperature range. OP275s are available in both plastic DIP and SOIC-8 packages. SOIC-8 packages are available in 2500 piece reels. Many audio amplifiers are not offered in SOIC-8 surface mount packages for a variety of reasons; how- ever, the OP275 was designed so that it would offer full perfor- mance in surface mount packaging. GENERAL DESCRIPTION The OP275 is the first amplifier to feature the Butler Amplifier front-end. This new front-end design combines both bipolar and JFET transistors to attain amplifiers with the accuracy and low noise performance of bipolar transistors, and the speed and sound quality of JFETs. Total Harmonic Distortion plus Noise equals that of previous audio amplifiers, but at much lower sup- ply currents. A very low l/f corner of below 6 Hz maintains a flat noise density response. Whether noise is measured at either 30 Hz or 1 kHz, it is only 6 nV/Ö Hz. The JFET portion of the input stage gives the OP275 its high slew rates to keep distortion low, even when large output swings are required, and the 22 V/ ms slew rate of the OP275 is the fastest of any standard audio amplifier. Best of all, this low noise and high speed are accomplished using less than 5 mA of supply current, lower than any standard audio amplifier. *Protected by U.S. Patent No. 5,101,126. © Analog Devices, Inc., 1995 Tel: 617/329-4700 Fax: 617/326-8703

FEATURES

Excellent Sonic Characteristics Low Noise: 6 nV/ ÖHz Low Distortion: 0.0006% High Slew Rate: 22 V/ ms Wide Bandwidth: 9 MHz Low Supply Current: 5 mA Low Offset Voltage: 1 mV Low Offset Current: 2 nA Unity Gain Stable

APPLICATIONS

ELECTRICAL CHARACTERISTICS

Parameter␣ Symbol Conditions Min Typ Max Units AUDIO PERFORMANCE␣ THD + Noise V IN = 3 V rms, RL = 2 kW , f = 1 kHz 0.006 % Voltage Noise Density e n f = 30 Hz 7 nV/ ÖHz f = 1 kHz 6 nV/ ÖHz Current Noise Density i n f = 1 kHz 1.5 pA/ ÖHz Headroom THD + Noise £ 0.01%, RL = 2 kW , VS = – 18 V >12.9 dBu INPUT CHARACTERISTICS␣ Offset Voltage V OS 1m V Input Bias Current I B VCM = 0 V 100 350 nA VCM = 0 V, –40°C £ TA £ +85°C 100 400 nA Input Offset Current I OS VCM = 0 V 2 50 nA VCM = 0 V, –40°C £ TA £ +85°C 2 100 nA Input Voltage Range V CM –10.5 +10.5 V Common-Mode Rejection Ratio CMRR V CM = – 10.5 V, –40°C £ TA £ +85°C 80 106 dB Large Signal Voltage Gain A VO RL = 2 kW 250 V/mV RL = 2 kW , –40°C £ TA £ +85°C 175 V/mV RL = 600 W 200 V/mV Offset Voltage Drift DVOS/DT2 mV/°C OUTPUT CHARACTERISTICS␣ Output Voltage Swing V O RL = 2 kW –13.5 – 13.9 +13.5 V RL = 600 W , VS = – 18 V +14, –16 V POWER SUPPLY␣ Power Supply Rejection Ratio PSRR V S = – 4.5 V to – 18 V 85 111 dB VS = – 4.5 V to – 18 V, –40°C £ TA £ +85°C8 0 d B Supply Current I SY VS = – 4.5 V to – 18 V, VO = 0 V, VS = – 22 V, VO = 0 V, RL = ¥ , Supply Voltage Range V S – 4.5 – 22 V DYNAMIC PERFORMANCE␣ Slew Rate SR R L = 2 kW 15 22 V/ ms Full-Power Bandwidth BW P kHz Gain Bandwidth Product GBP 9 MHz Phase Margin ø m 62 Degrees Overshoot Factor V IN = 100 mV, AV = +1, RL = 600 W , CL = 100 pF 10 % Specifications subject to change without notice. REV. A–2– OP275–SPECIFICATIONS (@ VS = 615.0 V, TA = +258C unless otherwise noted)

REV. A –3– Parameter Symbol Conditions Limit Units Offset Voltage V OS 1m V m a x Input Bias Current I B VCM = 0 V 350 nA max Input Offset Current I OS VCM = 0 V 50 nA max Input Voltage Range 1 VCM – 10.5 V min Common-Mode Rejection Ratio CMRR V CM = – 10.5 V 80 dB min Power Supply Rejection Ratio PSRR V = – 4.5 V to – 18 V 85 dB min Large Signal Voltage Gain A VO RL = 2 kW 250 V/mV min Output Voltage Range V O RL = 10 kW– 13.5 V min Supply Current I SY VO = 0 V, RL = ¥ 5 mA max NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and test ing. 1Guaranteed by CMRR test. Specifications subject to change without notice. WAFER TEST LIMITS(@ VS = 615.0 V, TA = +258C unless otherwise noted) ABSOLUTE MAXIMUM RATINGS 1 Storage Temperature Range Operating Temperature Range Junction Temperature Range Package Type qJA 4 qJC Units 8-Pin Plastic DIP (P) 103 43 °C/W 8-Pin SOIC (S) 158 43 °C/W NOTES 1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2For supply voltages greater than – 22 V, the absolute maximum input voltage is equal to the supply voltage. 3Shorts to either supply may destroy the device. See data sheet for full details. 4qJA is specified for the worst case conditions, i.e., qJA is specified for device in socket for cerdip, P-DIP, and LCC packages; qJA is specified for device soldered in circuit board for SOIC package. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP275 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model Temperature Range Package Option OP275GP –40 °C to +85°C 8-Pin Plastic DIP OP275GS –40 °C to +85°C 8-Pin SOIC OP275GSR –40 °C to +85°C SO-8 Reel, 2500 pcs. OP275GBC +25 °C DICE DICE CHARACTERISTICS Die Size 0.070 · 0.108 in. (7,560 sq. mils) Substrate is connected to V–

OP275–Typical Performance Curves REV. A–4– SUPPLY VOLTAGE – V OUTPUT VOLTAGE SWING – V –25 –10 –15 –20 TA = +25°C RL = 2kW +VOM –VOM Output Voltage Swing vs. Supply Voltage FREQUENCY – Hz 1M 10M10k 100k PHASE – Degrees 135 –45 –90 –20 –10 GAIN – dB VS = –15V TA = +25°C MARKER 15 309.059Hz MAG (A/H) 60.115dB MARKER 15 309.058Hz PHASE (A/R 90.606Deg Open-Loop Gain, Phase vs. Frequency FREQUENCY – Hz 120 100 100 1k 10M 10k 100k 1M VS = –15V TA = +25°C COMMON-MODE REJECTION – dB Common-Mode Rejection vs. Frequency TEMPERATURE – °C OPEN-LOOP GAIN – V/mV 1500 –50 –25 100 02 55 0 7 5 1250 1000 750 500 250 VS = –15V VO = –10V +GAIN RL = 2kW –GAIN RL = 2kW +GAIN RL = 600W –GAIN RL = 600W Open-Loop Gain vs. Temperature FREQUENCY – Hz CLOSED-LOOP GAIN – dB –301k 10k 100M 100k 1M 10M –10 –20 VS = –15V TA = +25°C AVCL = +100 AVCL = +10 AVCL = +1 Closed-Loop Gain vs. Frequency FREQUENCY – Hz 120 100 10 100 1M 1k 10k 100k POWER SUPPLY REJECTION – dB VS = –15V TA = +25°C +PSRR –PSRR Power Supply Rejection vs. Frequency FREQUENCY – Hz 1M 10M10k 100k PHASE – Degrees 180 135 –180 –45 –90 –135 –40 –10 –20 –30 GAIN – dB VS = –15V TA = +25°C Closed-Loop Gain and Phase, A V = +1 FREQUENCY – Hz IMPEDANCE – W 100 1k 10M 10k 100k 1M VS = –15V TA = +25°C AVCL = +1 AVCL = +10 AVCL = +100 Closed-Loop Output Impedance vs. Frequency FREQUENCY – Hz 100 –60 1k 10k 100M 100k 1M 10M –20 –40 PHASE – Degrees 135 180 225 270 VS = –15V RL = 2kW TA = +25°C OPEN-LOOP GAIN – dB GAIN PHASE Øm = 58° Open-Loop Gain, Phase vs. Frequency

REV. A –5– LOAD CAPACITANCE – pF 100OVERSHOOT – % 0 100 500 200 300 400 AVCL = +1 NEGATIVE EDGE AVCL = +1 POSITIVE EDGE VS = –15V RL = 2kW VIN = 100mV p-p Small-Signal Overshoot vs. Load Capacitance SUPPLY VOLTAGE – V 5.0SUPPLY CURRENT – mA 4.5 3.00 –5 –25–10 –15 4.0 3.5 –20 TA = +25°C TA = –40°C TA = +85°C Supply Current vs. Supply Voltage FREQUENCY – Hz 10 100 100k 1k

1 CURRENT NOISE DENSITY – pA/ Hz

V = –15V T = +25°C S A Current Noise Density vs. Frequency 100 1k 10k LOAD RESISTANCE – W TA = +25°C VS = –15V +VOM ‰–VOM ‰ MAXIMUM OUTPUT SWING – V Maximum Output Voltage vs. Load Resistance TEMPERATURE – °C ABSOLUTE OUTPUT CURRENT – mA 120 –50 –25 100 02 5 5 0 7 5 110 100 VS = –15V SINK SOURCE Short Circuit Current vs. Temperature TCV OS – µV/°C UNITS 500 400 01 1 0 234 5 67 89 300 200 100 BASED ON 920 OP AMPS VS = –15V –40°C to +85°C TCVOS Distribution TEMPERATURE – °C GAIN BANDWIDTH PRODUCT – MHz –50 –25 100 02 55 0 7 5 PHASE MARGIN – Degrees GBW Ø m Gain Bandwidth Product, Phase Margin vs. Temperature FREQUENCY – Hz MAXIMUM OUTPUT SWING – V 1k 10k 10M 100k 1M TA = +25°C VS = –15V AVCL = +1 RL = 2kW Maximum Output Swing vs. Frequency TEMPERATURE – °C 300INPUT BIAS CURRENT – nA –50 –25 100 02 55 0 7 5 250 200 150 100 VS = –15V Input Bias Current vs. Temperature

INPUT OFFSET VOLTAGE – µV UNITS 200 160 –500–400 500–300–200–100 0 100 200 300 400 120 BASED ON 920 OP AMPS VS = –15V TA = +25°C Input Offset (VOS) Distribution SETTLING TIME – ns STEP SIZE – V –10 0 100 900 200 300 400 500 600 700 800 +0.1% +0.01% –0.1% –0.01% Settling Time vs. Step Size +SR –SR CAPACITIVE LOAD – pF SLEW RATE – V/µs 0 100 500 200 300 400 TA = +25°C VS = –15V Slew Rate vs. Capacitive Load 100 200ns5V Negative Slew Rate RL = 2 kW , VS = –15 V, AV = +1 100 100ns50mV Small Signal Response RL = 2 kW , VS = –15 V, AV = +1 100 200ns5V Positive Slew Rate RL = 2 kW , VS = –15 V, AV = +1 2.5 kHz0 Hz CH A: 80.0 µV FS 10.0 µV/DIV MKR: 6.23 nV/ÖHz BW: 15.0 MHzMKR: 1 000 Hz Voltage Noise Density vs. Frequency VS = –15 V OP275–Typical Performance Curves REV. A–6– DIFFERENTIAL INPUT VOLTAGE – V 15SLEW RATE – V/µs VS = –15V RL = 2kW TA = +25°C Slew Rate vs. Differential Input Voltage TEMPERATURE – °C SLEW RATE – V/µs –50 –25 100 02 55 0 7 5 –SR +SR VS = –15V RL = 2kW Slew Rate vs. Temperature

REV. A –7– The OP275 has been designed with inherent short circuit pro- tection to ground. An internal 30 W resistor, in series with the output, limits the output current at room temperature to I SC + = 40 mA and ISC– = –90 mA, typically, with – 15 V supplies. However, shorts to either supply may destroy the device when excessive voltages or currents are applied. If it is possible for a user to short an output to a supply, for safe operation, the out- put current of the OP275 should be design-limited to – 30 mA, as shown in Figure 1. Total Harmonic Distortion Total Harmonic Distortion + Noise (THD + N) of the OP275 is well below 0.001% with any load down to 600 W . However, this is dependent upon the peak output swing. In Figure 2 it is seen that the THD + Noise with 3 V rms output is below 0.001%. In the following Figure 3, THD + Noise is below 0.001% for the 10 kW and 2 kW loads but increases to above 0.1% for the 600␣W load condition. This is a result of the output swing capability of the OP275. Notice the results in Figure 4, showing THD vs. V IN (V rms). This figure shows that the THD + Noise remains very low until the output reaches 9.5 volts rms. This performance is similar to competitive products. R FB FEEDBACK R X 332W A1 VOUT A1 = 1/2 OP275 Figure 1. Recommended Output Short Circuit Protection Figure 2. THD + Noise vs. Frequency vs. R LOAD Figure 3. THD + Noise vs. R LOAD; VIN =10 V rms, Figure 4. Headroom, THD + Noise vs. Output Amplitude will occur and distortion will be very high. Figure 5. THD + Noise vs. Supply Voltage OP275 with a 1/f corner at 2.24 Hz.

10 Hz0 Hz

Figure 6. 1/f Noise Corner, V S = –15 V, AV = 1000

REV. A –11– OP275 SPICE Model * Node assignments * noninverting input * inverting input * positive supply * negative supply * output .SUBCKT OP275 1 2 99 50 34 * INPUT STAGE & POLE AT 100 MHz R3 5 51 2.188 R4 6 51 2.188 CIN 1 2 3.7E-12 CM1 1 98 7.5E-12 CM2 2 98 7.5E-12 C2 5 6 364E-12 I1 97 4 100E-3 IOS 1 2 1E-9 EOS 9 3 POLY(1) 26 28 0.5E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 1.672 R6 8 4 1.672 D1 2 36 DZ D2 1 36 DZ EN 3 1 10 0 1 GN1 0 2 13 0 1E-3 GN2 0 1 16 0 1E-3 EREF 98 0 28 0 1 EP 97 0 99 0 1 EM 51 0 50 0 1 * VOLTAGE NOISE SOURCE DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * CURRENT NOISE SOURCE DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 * CURRENT NOISE SOURCE DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 * GAIN STAGE & DOMINANT POLE AT 32 Hz R7 18 98 1.09E6 C3 18 98 4.55E-9 G1 98 18 5 6 4.57E-1 V2 97 19 1.35 V3 20 51 1.35 D3 18 19 DX D4 20 18 DX * POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz R8 21 98 1E-3 R9 21 22 1.25E-3 C4 22 98 47.2E-12 G2 98 21 18 28 1E-3 * POLE AT 100 MHz R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 21 28 1 * POLE AT 100 MHz R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 23 28 1 * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz R12 25 26 1E6 C7 25 26 1.5915E-12 R13 26 98 1 E2 25 98 POLY(2) 1 98 2 98 0 2.50 2.50 * POLE AT 100 MHz R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 24 28 1 * OUTPUT STAGE R15 28 99 100E3 R16 28 50 100E3 C9 28 50 1E-6 ISY 99 50 1.85E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 27 29 10E-3 G7 33 50 29 27 10E-3 G8 29 99 99 27 10E-3 G9 50 29 27 50 10E-3 V4 30 29 1.3 V5 29 31 3.8 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * MODELS USED .MODEL QX PNP(BF=5E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1) .ENDS

REV. A–12– PRINTED IN U.S.A. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Narrow-Body SOIC (S Suffix) 0.1968 (5.00) 0.1890 (4.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 8-Lead Epoxy DIP (P Suffix) 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) C1652a–2–7/95