OP271AZ

OP271_02 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a OP271 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 PIN CONNECTIONS 16-Pin SOL (S-Suffix) Epoxy Mini-DIP (P-Suffix) 8-Pin Hermetic DIP (Z-Suffix) OUT A –IN A OUT B –IN B+IN A +IN BV– +– + – BA NC = NO CONNECT NC –IN A NC +IN A NC NC OUT B NC –IN B NC OUT A V+V– NC +IN B NC High-Speed, Dual Operational Amplifier

FEATURES

Excellent Speed: 8.5 V/ ms Typ Fast Settling (0.01%): 2 ms Typ Unity-Gain Stable High-Gain Bandwidth: 5 MHz Typ Low Input Offset Voltage: 200 mV Max Low Offset Voltage Drift: 21 mV/∞C Max High Gain: 400 V/mV Min Outstanding CMR: 106 dB Min Industry Standard 8-Pin Dual Pinout Available in Die Form GENERAL DESCRIPTION The OP271 is a unity-gain stable monolithic dual op amp featuring excellent speed, 8.5 V/ ms typical, and fast settling time, 2 ms typical to 0. 01%. The OP271 has a gain bandwidth of 5 MHz with a high phase margin of 62 ∞. Input offset voltage of the OP271 is under 200 mV with input offset voltage drift below 2 mV/∞C, guaranteed over the full military temperature range. Open-loop gain exceeds 400,000 into a 10 k W load ensuring outstanding gain accuracy and linearity. The input bias current is under 20 nA limiting errors due to source resistance. The OP271’s outstanding CMR, over 106 dB, and low PSRR, under 5.6 mV/V, reduce errors caused by ground noise and power supply fluctuations. In addition, the OP27l exhibits high CMR and PSRR over a wide frequency range, further improving system accuracy. Figure 1. Simplified Schematic

REV. A–2– OP271–SPECIFICATIONS (VS = ±15 V, TA = 25∞C, unless otherwise noted.)ELECTRICAL CHARACTERISTICS OP271A/E OP271F OP271G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE V OS 75 200 150 300 200 400 mV INPUT OFFSET CURRENT I OS VCM = 0 V 1 10 4 15 7 20 nA INPUT BIAS CURRENT I B VCM = 0 V 4 20 6 40 12 60 nA INPUT NOISE VOLTAGE DENSITY e n fO = 1 kHz 7.6 7.6 7.6 nV/Hz LARGE-SIGNAL V O = ±10 V VOLTAGE A VO RL = 10 kW 400 650 300 500 250 400 V/mV GAIN R L = 2 kW 300 500 200 300 175 250 V/mV INPUT VOLTAGE RANGE IVR ±12 ±12.5 ±12 ±12.5 ±12 ±12.5 V OUTPUT VOLTAGE SWING V O RL ≥ 2 kW± 12 ±13 ±12 ±13 ±12 ±13 V COMMON-MODE REJECTION CMR V CM = ±12 V 106 120 100 115 90 105 dB POWER SUPPLY RATIO to ±18 V PHASE MARGIN u m AV = +1 62 62 62 degrees SUPPLY CURRENT GAIN BANDWIDTH PRODUCT GBW 5 5 5 MHz CHANNEL CS V O = 20 Vp-p 125 175 125 175 175 dB SEPARATION f O = 10 Hz 125 175 125 175 175 dB INPUT CAPACITANCE C IN 33 3 p F INPUT RESISTANCE DIFFERENTIAL- MODE R IN 0.4 0.4 0.4 M W INPUT RESISTANCE COMMON MODE R INCM 20 20 20 G W SETTLING TIME t S AV = +1,

10 V Step

to 0.01% 2 2 2 ms NOTES 1Guaranteed by CMR test. 2Guaranteed but not 100% tested.

REV. A –3– OP271

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Unit INPUT OFFSET VOLTAGE V OS 115 400 mV AVERAGE INPUT OFFSET VOLTAGE DRIFT TCV OS 0.4 2 mV/∞C INPUT OFFSET CURRENT I OS VCM = 0 V 1.5 30 nA INPUT BIAS CURRENT IB V CM = 0 V 7 60 nA LARGE-SIGNAL VOLTAGE A VO VO = ±10 V GAIN R L = 10 kW 300 600 V/mV RL = 2 kW 200 500 V/mV INPUT VOLTAGE RANGE1 IVR ±12 ±12.5 V OUTPUT VOLTAGE SWING V O RL ≥ 2 kW± 12 ±13 V COMMON-MODE REJECTION CMR V CM = ±12 V 100 120 dB POWER SUPPLY REJECTION RATIO PSRR V S = ±4.5 V to ±18 V 1.0 5.6 mV/V SUPPLY CURRENT (ALL AMPLIFIERS) I SY No Load 5.3 75 mA NOTE 1Guaranteed by CMR test. Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE V OS 100 330 215 560 300 700 mV AVERAGE INPUT OFFSET VOLTAGE DRIFT TCV OS 0.4 2 1 4 2.0 5 mV/∞C INPUT OFFSET CURRENT I OS VCM = 0 V 1 30 5 40 15 50 nA INPUT BIAS CURRENT I B VCM = 0 V 6 60 10 70 15 80 nA LARGE-SIGNAL A VO VO = ± 10 V VOLTAGE GAIN R L = 10 kW 300 600 200 500 150 400 V/mV RL = 2 kW 200 500 100 400 90 300 V/mV INPUT VOLTAGE RANGE1 IVR ±12 ±12.5 ±12 ±12.5 ±12 ±12.5 V OUTPUT VOLTAGE SWING V O RL ≥ 2 kW± 12 ±13 ±12 ±13 ±12 ±13 V COMMON-MODE REJECTION CMR V CM = ±12 V 100 120 94 115 90 100 dB POWER SUPPLY RATIO to ±18 V SUPPLY CURRENT NOTE 1Guaranteed by CMR test. (VS = ±15 V, –55 ∞C £ TA £ 125∞C for OP271A, unless otherwise noted.) (VS = ±15 V, –40 ∞C £ TA £ +85∞C, unless otherwise noted.)

REV. A OP271 –4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP271 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE (Continued from Page 1) The OP271 offers outstanding dc and ac matching between chan- nels. This is especially valuable for applications such as multiple gain blocks, high-speed instrumentation and amplifiers, buffers and active filters. The OP271 conforms to the industry standard, 8-pin dual op amp pinout. It is pin compatible with the TL072, TL082, LF412, and 1458/1558 dual op amps and can be used to significantly improve systems using these devices. For applications requiring lower voltage noise, see the OP270. For a quad version of the OP271, see the OP471. ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature Range Package Type /H9258jA 3 /H9258jC Unit 8-Pin Hermetic DIP (Z) 134 12 ∞C/W 8-Pin Plastic DIP (P) 96 37 ∞C/W 8-Pin SOIC (S) 92 27 ∞C/W NOTES 1Absolute maximum ratings apply to packaged parts, unless otherwise noted. 2The OP271’s inputs are protected by back-to-back diodes. Current limiting resistors are not used in order to achieve low-noise performance. If differential voltage exceeds ±1.0 V, the input current should be limited to ±25 mA. 3/H9258jA is specified for worst case mounting conditions, i.e., /H9258jA is specified for device in socket for CERDIP and P-DIP packages; /H9258jA is specified for device soldered to printed circuit board for SOIC package. ORDERING GUIDE Package TA = 25∞C Operating VOS Max CERDIP Temperature (mV) 8-Pin Plastic Range 200 *OP271AZ MIL 200 *OP271EZ XND 300 *OP271FZ XND

400 OP271GP XND

400 *OP271GS XND *Not for new design, obsolete April 2002.

REV. A –5– OP271Typical Performance Characteristics– FREQUENCY – Hz VOLTAGE NOISE DENSITY – nV/ Hz 1 1 10 1k100 100 TA = 25/H11543C VS = /H1155015V 1/f CORNER = 40Hz TPC 1. Voltage Noise Density vs. Frequency FREQUENCY – Hz CURRENT NOISE DENSITY – pA/ Hz 1.0 0.110 1k 100 10.0 10k TA = 25/H11543C VS = /H1155015V 1/f CORNER = 40Hz TPC 4. Current Noise Density vs. Frequency –75 TEMPERATURE – /H11543C INPUT BIAS CURRENT – nA VS = /H1155015V VCM = 0V –50 –25 0 25 5 07 5 1 0 0 1 2 5 TPC 7. Input Bias Current vs. Temperature SUPPLY VOLTAGE – Volts 0 /H115505 TA = 25/H11543C VOLTAGE NOISE DENSITY – nV/ Hz /H1155010 /H1155015 /H1155020 AT 10Hz AT 1kHz TPC 2. Voltage Noise Density vs. Supply Voltage TEMPERATURE – /H11543C INPUT OFFSET VOLTAGE – /H9262V 120 VS = /H1155015V 100 –20 1251007550250–25–50–75 TPC 5. Input Offset Voltage vs. Temperature –75 –50 –25 0 25 50 75 100 125 TEMPERATURE – /H11543C INPUT OFFSET CURRENT – nA TPC 8. Input Offset Current vs. Temperature FREQUENCY – Hz TOTAL HARMONIC DISTORTION – % 0.00110 100 10k 1k 0.01 0.1 TA = 25/H11543C VS = /H1155015V VO = 10Vp-p RL = 2k/H9024 AV = 100 AV = 10 AV = 1 TPC 3. Total Harmonic Distortion vs. Frequency 0 01 5 234 TIME – Minutes CHANGE IN OFFSET VOLTAGE – /H9262V TA = 25/H11543C VS = /H1155015V TPC 6. Warm-Up Offset Voltage Drift COMMON MODE VOLTAGE – Volts INPUT BIAS CURRENT – nA TA = 25/H11543C VS = /H1155015V 12.5 TPC 9. Input Bias Current vs. Common-Mode Voltage

REV. A OP271 –6– FREQUENCY – Hz CMR – dB 100k 1M10k1k10 100 100 110 120 130 TA = 25/H11543C VS = /H1155015V TPC 10. CMR vs. Frequency FREQUENCY – Hz PSR – dB 0 1 100M 140 120 100 10M1M100k10k1k10010 TA = 25/H11543C +PSR –PSR TPC 13. PSR vs. Frequency OPEN-LOOP GAIN – dB 10–10 TA = 25/H11543C VS = /H1155015V 8765432 PHASE SHIFT – DEG 100 120 140 160 180 FREQUENCY – MHz PHASE GAIN PHASE MARGIN = 62/H11543C TPC 16. Open-Loop Gain, Phase Shift vs. Frequency SUPPLY VOLTAGE – Volts TOTAL SUPPLY CURRENT – mA 3 0 /H115505 /H1155020/H1155010 /H1155015 TA = +125/H11543C TA = +25/H11543C TA = –55/H11543C TPC 11. Total Supply Current vs. Supply Voltage FREQUENCY – Hz OPEN-LOOP GAIN – dB 140 0 11 0 100M 120 100 10M1M100k10k1k100 TA = 25/H11543C VS = /H1155015V TPC 14. Open-Loop Gain vs. Frequency OPEN-LOOP GAIN – V/mV /H1155020 TA = 25/H11543C RL = 10k/H9024 500 SUPPLY VOLTAGE – Volts /H1155015/H1155010/H1155050 1000 1500 2000 TPC 17. Open-Loop Gain vs. Supply Voltage TEMPERATURE – /H11543C TOTAL SUPPLY CURRENT – mA 3 125 1007550250–25–50–75 VS = /H1155015V TPC 12. Total Supply Current vs. Temperature FREQUENCY – Hz CLOSED-LOOP GAIN – dB0 10M1M100k10k1k–20 TA = 25/H11543C VS = /H1155015V TPC 15. Closed-Loop Gain vs. Frequency VS = /H1155015V TEMPERATURE – /H11543C PHASE MARGIN – DEG 1251007550250–25–50–75 GAIN-BANDWIDTH PRODUCT – MHz 150 GBW /H11632m TPC 18. Gain-Bandwidth Product, Phase Margin vs. Temperature

REV. A –7– OP271 FREQUENCY – Hz PEAK-TO-PEAK AMPLITUDE – Volts 10M1M100k10k1k TA = 25/H11543C VS = /H1155015V THD = 1% RL = 10k/H9024 TPC 19. Maximum Output Swing vs. Frequency LOAD RESISTANCE – /H9024 MAXIMUM OUTPUT – Volts4 100 10k 1k TA = 25/H11543C VS = /H1155015V POSITIVE SWING NEGATIVE SWING TPC 20. Maximum Output Voltage vs. Load Resistance 120 100 FREQUENCY – Hz OUTPUT IMPEDANCE – /H9024 100 10k 1k TA = 25/H11543C VS = /H1155015V AV = 100 100k 1M 10M 140 160 180 AV = 1 TPC 21. Output Impedance vs. Frequency TEMPERATURE – /H11543C SLEW RATE – V//H9262S –75 VS = /H1155015V –SR +SR –50 –25 0 25 50 75 100 125 TPC 22. Slew Rate vs. Temperature FREQUENCY – Hz CHANNEL SEPARATION – dB 100k 1M10k1k10 100 100 160 170 180 190 TA = 25/H11543C VS = /H1155015V 110 120 130 140 150 10M TPC 23. Channel Separation vs. Frequency 5/H9262s5V TA = 25/H11543C VS = /H1155015V AV = +1 TPC 24. Large-Signal Transient Response 200ns50mV TA = 25/H11543C VS = /H1155015V AV = +1 TPC 25. Small Signal Transient Response

REV. A OP271 –8– OP271E ASSUME: A1 AND A2 ARE MATCHED. AO(s) = /H9275 s VO = (K1+1) VIN VIN VO OP271E R2 = R1 OP271 8.5V//H9262s PLACE SUPPLY DECOUPLING CAPACITORS AT OP271 VOUT CL 1000pF VIN 10/H9262F 0.1/H9262F 50/H9024 200pF 10/H9262F 0.1/H9262F OP271 Figure 2. Driving Large Capacitive Loads Figure 3. Pulsed Operation

APPLICATION INFORMATION

Capacitive Load Driving and Power Supply Considerations The OP217 is unity-gain stable and is capable of driving large capacitive loads without oscillating. Nonetheless, good supply bypassing is highly recommended. Proper supply bypassing reduces problems caused by supply line noise and improves the capacitive load driving capability of the OP271. In the standard feedback amplifier, the op amp’s output resistance combines with the load capacitance to form a low-pass filter that adds phase shift in the feedback network and reduces stability. A simple circuit to eliminate this effect is shown in Figure 2. The added components, C1 and R3, decouple the amplifier from the load capacitance and provide additional stability. The values of C1 and R3 shown in Figure 8 are for a load capacitance of up to 1000 pF when used with the OP271. Unity-Gain Buffer Applications When R f /H11349 100 /H9024 and the input is driven with a fast, large-signal pulse (>1 V), the output waveform will look as shown in Figure During the fast feedthrough-like portion of the output, the input protection diodes effectively short the output to the input, and a current, limited only by the output short-circuit protection, will be drawn by the signal generator. With R f /H11350 500 /H9024, the output is capable of handling the current requirements (I L /H11349 20 mA at

10 V); the amplifier will stay in its active mode and a smooth

transition will occur. When R f > 3 k/H9024, a pole created by Rf and the amplifier’s input capacitance (3 pF) creates additional phase shift and reduces phase margin. A small capacitor in parallel with R f helps eliminate this problem. Computer Simulations Many electronic design and analysis programs include models for op amps which calculate AC performance from the location of poles and zeros. As an aid to designers utilizing such a program, major poles and zeros of the OP271 are listed below. Their location will vary slightly between production lots. Typically, they will be within /H1155015% of the frequency listed. Use of this data will enable the designer to evaluate gross circuit performance quickly, but should not supplant rigorous characterization of a breadboard circuit. POLES ZEROS 15Hz 2.5 MHz

1.2 MHz 4 X 23 MHz

2 X 32 MHz -

8 X 40 MHz -

APPLICATIONS

The simple amplifier depicted in Figure 4, utilizes a monolithic dual operational amplifier and a few resistors to substantially reduce phase error compared to conventional amplifier designs. At a given gain, the frequency range for a specified phase accuracy is over a decade greater than for a standard single op amp amplifier. The low phase error amplifier performs second-order frequency compensation through the response of op amp A2 in the feedback loop of A1. Both op amps must be extremely well matched in frequency response. At low frequencies, the A1 feedback loop forces V 2/(K1 + 1)=VIN. The A2 feedback loop forces VO/VIN=K1 + 1. The DC gain is determined by the resistor divider around A2. Note that, like a conventional single op amp amplifier, the DC gain is set by resistor ratios only. Minimum gain for the low phase error amplifier is 10. Figure 4. Low Phase Error Amplifier

REV. A OP271 –10– 8-Lead Ceramic Dip-Glass Hermetic Seal [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) 1 4 0.310 (7.87) 0.220 (5.59)PIN 1 0.005 (0.13) MIN 0.055 (1.40) MAX 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) SEATING PLANE 0.200 (5.08) MAX 0.405 (10.29) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN OUTLINE DIMENSIONS 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) SEATING PLANE 0.015 (0.38) MIN 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) BSC 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) COMPLIANT TO JEDEC STANDARDS MO-095AA 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8) Dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) /H11547 45/H11543 8/H11543 0/H11543 1.75 (0.0688) 1.35 (0.0532) SEATING PLANE 0.25 (0.0098) 0.10 (0.0040) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) BSC 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130)COPLANARITY 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA

REV. A OP271 –11–

Revision History

10/02—Data Sheet changed from REV. 0 to REV. A.

–12– C00326-0-10/02(A) PRINTED IN U.S.A.