OP270 AD | Alldatasheet

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REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. a OP270 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. Dual Very Low Noise Precision Operational Amplifier

FEATURES

Very Low Noise 5 nV/ ÷÷÷÷÷Hz @ 1 kHz Max Excellent Input Offset Voltage 75 /H9262V Max Low Offset Voltage Drift 1 /H9262V//H11543C Max Very High Gain 1500 V/mV Min Outstanding CMR 106 dB Min Slew Rate 2.4 V/ /H9262s Typ Gain Bandwidth Product 5 MHz Typ Industry-Standard 8-Lead Dual Pinout SIMPLIFIED SCHEMATIC (One of Two Amplifiers Is Shown) –IN +IN BIAS OUT GENERAL DESCRIPTION The OP270 is a high performance, monolithic, dual operational amplifier with exceptionally low voltage noise, 5 nV/ ÷Hz max at 1 kHz. It offers comparable performance to ADI’s industry standard OP27. The OP270 features an input offset voltage below 75 mV and an offset drift under 1 mV/∞C, guaranteed over the full military tem- perature range. Open-loop gain of the OP270 is over 1,500,000 into a 10 kW load, ensuring excellent gain accuracy and linearity, even in high gain applications. Input bias current is under 20 nA, which reduces errors due to signal source resistance. The OP270’s CMR of over 106 dB and PSRR of less than 3.2 mV/V signifi- cantly reduce errors due to ground noise and power supply fluctuations. Power consumption of the dual OP270 is one-third less than two OP27s, a significant advantage for power conscious applications. The OP270 is unity-gain stable with a gain bandwidth product of 5 MHz and a slew rate of 2.4 V/ ms. The OP270 offers excellent amplifier matching, which is important for applications such as multiple gain blocks, low noise instru- mentation amplifiers, dual buffers, and low noise active filters. The OP270 conforms to the industry-standard 8-lead DIP pinout. It is pin compatible with the MC1458, SE5532/A, RM4558, and HA5102 dual op amps, and can be used to upgrade systems using those devices. For higher speed applications, the OP271, with a slew rate of 8V /ms, is recommended. For a quad op amp, see the OP470. CONNECTION DIAGRAMS 16-Lead SOIC (S-Suffix) NC = NO CONNECT –IN A 16 +IN A NC NC +IN B –IN B NC OUT A NC NC NC NC OUT B NC OP270 8-Lead PDIP (P-Suffix) 8-Lead CERDIP (Z-Suffix) OUT A 8 –IN A +IN A OUT B –IN B +IN B A B OP270

REV. C–2– (VS = /H1155015 V, TA =2 5/H11543C, unless otherwise noted.)OP270–SPECIFICATIONS OP270E OP270F OP270G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT Input Offset Voltage V OS 10 75 20 150 50 250 mV Input Offset Current l OS VCM =0 V 1 1 0 31 5 52 0 n A Input Bias Current I B VCM =0 V 5 20 10 40 15 60 nA Input Noise Voltage e n p-p 0.1 Hz to 10 Hz 80 200 80 200 80 nV p-p (Note 1) (Note 2) Input Noise f O = 10 Hz 1.1 1.1 1.1 pA/ ÷÷÷÷÷Hz Current Density i n fO = 100 Hz 0.7 0.7 0.7 pA/ ÷÷÷÷÷Hz fO = 1 kHz 0.6 0.6 0.6 pA/ ÷÷÷÷÷Hz Large-Signal V O = ± 10 V Voltage Gain A VO RL = 10 kW 1500 2300 1000 1700 750 1500 V/mV RL =2 kW 750 1200 500 900 350 700 V/mV Input Voltage Range IVR (Note3) ± 12 ± 12.5 ± 12 ± 12.5 ± 12 ± 12.5 V Output Voltage Swing V O RL ≥ 2k W± 12 ± 13.5 ± 12 ± 13.5 ± 12 ± 13.5 V Common-Mode Rejection CMR V CM = ± 11 V 106 125 100 120 90 110 dB Power Supply to ± 18 V Supply Current I SY No Load 4 6.5 4 6.5 4 6.5 mA (All Amplifiers) Gain Bandwidth GBP 5 5 5 MHz Product Channel Separation CS V O = ± 20 V p-p fO = 10 Hz 125 175 125 175 175 dB (Note 1) Input Capacitance C IN 33 3 p F Input Resistance R IN 0.4 0.4 0.4 M W Differential-Mode Input Resistance R INCM 20 20 20 G W Common-Mode Settling Time t S AV = +1, 10 V 5 5 5 ms Step to 0.01% NOTES 1. Guaranteed but not 100% tested. 2. Sample tested. 3. Guaranteed by CMR test. Specifications subject to change without notice.

REV. C –3– ELECTRICAL SPECIFICATIONS SPECIFICATIONS OP270 (Vs = /H1155015 V, –40∞C £ TA £ 85/H11543C, unless otherwise noted. ) OP270E OP270F OP270G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT Input Offset Voltage V OS 25 150 45 275 100 400 mV Average Input Offset Voltage Drift TCV OS 0.2 1 0.4 2 0.7 3 mV/∞C Input Offset Current I OS VCM =0 V 1.5 30 5 40 15 50 nA Input Bias Voltage I B VCM =0 V 6 60 15 70 19 80 nA Large-Signal V O = ± 10 V Voltage Gain A VO RL = 10 kW 1000 1800 600 1400 400 1250 V/mV RL =2 kW 500 900 300 700 225 670 V/mV Input Voltage Range * IVR ± 12 ± 12.5 ± 12 ± 12.5 ± 12 ± 12.5 V Output Voltage Swing V O RL ≥ 2k W± 12 ± 13.5 ± 12 ± 13.5 ± 12 ± 13.5 V Common-Mode Rejection CMR V CM = ± 11 V 100 120 94 115 90 100 dB Power Supply to ± 18 V (All Amplifiers) * Guaranteed by CMR test. Specifications subject to change without notice.

REV. C OP270 –4– ABSOLUTE MAXIMUM RATINGS 1 Storage Temperature Range Junction Temperature (T ORDERING GUIDE TA = +25°C VOS Max θJC θJA* Temperature Package Package Model ( /H9262V) ( °C/W) ( °C/W) Range Description Option OP270EZ 75 12 134 XIND 8- Lead CERDIP Q-8 (Z-Suffix) OP270FZ 150 12 134 XIND 8- Lead CERDIP Q-8 (Z-Suffix) OP270GP 250 37 96 XIND 8-Lead PDIP N-8 (P-Suffix) OP270GS 250 27 92 XIND 16-Lead SOIC RW-16 (S-Suffix) *θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device in socket for CERDIP and PDIP packages; θJA is specified for device soldered to printed circuit board for SOIC package. Operating Temperature Range NOTES

1 Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 The OP270’s inputs are protected by back-to-back diodes. Current limiting resistors are not used, in order to achieve low noise performance. If d ifferential voltage exceeds +10 V, the input current should be limited to ±25 mA. For military processed devices, please refer to the Standard Microcircuit Drawing (SMD) available at SMD Part Number ADI Equivalent 5962-8872101PA OP270AZMDA WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP270 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. C –5– OP270 FREQUENCY (Hz) VOLTAG E NOISE (nV/ Hz) 1 10 100 1k 1/f CORNER = 5Hz TA = 25/H11543C VS = /H1155015V TPC 1. Voltage Noise Density vs. Frequency FREQUENCY (Hz) CURRENT NOISE (pA/ Hz) 10 100 10k 0.1 1.0 TA = 25/H11543C VS = /H1155015V 1/f CORNER = 200Hz TPC 4. Current Noise Density vs. Frequency TEMPERA TURE (/H11543C) INPUT BIAS CURRENT (nA) –75 –50 0 50 100 125 VS = /H1155015V VCM = 0V –25 25 75 TPC 7. Input Bias Current vs. Temperature SUPPL Y VOL T AGE (V) VOLTAG E NOISE (nV/ Hz) 0 /H115505 /H1155015 /H1155020 /H1155010 TA = 25/H11543C AT 10Hz AT 1kHz TPC 2. Voltage Noise Density vs. Supply Voltage TEMPERA TURE (/H11543C) VOLTAG E NOISE (nV/ Hz) –75 –30 –10 –50 –25 0 25 50 75 100 125 –20 VS = /H1155015V TPC 5. Input Offset Voltage vs. Temperature TEMPERA TURE (/H11543C) INPUT OFFSET CURRENT (nA) –75 –50 0 50 100 125 VS = /H1155015V VCM = 0V –25 25 75 TPC 8. Input Offset Current vs. Temperature TA = 25/H11543C VS = /H1155015V NOISE VOL T AGE (100nV/DIV) 0.1Hz TO 10Hz NOISE TIME (1sec/DIV) TPC 3. 0.1 Hz to 10 Hz Input Voltage Noise TIME (Minutes) CHANGE IN OFFSET VOL T AGE (/H9262A) 12345 TA = 25/H11543C VS = /H1155015V TPC 6. Warm-Up Offset Voltage Drift COMMON-MODE VOL T AGE (V) INPUT BIAS CURRENT (nA) –12.5 TA = 25/H11543C VS = /H1155015V –10.0 –7.5 –5.0 –2.5 0.0 2.5 5.0 7.5 10.0 12.5 TPC 9. Input Bias Current vs. Common-Mode Voltage Typical Performance Characteristics–

REV. C OP270 –6– FREQUENCY (Hz) CMR (dB) 130 110 TA = 25/H11543C VS = /H1155015V 11 0 100 1k 10k 100k 1M 120 100 TPC 10. CMR vs. Frequency FREQUENCY (Hz) PSR (dB) 140 0 1 100 10k 1M 100M TA = 25/H11543C 10 1k 100k 10M 100 120 –PSR +PSR TPC 13. PSR vs. Frequency FREQUENCY (Hz) GAIN (dB) –10 1 TA = 25/H11543C VS = /H1155015V PHASE GAIN PHASE MARGIN = 62/H11543 180 160 120 140 100 PHASE SHIFT (Degrees) 23 4 5 6 7 8 9 1 0 TPC 16. Open-Loop Gain Phase Shift vs. Frequency SUPPL Y VOL T AGE (V) TOTAL SUPPL Y CURRENT (mA) 0 /H115505 /H1155010 /H1155015 /H1155020 +125/H11543C +25/H11543C –55/H11543C TPC 11. Total Supply Current vs. Supply Voltage FREQUENCY (Hz) VOLTAGE GAIN (dB) 140 0 1 100 10k 1M 100M TA = 25/H11543C VS = /H1155015V 10 1k 100k 10M 100 120 TPC 14. Open-Loop Gain vs. Frequency SUPPL Y VOL T AGE (V) OPEN-LOOP GAIN (V/mV) 5000 1000 2000 3000 4000 /H115505 /H1155010 /H1155015 /H1155020 /H1155025 TPC 17. Open-Loop Gain vs. Supply Voltage TEMPERA TURE (/H11543C) TOTAL SUPPL Y CURRENT (mA) –75 –25 25 75 125 VS = /H1155015V –50 0 50 100 TPC 12. Total Supply Current vs. Temperature FREQUENCY (Hz) CLOSED-LOOP GAIN (dB) –201k 10k TA = 25/H11543C VS = /H1155015V 100k 10M TPC 15. Closed-Loop Gain vs. Frequency TEMPERA TURE (/H11543C) PHASE MARGIN (Degrees) 40–75 –50 –25 0 25 50 75 100 125 150 GAIN BANDWIDTH PRODUCT (MHz) /H9021 GBP TPC 18. Gain-Bandwidth Phase Margin vs. Temperature

REV. C –7– OP270 FREQUENCY (Hz) PEAK-TO-PEAK AMPLITUDE (V) 01k 10k 100k 1M 10M TA = 25/H11543C VS = /H1155015V THD = 1% TPC 19. Maximum Output Swing vs. Frequency FREQUENCY (Hz) OUTPUT IMPEDANCE (/H9024) 01k 100k 10M 100 10k 1M TA = +25/H11543C VS = /H1155015V AV = 100 AV = 10 AV = 1 TPC 22. Output Impedance vs. Frequency FREQUENCY (Hz) DISTORTION (%) 0.00110 10k 0.1 TA = 25/H11543C VS = /H1155015V VO = 20V p-p RL =2k/H9024 100 0.01 AV = 10 AV = 1 TPC 25. Total Harmonic Distor- tion vs. Frequency LOAD RESIST ANCE (/H9024) MAXIMUM OUTPUT ( V) 51k 10k 100k TA = 25/H11543C VS = /H1155015V NEGA TIVE SWING POSITIVE SWING TPC 20. Maximum Output Voltage vs. Load Resistance TEMPERA TURE (/H11543C) SLEW RA TE (V//H9262s) 2.2–75 25 125 2.5 2.8 –25 75 VS = /H1155015V –SR +SR 0 100–50 50 2.3 2.4 2.6 2.7 TPC 23. Slew Rate vs. Temperature TA = 25/H11543C VS = /H1155015V AV = +1 RL = 2k/H9024 5V 20/H9262s TPC 26. Large Signal Transcient Response CAP ACITIVE LOAD (pF) OVERSHOOT (%) 00 400 1000 TA = 25/H11543C VS = /H1155015V VIN = 100mV AV = +1 200 600 800 TPC 21. Small-Signal Overshoot vs. Capacitive Load FREQUENCY (Hz) CHANNEL SEP ARA TION (dB) 7011 k 1 M 130 190 10k TA = 25/H11543C VS = /H1155015V VO = 20V p-p TO 10kHz 100 100k10 110 150 170 120 180 100 140 160 TPC 24. Channel Separation vs. Frequency TA = 25/H11543C VS = /H1155015V AV = +1 RL = 2k/H9024 50mV 200nS TPC 27. Small-Signal Transient Response

7 OUT

1 OUT

Figure 15. Digital Panning Control Figure 16. Digital Panning Control Output Figure 17. Dual Programmable Gain Amplifier

REV. C OP270 –14– 8-Lead Ceramic Dual In-Line Package [CERDIP] Z-Suffix (Q-8) Dimensions shown in inches and (millimeters) 1 4 0.310 (7.87) 0.220 (5.59)PIN 1 0.005 (0.13) MIN 0.055 (1.40) MAX 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) SEATING PLANE 0.200 (5.08) MAX 0.405 (10.29) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] P-Suffix (N-8) Dimensions shown in inches and (millimeters) SEATING PLANE 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) BSC 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AA 0.015 (0.38) MIN 16-Lead Standard Small Outline Package [SOIC] Wide Body S-Suffix (RW-16) Dimensions shown in millimeters and (inches) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AA SEATING PLANE 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) BSC 16 9 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 10.50 (0.4134) 10.10 (0.3976) 0.32 (0.0126) 0.23 (0.0091) 8/H11543 0/H11543 0.75 (0.0295) 0.25 (0.0098) /H11547 45/H11543 1.27 (0.0500) 0.40 (0.0157) COPLANARITY 0.10

REV. C OP270 –15–

Revision History

4/03—Data Sheet changed from REV. B to REV. C. 11/02—Data Sheet changed from REV. A to REV. B. 9/02—Data Sheet changed from REV. 0 to REV. A.

–16– C00325–0–4/03(C)