OP270 (Rev. F)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 20
Technical content
Rev. F | Page 2 of 20 TABLE OF CONTENTS Capacitive Load Driving and Power Supply Considerations .... 15
REVISION HISTORY
10/15—Rev. E to Rev. F Changes to Supply Voltage Parameter and Differential Input 2/10—Rev. D to Rev. E 2/09—Rev. C to Rev. D 4/03—Rev. B to Rev. C 11/02—Rev. A to Rev. B 9/02—Rev. 0 to Rev. A 2/01—Revision 0: Initial Version
Rev. F | Page 3 of 20 SPECIFICATIONS VS = ±15 V , TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions OP270E OP270F OP270G Unit Min Typ Max Min Typ Max Min Typ Max Input Offset Voltage V OS 10 75 20 150 50 250 μV Input Offset Current I OS V CM = 0 V 1 10 3 15 5 20 nA Input Bias Current I B V CM = 0 V 5 20 10 40 15 60 nA Input Noise Voltage1 e n p-p 0.1 Hz to 10 Hz 80 200 80 200 80 nV p-p Input Noise Current Density i n f O = 10 Hz 1.1 1.1 1.1 pA/√Hz i n f O = 100 Hz 0.7 0.7 0.7 pA/√Hz i n f O = 1 kHz 0.6 0.6 0.6 pA/√Hz Large-Signal Voltage Gain A VO VO = ±10 V, RL = 10 kΩ 1500 2300 1000 1700 750 1500 V/mV VO = ±10 V, RL = 2 kΩ 750 1200 500 900 350 700 V/mV Input Voltage Range3 IVR ±12 ±12.5 ±12 ±12.5 ±12 ±12.5 V Output Voltage Swing V O R L ≥ 2 kΩ ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 V Common-Mode Rejection CMR V CM = ±11 V 106 125 100 120 90 110 dB Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V Supply Current (All Amplifiers) ISY No load 4 6.5 4 6.5 4 6.5 mA Gain Bandwidth Product GBP 5 5 5 MHz Channel Separation1 CS VO = ±20 V p-p, fO = 10 Hz 125 175 125 175 175 dB Input Capacitance C IN 3 3 3 pF Input Resistance Differential Mode R IN 0.4 0.4 0.4 MΩ Common Mode R INCM 20 20 20 GΩ Settling Time tS AV = +1, 10 V, step to 0.01% 5 5 5 μs 1 Guaranteed but not 100% tested. 2 Sample tested. 3 Guaranteed by CMR test.
Rev. F | Page 4 of 20 ELECTRICAL SPECIFICATIONS VS = ±15 V , −40°C ≤ TA ≤ 85°C, unless otherwise noted. Table 2. Parameter Symbol Test Conditions OP270E OP270F OP270G Unit Min Typ Max Min Typ Max Min Typ Max Input Offset Voltage V OS 25 150 45 275 100 400 μV Average Input Offset Voltage Drift TCVOS 0.2 1 0.4 2 0.7 3 μV/°C Input Offset Current I OS V CM = 0 V 1.5 30 5 40 15 50 nA Input Bias Voltage I B V CM = 0 V 6 60 15 70 19 80 nA Large-Signal Voltage Gain A VO VO = ±10 V, RL = 10 kΩ 1000 1800 600 1400 400 1250 V/mV A VO VO = ±10 V, RL = 2 kΩ 500 900 300 700 225 670 V/mV Input Voltage Range1 IVR ±12 ±12.5 ±12 ±12.5 ±12 ±12.5 V Output Voltage Swing V O R L ≥ 2 kΩ ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 V Common-Mode Rejection CMR V CM = ±11 V 100 120 94 115 90 100 dB Power Supply Rejection Ratio Supply Current (All Amplifiers) 1 Guaranteed by CMR test.
Rev. F | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage ±18 V Differential Input Voltage1 ±1.0 V Differential Input Current1 ±25 mA Input Voltage Supply voltage Output Short-Circuit Duration Continuous Storage Temperature Range −65°C to +150°C Lead Temperature Range (Soldering, 60 sec) 300°C Junction Temperature (TJ) −65°C to +150°C Operating Temperature Range −40°C to +85°C 1 The OP270 inputs are protected by back-to-back diodes. To achieve low noise performance, current-limiting resistors are not used. If the differential voltage exceeds +10 V, the input current should be limited to ±25 mA. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
For reference, typical source resistances of some signal sources are listed in Table 4. Table 4. Typical Source Resistances Strain Gage <500 Ω Typically used in low frequency applications. direct coupling is used. OP270 IB can be disregarded. applications. OP270 does not introduce any self-magnetization problems. Figure 35. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
half of the OP270, which also holds AGND at virtual ground. eliminated by using feedback resistors internal to the DAC8221. input signal and a digital ramp applied to the DAC data input.
20 MΩ resistor placed in parallel with the DAC feedback loop
Figure 44. Digital Panning Control Figure 45. Digital Panning Control Output
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 50. 16-Lead Standard Small Outline Package [SOIC_W] 1 The OP270GPZ, OP270GSZ, and OP270GSZ-REEL are RoHS compliant parts. printed circuit board for SOIC package. registered trademarks are the prop erty of their respective owners.