OP250

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(SO-8) OP250 OUT A –IN A +IN A OUT B –IN B +IN B V+1 (Not to Scale) 8-Lead TSSOP (RU-8) –IN A +IN A OUT B –IN B +IN B V+1 4 5 8OUT A OP250 14-Lead Narrow Body SO (N-14) OUT A –IN A +IN A –IN D +IN D OUT D1 +IN B –IN B OUT B –IN C OUT C +IN C5 OP450 (Not to Scale) 14-Lead TSSOP (RU-14) AD8532 OUT A –IN A +IN A –IN D +IN D OUT D1 14 +IN B –IN B OUT B –IN C OUT C +IN C OP450 1 14 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a CMOS Single-Supply Rail-to-Rail Input/Output Operational Amplifiers OP250/OP450 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997

FEATURES

Single-Supply Operation: 2.7 V to 6 V High Output Current: 6100 mA Low Supply Current: 800 mA/Amp Wide Bandwidth: 1 MHz Slew Rate: 2.2 V/ ms No Phase Reversal Low Input Currents Unity Gain Stable

APPLICATIONS

Battery Powered Instrumentation Medical Remote Sensors ASIC Input or Output Amplifier Automotive GENERAL DESCRIPTION The OP250 and OP450 are dual and quad CMOS single-supply, amplifiers featuring rail-to-rail inputs and outputs. Both are guar- anteed to operate from a +2.7 V to +5 V single supply. These amplifiers have very low input bias currents. Outputs are capable of driving 100 mA loads and are stable with capacitive loads. Supply current is less than 1 mA per amplifier. Applications for these amplifiers include portable medical equipment, safety and security, and interface to transducers with high output impedance. The ability to swing rail-to-rail at both the input and output en- ables designers to build multistage filters in single-supply sys- tems and maintain high signal-to-noise ratios. The OP250 and OP450 are specified over the extended indus- trial (–40°C to +125°C) temperature range. The OP250, dual, is available in 8-lead TSSOP and SO surface mount packages. The OP450, quad, is available in 14-lead thin shrink small out- line (TSSOP) and narrow 14-lead SO packages.

REV. 0–2– OP250/OP450–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V OS 8m V –40°C < TA < +125°C2 0 m V Input Bias Current I B 24 0 p A –40°C < TA < +85°C6 0 p A –40°C < TA < +125°C 500 pA Input Offset Current I OS 0.5 25 pA –40°C < TA < +125°C6 0 p A Input Voltage Range 03 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 3 V 40 55 dB –40°C < TA < +125°C3 5 d B Large Signal Voltage Gain A VO RL = 2 kΩ , VO = 0.3 V to 2.7 V 800 V/mV Offset Voltage Drift ΔVOS/ΔT1 0 µV/°C Bias Current Drift ΔIB/ΔT 1.8 pA/ °C Offset Current Drift ΔIOS/ΔT 0.07 pA/ °C OUTPUT CHARACTERISTICS Output Voltage High V OH IL = 100 µA 2.99 V IL = 10 mA 2.85 2.94 V –40°C to +125°C 2.8 V Output Voltage Low V OL IL = 100 µA1 m V IL = 10 mA 55 100 mV –40°C to +125°C 125 mV Output Current I OUT 100 mA Open Loop Impedance Z OUT f = 1 MHz, AV = 1 180 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V S = 2.7 V to 6 V 60 80 dB –40°C < TA < +125°C5 5 d B Supply Current/Amplifier I SY VO = 0 V 700 1,000 µA –40°C < TA < +125°C 1,250 µA DYNAMIC PERFORMANCE Slew Rate SR R L = 10 kΩ 1.9 V/ µs Settling Time t S To 0.01% 4 µs Gain Bandwidth Product GBP 0.95 MHz Phase Margin Øo 46 Degrees Channel Separation CS f = 1 kHz, R L = 10 kΩ 100 dB NOISE PERFORMANCE Voltage Noise e n p–p 0.1 Hz to 10 Hz 10 µV p–p Voltage Noise Density e n f = 1 kHz 45 nV/ √Hz f = 10 kHz 30 nV/ √Hz Current Noise Density i n f = 1 kHz 0.05 pA/ √Hz Specifications subject to change without notice. (VS = 13.0 V, TA = 1258C, VCM = 1.5 V unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V OS 2 7.5 mV –40°C < TA < +125°C2 0 m V Input Bias Current I B 24 0 p A –40°C < TA < +85°C6 0 p A –40°C < TA < +125°C 500 pA Input Offset Current I OS 0.5 25 pA –40°C < TA < +125°C6 0 p A Input Voltage Range 05 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 5 V 45 60 dB –40°C < TA < +125°C4 0 d B Large Signal Voltage Gain A VO RL = 2 kΩ , Vo = 0.3 V to 4.7 V 1,000 V/mV Offset Voltage Drift ΔVOS/ΔT –40 °C < TA < +125°C1 0 µV/°C Bias Current Drift ΔIB/ΔT 1.8 pA/ °C Offset Current Drift ΔIOS/ΔT 0.07 pA/ °C OUTPUT CHARACTERISTICS Output Voltage High V OH IL = 100 µA 4.99 V IL = 10 mA 4.9 4.94 V –40°C to +125°Cm V Output Voltage Low V OL IL = 100 µA1 V IL = 10 mA 40 100 mV –40°C to +125°C 125 mV Output Current I OUT ± 100 mA Open Loop Impedance Z OUT f =1 MHz, AV = 1 200 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V S = 2.7 V to 6 V 60 80 dB –40°C < TA < +125°C5 5 d B Supply Current/Amplifier I SY VO = 0 V 800 1,250 µA –40°C < TA < +125°C 750 1,750 µA DYNAMIC PERFORMANCE Slew Rate SR R L = 10 kΩ 2.2 V/ µs Full-Power Bandwidth BW P 1% Distortion 100 kHz Settling Time t S To 0.01% 3 µs Gain Bandwidth Product GBP 1 MHz Phase Margin Øo 48 Degrees Channel Separation CS f = 1 kHz, R L = 10 kΩ 100 dB NOISE PERFORMANCE Voltage Noise e n p–p 0.1 Hz to 10 Hz 10 µV p–p Voltage Noise Density e n f = 1 kHz 45 nV/ √Hz f = 10 kHz 30 nV/ √Hz Current Noise Density i n f = 1 kHz 0.05 pA/ √Hz Specifications subject to change without notice. REV. 0 –3– OP250/OP450 (VS = 15.0 V, TA = 1258C, VCM =2.5 V unless otherwise noted)

REV. 0–4– Package Type uJA* uJC Units 8-Lead SOIC (S) 158 43 °C/W 8-Lead TSSOP (RU) 240 43 °C/W 14-Lead SOIC (N) 120 36 °C/W 14-Lead TSSOP (RU) 180 35 °C/W *θJA is specified for the worst case conditions, i.e., θJA specified for device soldered in circuit board for surface mount packages. ABSOLUTE MAXIMUM RATINGS 1, 2 Output Short-Circuit Storage Temperature Range Operating Temperature Range Junction Temperature Range NOTES 1Absolute maximum ratings apply at +25 °C, unless otherwise noted. 2Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP250/OP450 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Temperature Package Package Model Range Description Options OP250GS –40 °C to +125°C 8-Lead SOIC SO-8 OP250GRU –40 °C to +125°C 8-Lead TSSOP RU-8 OP450GS –40 °C to +125°C 14-Lead SOIC N-14 OP450GRU –40 °C to +125°C 14-Lead TSSOP RU-14 WARNING! ESD SENSITIVE DEVICE

REV. 0–14– * OP250 SPICE Macro-Model Typical Values * 10/97, Ver. 1 * TAM / ADSC * Node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply .SUBCKT OP2501 2 99 50 45 * INPUT STAGE M1 4 3 6 6 MNIN L=2u W=66u M2 5 2 6 6 MNIN L=2u W=66u M3 7 3 9 9 MPIN L=2u W=66u M4 8 2 9 9 MPIN L=2u W=66u RD1 99 4 5E3 RD2 99 5 5E3 RD3 7 50 5E3 RD4 8 50 5E3 VCM1 10 50 -.3 VCM2 99 11 -.3 D1 10 6 DX D2 9 11 DX +1 1 1 IOS 1 2 .25E-12 IBIAS1 6 50 700E-6 IBIAS2 99 9 700E-6 * CMRR=60 dB, ZERO AT 20kHz ECM1 60 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 60 61 159.2E3 RCM2 61 98 159 CCM1 60 61 50E-12 * PSRR=90dB, ZERO AT 200Hz RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 50 * INTERNAL VOLTAGE REFERENCE RSY1 99 91 100E3 RSY2 50 90 100E3 VSN1 91 90 DC 0 EREF 98 0 (90,0) 1 GSY 99 50 POLY(1) (99,50) -1.81E-3 1.5E-5 * VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz) VN1 80 0 0 RN1 80 0 16.45E-3 HN 81 0 VN1 30 RN2 81 0 1 * POLE AT 1.25MHz G2 98 20 POLY(2) (4,5) (7,8) 0 5E-5 5E-5 R2 20 98 10E3 C2 20 98 12.7E-12 * GAIN STAGE G1 98 30 (20,98) 3.5E-4 R1 30 98 6.25E6 CF 30 45 135E-12 D4 31 99 DX D5 50 32 DX V1 31 30 0.7 V2 30 32 0.7 * OUTPUT STAGE M5 45 41 99 99 MPOUT L=2u W=6660u M6 45 42 50 50 MNOUT L=2u W=6660u EO1 99 41 POLY(1) (98,30) .9232 1 EO2 42 50 POLY(1) (30,98) .8914 1 * MODELS .MODEL MNIN NMOS(LEVEL=2,VTO=0.75, +KP=20E-6,CGSO=0,KF=2.5E-31,AF=1) .MODEL MPIN PMOS(LEVEL=2,VTO=-0.75, +KP=20E-6,CGSO=0,KF=2.5E-31,AF=1) .MODEL MNOUT NMOS(LEVEL=2,VTO=0.75, +KP=30E-6,LAMBDA=0.04,CGSO=0) .MODEL MPOUT PMOS(LEVEL=2,VTO=-0.75, +KP=20E-6,LAMBDA=0.04,CGSO=0) .MODEL DX D(IS=1E-16) .ENDS OP250

REV. 0 –15– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 14-Lead Plastic DIP (N-14) 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) PIN 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93)SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 8-Lead TSSOP (RU-8) 8 5 0.122 (3.10) 0.114 (2.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 0.0256 (0.65) BSC SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 14-Lead TSSOP (RU-14) 14 8 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50)

C3236–8–10/97PRINTED IN U.S.A. –16–