OP249GSZ

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Rev. H | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

11/13—Rev. G to Rev. H 4/10—Rev. F to Rev. G Changes to Features Section and General Description Section . 1 Deleted Long Term Offset Voltage Parameter and Changes to Offset Voltage Parameter, Offset Voltage Changes to Offset Voltage Parameter and Offset Voltage 5/07—Rev. E to Rev. F 9/01—Rev. D to Rev. E Edits to Absolute Maximum Ratings, Package Type, and

Rev. H | Page 3 of 20 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VS = ±15 V , TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Conditions OP249A OP249F Unit Min Typ Max Min Typ Max Offset Voltage VOS VCM = 0 V 0.2 0.75 0.2 0.9 mV Offset Stability 1.5 1.5 µV/month Input Bias Current IB VCM = 0 V, TA = 25°C 30 75 30 75 pA Input Offset Current IOS VCM = 0 V, TA = 25°C 6 25 6 25 pA Input Voltage Range1 IVR 12.5 12.5 V ±11 ±11 V −12.5 –12.5 V Common-Mode Rejection CMR VCM = ±11 V 80 90 80 90 dB Power-Supply Rejection Ratio PSRR VS = ± 4.5 V to ±18 V 12 31.6 12 50 µV/V Large Signal Voltage Gain AVO VO = ±10 V, RL = 2 kΩ 1000 1400 500 1200 V/mV Output Voltage Swing VO RL = 2 kΩ 12.5 12.5 V ±12.0 ±12.0 V −12.5 –12.5 V Short-Circuit Current Limit ISC Output shorted to ground 36 36 mA ±20 ±50 ±20 ±50 mA −33 –33 mA Supply Current ISY No load, VO = 0 V 5.6 7.0 5.6 7.0 mA Slew Rate SR RL = 2 kΩ, CL = 50 pF 18 22 18 22 V/µs Gain Bandwidth Product2 GBW 3.5 4.7 3.5 4.7 MHz Phase Margin ΘM 0 dB gain 55 55 Degrees Differential Input Impedance ZIN 1012||6 1012||6 Ω||pF Open-Loop Output Resistance RO 35 35 Ω Voltage Noise en p-p 0.1 Hz to 10 Hz 2 2 µV p-p Voltage Noise Density en fO = 10 Hz 75 75 nV/√Hz fO = 100 Hz 26 26 nV/√Hz fO = 1 kHz 17 17 nV/√Hz fO = 10 kHz 16 16 nV/√Hz Current Noise Density in fO = 1 kHz 0.003 0.003 pA/√Hz Voltage Supply Range VS ±4.5 ±15 ±18 ±4.5 ±15 ±18 V 1 Guaranteed by CMR test. 2 Guaranteed by design. 3 Settling time is sample tested.

Rev. H | Page 4 of 20 VS = ±15 V , TA = 25°C, unless otherwise noted. Table 2. Parameter Symbol Conditions OP249G Unit Min Typ Max Offset Voltage VOS VCM = 0 V 0.4 2.0 mV Input Bias Current IB VCM = 0 V, TA = 25°C 40 75 pA Input Offset Current IOS VCM = 0 V TA = 25°C 10 25 pA Input Voltage Range1 IVR 12.5 V ±11 V −12.0 V Common-Mode Rejection CMR VCM = ±11 V 76 90 dB Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 12 50 µV/V Large Signal Voltage Gain AVO VO = ±10 V; RL = 2 kΩ 500 1100 V/mV Output Voltage Swing VO RL = 2 kΩ 12.5 V ±12.0 V −12.5 V Short-Circuit Current Limit ISC Output shorted to ground 36 mA ±20 ±50 mA −33 mA Supply Current ISY No load; VO = 0 V 5.6 7.0 mA Slew Rate SR RL = 2 kΩ, CL = 50 pF 18 22 V/µs Gain Bandwidth Product2 GBW 4.7 MHz Settling Time tS 10 V step 0.01% 0.9 1.2 µs Phase Margin ΘM 0 dB gain 55 Degree Differential Input Impedance ZIN 1012||6 Ω||pF Open-Loop Output Resistance RO 35 Ω Voltage Noise en p-p 0.1 Hz to 10 Hz 2 μV p-p Voltage Noise Density en fO = 10 Hz 75 nV/√Hz fO = 100 Hz 26 nV/√Hz fO = 1 kHz 17 nV/√Hz fO = 10 kHz 16 nV/√Hz Current Noise Density in fO = 1 kHz 0.003 pA/√Hz Voltage Supply Range VS ±4.5 ±15 ±18 V 1 Guaranteed by CMR test. 2 Guaranteed by design.

Rev. H | Page 5 of 20 VS = ±15 V , −55°C ≤ TA ≤ +125°C for A grade, unless otherwise noted. Table 3. Parameter Symbol Conditions OP249A Unit Min Typ Max Offset Voltage VOS V CM = 0 V 0.12 1.0 mV Offset Voltage Temperature Coefficient TCV OS V CM = 0 V 1 10 μV/°C Input Bias Current1 I B 4 20 nA Input Offset Current1 I OS 0.04 4 nA Input Voltage Range2 IVR 12.5 V ±11 V −12.5 V Common-Mode Rejection CMR V CM = ±11 V 76 110 dB Power Supply Rejection Ratio PSRR V S = ±4.5 V to ±18 V 5 50 μV/V Large Signal Voltage Gain AVO R L = 2 kΩ; VO = ±10 V 500 1400 V/mV Output Voltage Swing VO R L = 2 kΩ 12.5 V ±12 V −12.5 V Supply Current ISY No load, V O = 0 V 5.6 7.0 mA 1 TA = 125°C. 2 Guaranteed by CMR test. VS = ±15 V , −40°C ≤ TA ≤ +85°C, unless otherwise noted. Table 4. Parameter Symbol Conditions OP249F OP249G Unit Min Typ Max Min Typ Max Offset Voltage VOS V CM = 0 V 0.5 1.1 1.0 3.6 mV Offset Voltage Temperature Coefficient TCV OS V CM = 0 V 2.2 12 6 25 μV/°C Input Bias Current1 I B 0.3 4.0 0.5 4.5 nA Input Offset Current1 I OS 0.02 1.2 0.04 1.5 nA Input Voltage Range2 IVR 12.5 12.5 V ±11 ±11 V −12.5 −12.5 V Common-Mode Rejection CMR V CM = ±11 V 80 90 76 95 dB Power Supply Rejection Ratio PSRR V S = ±4.5 V to ±18 V 7 100 10 100 μV/V Large Signal Voltage Gain AVO R L = 2 kΩ; VO = ±10 V 250 1200 250 1200 V/mV Output Voltage Swing VO R L = 2 kΩ 12.5 12.5 V ±12 ±12.0 V −12.5 −12.5 V Supply Current ISY No load, V O = 0 V 5.6 7.0 5.6 7.0 mA 1 TA = 85°C. 2 Guaranteed by CMR test.

1 Absolute maximum ratings apply to packaged parts, unless otherwise noted.

2 For supply voltages less than ±18 V, the absolute maximum input voltage is

equal to the supply voltage. Table 6. Thermal Resistance soldered to printed circuit board for SOIC package.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP]

Rev. H | Page 19 of 20 NOTES

Rev. H | Page 20 of 20 NOTES ©1989–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00296-0-11/13(H)