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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a OP215 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Dual Precision JFET-Input Operational Amplifier
FEATURES
High Slew Rate: 10 V/ /H9262s Min Fast Settling Time: 0.9 /H9262s to 0.1% Type Low Input Offset Voltage Drift: 10 /H9262V//H11543C Max Wide Bandwidth: 3.5 MHz Min Temperature-Compensated Input Bias Currents Guaranteed Input Bias Current: 18 nA Max (125 /H11543C) Bias Current Specified Warmed Up over Temperature Low Input Noise Current: 0.01 pA/ ÷Hz Type High Common-Mode Rejection Ratio 86 dB Min Pin Compatible with Standard Dual Pinouts Models with MIL-STD-883 Class B Processing Available GENERAL DESCRIPTION The OP215 offers the proven JFET-input performance advantages of high speed and low input bias current with the tracking and convenience advantages of a dual op amp configuration. Low input offset voltages, low input currents, and low drift are featured in these high-speed amplifiers. On-chip zener-zap trimming is used to achieve low V OS, while a bias-current compensation scheme gives a low input bias current NOMINV INPUT+ 7.4 pF Q12 INV INPUT J11 NULL J8 J7 NULL Q11 3.6 k/H9024 Q16 Q13 Q15 3.6k/H9024 Q14 Q4 Q2 R2 C2 7.4pF Q10 Q19 Q17 Q18 Q21 Q20 J10 Q23 R13 Q24 Q22 OUTPUT R10 Q25 R11 R12 NOTE R7, R8 ARE ELECTRONICALLY ADJUSTED ON-CHIP FOR MINIMUM OFFSET VOLTAGE Figure 1. Simplified Schematic (1/2 OP215) which greatly extends the application usefulness of this device. OP249 and AD712 data sheets.
REV. A–2– OP215–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Type Max Min Type Max Unit Input Offset Voltage V OS RS = 50 W 0.2 1.0 2.0 4.0 mV ‘G’ Grade 2.5 6.0 mV Input Offset Current1 IOS Tj = 25∞C3 5 0 3 100 pA Device Operating 5 100 5 200 pA Input Bias Current1 IB Tj = 25∞C ± 15 ± 100 ± 15 ± 300 pA Device Operating ± 18 ± 300 ± 18 ± 600 pA Input Resistance R IN 101,2 101,2 W Large-Signal Voltage A VO RL /H11350 2 kW, 150 500 50 200 V/mV Gain V O = ± 10 V Output Voltage Swing V O RL = 10 kW± 12 ± 13 ± 12 ± 13 V RL = 2 kW± 11 ± 12.7 ± 11 ± 12.7 V Supply Current I SY 6.0 8.5 7.0 10.0 mA ‘G’ Grade 7.0 12.0 mA Slew Rate SR A VCL = 1 10 18 5 15 V/ /H9262s Gain Bandwidth GBW 3.5 5.7 3.0 5.4 MHz Product3 Closed-Loop Bandwidth CLBW A VCL = 1 13 12 MHz Setting Time t S To 0.01% 2.3 2.4 /H9262s To 0.05%2 1.1 1.2 /H9262s To 0.10% 0.9 1.0 /H9262s Input Voltage Range IVR 10.2 14.8 10.1 14.8 V Common-Mode CMRR V CM = ± IVR 82 100 80 96 dB Rejection Ratio E, G Grades Power Supply Rejection PSRR V S = ± 10 V to ± 16 V 10 51 /H9262V/V Ratio V S = ± 10 V to ± 15 V 16 100 /H9262V/V Input Noise Voltage /H9258nf O = 100 Hz 20 20 nV/ ÷Hz Density f O = 1,000 Hz 15 15 nV/ ÷Hz Input Noise Current I n fO = 100 Hz 0.01 0.01 pA/ ÷Hz Density f O = 1,000 Hz 0.01 0.01 pA/ ÷Hz Input Capacitance C IN 33 p F NOTES 1Input bias current is specified for two different conditions. The T j = 25∞C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed up condition at 25 ∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standar d JFET input op amps. I S and IOS are measured at V CM = 0. 2Setting time is defined here for a unity gain inverter connection using 2 k W resistors. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See setting time test circuit. 3Sample tested. Specifications are subject to change without notice. (at VS = ± 15 V, TA = 25/H11543C, unless otherwise noted.)
REV. A –3– OP215 SPECIFICATIONS Parameter Symbol Conditions Min Type Max Min Type Max Unit Input Offset Voltage V OS RS = 50 W 0.4 1.65 3.5 8.0 mV Average Input Offset Voltage Drift Without External Trim 1 TCVOS 31 5 6 /H9262V/∞C With External Trim TCV OSn RP = 100 kW 34 /H9262V/∞C Input Offset Current2 IOS Tj = 70∞C 0.06 0.45 0.08 0.65 nA TA = 70∞C 0.08 0.80 0.10 1.2 nA Device Operating Input Bias Current2 IS Tj = 70∞C ± 0.12 ± 0.70 ± 0.14 ± 0.9 nA Device Operating Input Voltage Range IVR 10.2 14.7 10.1 14.7 V Common-Mode CMRR V CM = ± IVR 80 98 7 69 4 d B Rejection Ratio Power Supply Rejection PSRR V S = ± 10 V to ± 16 V 13 100 Ratio V S = ± 10 V to ± 15 V 20 159 /H9262V/V Large-Signal A VO RL /H11350 2 kW 50 180 35 130 V/mV Voltage Gain V O = ± 10 V Output Voltage Swing V O RL /H11350 10 kW± 12 ± 13 ± 12 ± 13 V NOTES 1Sample tested. 2Input bias current is specified for two different conditions. The T j = 25∞C specification is with the junction at ambient temperature; the Device Operating specification is with the device operating in a warmed up condition at 25 ∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standar d JFET input op amps. I S and IOS are measured at V CM = 0. Specifications are subject to change without notice. (at VS = ±15 V, 0/H11543C /H11349 TA /H11349 70/H11543C for E Grade, –40 /H11543C /H11349 TA /H11349 +85/H11543C for G Grade, unless otherwise noted.)
REV. A OP215 –4– ORDERING INFORMATION 1 Package Temperature T A = 25∞C, Model Type Range V OS Max (mV) OP215EZ2 8-Lead CerDIP COM 1.0 OP215GP2 8-Lead Plastic DIP XIND 6.0 For military processed devices, please refer to the standard microcircuit drawing (SMD) available at www.dscc.dla.mil/programs/milspec/default.asp SMD Part Number ADI Equivalent 5962-8853801GA2 OP215AJMDA 5962-8853801PA OP215AZMDA 5962-8838032A2 OP215BRCMDA NOTES 1Burn-in is available on commercial and industrial temperature range parts in CerDIP and plastic DIP packages. 2Not for new design, obsolete April 2002. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP215 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage Operating Temperature Range Differential Input Voltage Input Voltage2 Junction Temperature (T NOTES 1Absolute maximum ratings apply to packaged parts, unless otherwise noted. 2Unless otherwise specified, the absolute maximum negative input voltage is equal to one volt more positive than the negative power supply voltage. Package Type /H9258JA * /H9258JC Unit 8-Lead Hermetic DIP (Z) 134 12 ∞C/W 8-Lead Plastic DIP (P) 96 37 ∞C/W */H9258JA is specified for worst-case mounting conditions, i.e., /H9258JA is specified for device in socket for CerDIP and P-DIP packages. PIN CONFIGURATION OUT B IN B +IN B OUT A IN A +IN A + + AB
REV. A –5– Typical Performance Characteristics–OP215 100 500ns TPC 1. Large-Signal Transient Response FREQUENCY Hz GAIN dB 1M 10M 100M 10 100 110 120 130 140 150 160 170 180 190 200 PHASE SHIFT Degrees PHASE MARGIN = 66/H11543 AV > 10 AV = 1VS = /H1155015V TA = 25/H11543C TPC 4. Closed-Loop Bandwidth and Phase Shift vs. Frequency FREQUENCY Hz PEAK-TO-PEAK AMPLITUDE V 100K 1M 10M VS = /H1155015V TA = 25/H11543C AV = /H115451 TPC 7. Maximum Output Swing vs. Frequency 100 100ns 20mV TPC 2. Small-Signal Transient Response TEMPERA TURE /H11543C BANDWIDTH MHz 50 VS = /H1155015V BANDWIDTH VARIA TION FROM /H115505 < VS < /H1155020V IS < 5% CLOSED-LOOP BANDWIDTH AV = /H115451 GAIN BANDWIDTH PRODUCT 25 0 25 50 75 100 125 TPC 5. Bandwidth vs. Temperature AMBIENT TEMPERA TURE /H11543C SLEW RA TE V//H9262s 50 AV = /H115451 VS = /H1155015V NEGA TIVE 25 0 25 50 75 100 125 POSITIVE TPC 8. Slew Rate vs. Temperature SETTLING TIME /H9262s OUTPUT VOL T AGE SWING FROM 0V V 10 VS = /H1155015V TA = 25/H11543C AV = 1 10mV 5mV 1mV 10mV 5mV 1mV TPC 3. Settling Time FREQUENCY Hz OPEN-LOOP VOL T AGE GAIN dB 120 -20 10 100 1k 10k 100k 1M 10M 100 100M VS = /H1155015V TA = 25/H11543C TPC 6. Open-Loop Frequency Response FREQUENCY Hz COMMON-MODE REJECTION RA TIO dB 100 10 100 1k 10k 100k 1M 10M 100M VS = /H1155015V TA = 25/H11543C TPC 9. Common-Mode Rejection Ratio vs. Frequency
Figure 5. Burn-In Circuit the capacitance from the input to ground. Dimensions shown in inches and (mm).
REV. A–8– C02683–0–4/02(A) PRINTED IN U.S.A. OP215
Revision History
Data Sheet changed from REV. 0 to REV. A.