OP184EP

OP-184 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Precision Rail-to-Rail Input & Output Operational Amplifiers OP184/OP284/OP484

FEATURES

Wide Bandwidth: 4 MHz Low Offset Voltage: 65 mV Unity-Gain Stable High Slew Rate: 4.0 V/ ms Low Noise: 3.9 nV/ √Hz

APPLICATIONS

Battery Powered Instrumentation Power Supply Control and Protection Telecom DAC Output Amplifier ADC Input Buffer GENERAL DESCRIPTION The OP184/OP284/OP484 are single, dual and quad single- supply, 4 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. They are guaranteed to operate from +3 to +36 (or ± 1.5 to ± 18) volts and will function with a single supply as low as +1.5 volts. These amplifiers are superb for single supply applications re- quiring both ac and precision dc performance. The combination of bandwidth, low noise and precision makes the OP184/OP284/ OP484 useful in a wide variety of applications, including filters and instrumentation. Other applications for these amplifiers include portable telecom equipment, power supply control and protection, and as amplifi- ers or buffers for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezo electric, and resistive transducers. The ability to swing rail-to-rail at both the input and output en- ables designers to build multistage filters in single-supply sys- tems and to maintain high signal-to-noise ratios. The OP184/OP284/OP484 are specified over the HOT extended industrial (–40°C to +125°C) temperature range. The single and dual are available in 8-pin plastic DIP plus SO surface mount packages. The quad OP484 is available in 14-pin plastic DIPs and 14-lead narrow-body SO packages. PIN CONFIGURATIONS 8-Lead Epoxy DIP (P Suffix) 8-Lead SO (S Suffix) OUT A NULL NCNULL –IN A +IN A OP184 NC = NO CONNECT 8-Lead Epoxy DIP (P Suffix) 8-Lead SO (S Suffix) OP284 OUT B –IN B +IN B V+OUT A –IN A +IN A 14-Lead Epoxy DIP (P Suffix) 14-Lead Narrow-Body SO (S Suffix) OP484 OUT A –IN A +IN A +IN B –IN B OUT B OUT D –IN D +IN D +IN C –IN C OUT C Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996

OP184/OP284/OP484–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage “OP184/284E” Grade V OS (Note 1) 65 µV –40°C ≤ TA ≤ +125°C 165 µV Offset Voltage “OP184/284F” Grade V OS 125 µV –40°C ≤ TA ≤ +125°C 350 µV Offset Voltage “OP484E” Grade V OS 75 µV –40°C ≤ TA ≤ +125°C 175 µV Offset Voltage “OP484F” Grade V OS 150 µV –40°C ≤ TA ≤ +125°C 450 µV Input Bias Current I B 60 350 nA –40°C ≤ TA ≤ +125°C 575 nA Input Offset Current I OS 25 0 n A –40°C ≤ TA ≤ +125°C5 0 n A Input Voltage Range 0+ 5 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 5 V 60 dB Common-Mode Rejection Ratio CMRR V CM = 1.0 V to 4.0 V, –40°C ≤ TA ≤ +125°C8 6 d B Large Signal Voltage Gain A VO RL = 2 kΩ , 1 V ≤ VO ≤ 4 V 50 240 V/mV RL = 2 kΩ , –40°C ≤ TA ≤ +125°C 25 V/mV Bias Current Drift ΔIB/ΔT 150 pA/ °C OUTPUT CHARACTERISTICS Output Voltage High V OH IL = 1.0 mA +4.85 V Output Voltage Low V OL IL = 1.0 mA 125 mV Output Current I OUT ± 6.5 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V S = +2.0 V to +10 V, –40°C ≤ TA ≤ +125°C7 6 d B Supply Current/Amplifier I SY VO = 2.5 V, –40°C ≤ TA ≤ +125°C 1.45 mA Supply Voltage Range V S +3 +36 V DYNAMIC PERFORMANCE Slew Rate SR R L = 2 kΩ 1.65 2.4 V/ µs Settling Time t s To 0.01%, 1.0 V Step 2.5 µs Gain Bandwidth Product GBP 3.25 MHz Phase Margin Øo 45 Degrees NOISE PERFORMANCE Voltage Noise e n p-p 0.1 Hz to 10 Hz 0.3 µV p-p Voltage Noise Density e n f = 1 kHz 3.9 nV/ √Hz Current Noise Density i n 0.4 pA/ √Hz NOTES 1Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. Specifications subject to change without notice. REV. 0–2– (@ VS = +5.0 V, VCM = 2.5 V, TA = +258C unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage “OP184/284E” Grade V OS (Note 1) 65 µV –40°C ≤ TA ≤ +125°C 165 µV Offset Voltage “OP184/284F” Grade V OS 125 µV –40°C ≤ TA ≤ +125°C 350 µV Offset Voltage “OP484E” Grade V OS 100 µV –40°C ≤ TA ≤ +125°C 200 µV Offset Voltage “OP484F” Grade V OS 150 µV –40°C ≤ TA ≤ +125°C 450 µV Input Bias Current I B 60 350 nA –40°C ≤ TA ≤ +125°C 575 nA Input Offset Current I OS –40°C ≤ TA ≤ +125°C5 0 n A Input Voltage Range 0+ 3 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 3 V 60 dB Common-Mode Rejection Ratio CMRR V CM = 0 V to 3 V, –40°C ≤ TA ≤ +125°C5 6 d B OUTPUT CHARACTERISTICS Output Voltage High V OH IL = 1.0 mA +2.85 V Output Voltage Low V OL IL = 1.0 mA 125 mV POWER SUPPLY Power Supply Rejection Ratio PSRR V S = ± 1.25 V to ± 1.75 V 76 dB Supply Current/Amplifier I SY VO = 1.5 V, –40°C ≤ TA ≤ +125°C 1.35 mA DYNAMIC PERFORMANCE Gain Bandwidth Product GBP 3 MHz NOISE PERFORMANCE Voltage Noise Density e n f = 1 kHz 3.9 nV/ √Hz NOTES 1Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. Specifications subject to change without notice. REV. 0 –3– OP184/OP284/OP484 (@ VS = +3.0 V, VCM = 1.5 V, TA = +258C unless otherwise noted)

REV. 0–4– OP184/OP284/OP484 Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage “OP184/284E” Grade VOS (Note 1) 100 µV –40°C ≤ TA ≤ +125°C 200 µV Offset Voltage “OP284F” Grade V OS 175 µV –40°C ≤ TA ≤ +125°C 375 µV Offset Voltage “OP484E” Grade V OS 150 µV –40°C ≤ TA ≤ +125°C 300 µV Offset Voltage “OP484F” Grade V OS 250 µV –40°C ≤ TA ≤ +125°C 500 µV Input Bias Current I B 80 350 nA –40°C ≤ TA ≤ +125°C 575 nA Input Offset Current I OS –40°C ≤ TA ≤ +125°C5 0 n A Input Voltage Range –15 +15 V Common-Mode Rejection Ratio CMRR V CM = –14.0 V to +14.0 V, –40°C ≤ TA ≤ +125°C8 6 9 0 d B Common-Mode Rejection Ratio CMRR V CM = –15.0 V to +15.0 V 80 dB Large Signal Voltage Gain A VO RL = 2 kΩ , –10 V ≤ VO ≤ 10 V 150 1000 V/mV RL = 2 kΩ , –40°C ≤ TA ≤ +125°C 75 V/mV Offset Voltage Drift “E” Grade ΔVOS/ΔT 0.2 2.00 µV/°C Bias Current Drift ΔIB/ΔT 150 pA/ °C OUTPUT CHARACTERISTICS Output Voltage High V OH IL = 1.0 mA +14.8 V Output Voltage Low V OL IL = 1.0 mA –14.875 V Output Current I OUT ± 10 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V S = ± 2.0 V to ± 18 V, –40°C ≤ TA ≤ +125°C9 0 d B Supply Current/Amplifier I SY VO = 0 V, –40°C ≤ TA ≤ +125°C 2.0 mA Supply Current/Amplifier I SY VS = ± 18 V, –40°C ≤ TA ≤ +125°C 2.25 mA DYNAMIC PERFORMANCE Slew Rate SR R L = 2 kΩ 2.4 4.0 V/ µs Full-Power Bandwidth BW p 1% Distortion, RL = 2 kΩ , VO = 29 V p-p 35 kHz Settling Time t S To 0.01%, 10 V Step 4 µs Gain Bandwidth Product GBP 4.25 MHz Phase Margin Øo 50 Degrees NOISE PERFORMANCE Voltage Noise e n p-p 0.1 Hz to 10 Hz 0.3 µV p-p Voltage Noise Density e n f = 1 kHz 3.9 nV/ √Hz Current Noise Density i n 0.4 pA/ √Hz NOTES 1Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. Specifications subject to change without notice. WAFER TEST LIMITS Parameter Symbol Conditions Limit Units Offset Voltage OP284 V OS 65 µV max Offset Voltage OP484 V OS 75 µV max Input Bias Current I B 350 nA max Input Offset Current I OS 50 nA max Input Voltage Range V CM V– to V+ V min Common-Mode Rejection Ratio CMRR V CM = +1 V to +4 V 86 dB min Power Supply Rejection Ratio PSRR V S = ± 2 V to ± 18 V 90 dB min Large Signal Voltage Gain A VO RL = 2 kΩ 50 V/mV min Output Voltage High V OH IL = 1.0 mA 4.85 V min Output Voltage Low V OL IL = 1.0 mA 125 mV max Supply Current/Amplifier I SY VO = 0 V, RL = ∞ 1.45 mA max NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. (@ VS = +5.0 V, VCM = 2.5 V, TA = +258C unless otherwise noted) (@ VS = 615.0 V, VCM = 0 V, TA = +258C unless otherwise noted)

than 5 mA to prevent degradation or destruction of the input devices. Substrate (Die Backside) Is Connected to V–. Substrate (Die Backside) Is Connected to V–. Figure 1. Simplified Schematic

approximately 1 µs to recover from negative saturation. Figure 48. Output Overload Recovery Test Circuit Figure 49. A Single Supply, +3 V Low Noise Instrumenta-

2.5 V references require at least a minimum operating supply of

total change in load current of ± 1 mA. Figure 50. A +2.5 V Reference that Operates on a Single

inverting and not usable in single supply applications.

13 DAC8043

Figure 51. A +5 V Only, 12-Bit DAC Swings Rail-to-Rail Figure 52. A High-Side Load Current Monitor value of the resistor and capacitor is best determined empirically. Figure 53. Snubber Network Compensates for Capacitive

tain this threshold voltage between 20 mV and 50 mV. takes into account the SO-8 device’s 2.5 W, 25°C dissipation. input to R1, leaving the U1A/B amplifiers and Q1 still active. configures the active filter to reject 50 Hz interference. Figure 56. A +3 V Single Supply, 50/60 Hz Active Notch

REV. 0 –17– OP184/OP284/OP484 *OP284 SPICE Macro-model 9/94 / Rev. A * ARG/ADI * Copyright 1995 by Analog Devices * Refer to “README.DOC” file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * Node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply .SUBCKT OP284 1 2 99 50 45 * INPUT STAGE Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1 IOS 2 1 5E-9 CIN 1 2 2E-12 GN1 98 1 (17,98) 1E-3 GN2 98 2 (23,98) 1E-3 * VOLTAGE NOISE SOURCE WITH FLICKER NOISE VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * CURRENT NOISE SOURCE WITH FLICKER NOISE VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * GAIN STAGE EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R9 20 98 1E3 * COMMON MODE STAGE WITH ZERO AT 100Hz ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 1.592E-3 * NEGATIVE ZERO AT 20MHz E1 27 98 (20,98) 1E6 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 (27,28) 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * POLE AT 40MHz G4 98 29 (28,98) 1 R19 29 98 1 C9 29 98 3.979E-9 * POLE AT 40MHz G5 98 30 (29,98) 1 R20 30 98 1 C10 30 98 3.979E-9 * OUTPUT STAGE ISY 99 50 0.276E-3 GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0

REV. 0–18– OP184/OP284/OP484 FSCP 46 99 VSCP 1 RSCP 46 99 40 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0 FSCN 50 47 VSCN 1 RSCN 47 50 40 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=200 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=100 VA=60 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160) .ENDS

REV. 0 –19– OP184/OP284/OP484 14-Lead Epoxy DIP (P Suffix) 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 14-Lead Narrow-Body SO (S Suffix) 14 8 0.3444 (8.75) 0.3367 (8.55) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 8-Lead Epoxy DIP (P Suffix) 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15)0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-Lead SO (S Suffix) 0.1968 (5.00) 0.1890 (4.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° OUTLINE DIMENSIONS Dimensions shown in inches and (mm).

PRINTED IN U.S.A. C2167–12–10/96 –20–