OP177_06 AD | Alldatasheet

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Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

TA = 25°C, 25 μV maximum Outstanding offset voltage drift 0.1 μV/°C maximum Excellent open-loop gain and gain linearity

12 V/μV typical

CMRR: 130 dB minimum PSRR: 115 dB minimum Low supply current 2.0 mA maximum Fits industry-standard precision op amp sockets PIN CONFIGURATION NC = NO CONNECT –IN +IN OUT NCV– VOS TRIM VOS TRIM 00289-001 OP177 TOP VIEW (Not to Scale) Figure 1. 8-Lead PDIP (P-Suffix), high closed-loop gain applications. well as the space saving 8-lead SOIC. *R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY. Figure 2. Simplified Schematic

Rev. E | Page 2 of 16 TABLE OF CONTENTS Thermocouple Amplifier with Cold-Junction

REVISION HISTORY

5/06—Rev. D to Rev. E 4/06—Rev. C to Rev. D 1/05—Rev. B to Rev. C 11/95—Rev. 0: Initial Version

Rev. E | Page 3 of 16 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

@ VS = ±15 V , TA = 25°C, unless otherwise noted. Table 1. OP177F OP177G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE VOS 10 25 20 60 μV LONG-TERM INPUT OFFSETT Voltage Stability ΔVOS/time 0.3 0.4 μV/mo INPUT OFFSET CURRENT IOS 0.3 1.5 0.3 2.8 nA INPUT NOISE VOLTAGE en fO = 1 Hz to 100 Hz2 118 150 118 150 nV rms INPUT NOISE CURRENT in fO = 1 Hz to 100 Hz2 3 8 3 8 pA rms INPUT RESISTANCE Differential Mode3 RIN 26 45 18.5 45 MΩ INPUT RESISTANCE COMMON MODE RINCM 200 200 GΩ INPUT VOLTAGE RANGE4 IVR ±13 ±14 ±13 ±14 V COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 130 140 115 140 dB POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 115 125 110 120 dB LARGE SIGNAL VOLTAGE GAIN AVO RL ≥ 2 kΩ, VO = ±10 V5 5000 12,000 2000 6000 V/mV OUTPUT VOLTAGE SWING VO RL ≥ 10 kΩ ±13.5 ±14.0 ±13.5 ±14.0 V SLEW RATE2 SR RL ≥ 2 kΩ 0.1 0.3 0.1 0.3 V/μs CLOSED-LOOP BANDWIDTH2 BW AVCL = 1 0.4 0.6 0.4 0.6 MHz OPEN-LOOP OUTPUT RESISTANCE RO 60 60 Ω POWER CONSUMPTION PD VS = ±15 V, no load 50 60 50 60 mW VS = ±3 V, no load 3.5 4.5 3.5 4.5 mW SUPPLY CURRENT ISY VS = ±15 V, no load 1.6 2 1.6 2 mA OFFSET ADJUSTMENT RANGE RP = 20 kΩ ±3 ±3 mV 1 Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 μV. 2 Sample tested. 3 Guaranteed by design. 4 Guaranteed by CMRR test condition. 5 To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.

1 For supply voltages less than ±22 V, the absolute maximum input voltage is

equal to the supply voltage. device soldered to printed circuit board for SOIC package. Table 4. Thermal Resistance degradation or loss of functionality.

0 INPUT BIAS CURRENT (nA)

Figure 12. Input Bias Current vs. Temperature Figure 13. Input Offset Current vs. Temperature Figure 14. Closed-Loop Response for Various Gain Configurations Figure 15. Open-Loop Frequency Response Figure 16. CMRR vs. Frequency Figure 17. PSRR vs. Frequency

determined by the size of CH and the bias current of the AD820. CC is selected to smooth the response of the loop. Figure 32. Precision Threshold Detector/Amplifier

Rev. E | Page 14 of 16 ORDERING GUIDE Model Temperature Range Package Description Package Option OP177FP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8) OP177FPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8) OP177GP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8) OP177GPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8) OP177FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177FS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177FSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177FSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177FSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) OP177GSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1 Z = Pb-free part.

Rev. E | Page 15 of 16 NOTES

Rev. E | Page 16 of 16 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00289-0-5/06 (E)