OP15

OP15 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a OP15/OP17 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Precision JFET-Input Operational Amplifiers OUTPUT *R7, R8 ARE ELECTRONICALL Y ADJUSTED ON CHIP FOR MINIMUM OFFSET VOL T AGE. 7.4pF J1 J2 Q7R3 NONINVERTING INPUT –INV INPUT R8* R7* NULL NULL J11 Q12 Q11 Q1 Q2 Q3 Q4 3.6k/H9024 Q16 Q13 Q16 J6Q9 R2 C2 3.6k/H9024 Q15 Q14 Q19 Q17 Q10 Q21 Q20 R13 Q24 Q22 J10 Q23 Q25 R11 Figure 1. Simplified Schematic

FEATURES

Significant Performance Advantages over LF155 and LF157 Devices Low Input Offset Voltages: 500 /H9262V Max Low Input Offset Voltage Drift: 2.0 /H9262V//H11543C Minimum Slew Rate Guaranteed on All Models Temperature-Compensated Input Bias Currents Bias Current Specified Warmed-Up Over Temperature Internal Compensation Low Input Noise Current: 0.01 pA/ ÷÷÷÷÷Hz High Common-Mode Rejection Ratio: 100 dB Models with MIL-STD 883 Processing Available OP15

156 Speed with 155 Dissipation: 80 mW Typ

Wide Bandwidth: 6 MHz High Slew Rate: 13 V/ /H9262s Fast Settling to ±0.1%: 1,200 ns OP17 Highest Slew Rate: 60 V/ /H9262s Fastest Settling to ±0.1%: 600 ns Highest Gain Bandwidth Product (A VCL = 5 Min): 30 MHz Guaranteed Input Bias Current @ 125 /H11543C GENERAL DESCRIPTION The ADI-JFET input series of devices offer clear advantages over industry-generic devices and are superior in both cost and perfor- mance to many dielectrically-isolated and hybrid op amps. All devices offer offset voltages as low as 0.5 mV with TCV OS guaranteed to 5 mV/∞C. A unique input bias cancellation circuit reduces the I B by a factor 10 over conventional designs. In addition ADI specifies I B and IOS with the devices warmed up and operating at 25∞C ambient. These devices were designed to provide real precision performance along with high speed. Although they can be nulled, the design objective was to provide low offset-voltage without nulling. Systems generally become more cost effective as the number of trim circuits is decreased. ADI achieves this performance by use of an improved bipolar compatible JFET process coupled with on chip, zener-zap offset trimming. The OP15 provides an excellent combinations of high speed and low input offset voltage. In addition, the OP15 offers the speed of the 156A op amp with the power dissipation of a 155A. The combination of a low input offset voltage of 500 mV, slew rate of 13 V/ms, and settling time of 1,200 ns to 0.1% makes the OP15 an op amp of both precision and speed. The additional features of low supply current coupled with an input bias current makes the OP15 ideal for a wide range of applications. The OP17 has a slew rate of 60 V/ ms and is the best choice for applications requiring high closed-loop gain with high speed. See OP42 datasheet for unity gain applications and the OP215 datasheet for a dual configuration of the OP15.

REV. A–2– OP15/OP17–SPECIFICATIONS OP15A, OP15E OP15F OP15G OP17A, OP17E OP17F OP17G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Input Offset Current I OS OP15 T J = 25∞C1 31 0 62 0 12 50 pA Device Operating 5 22 10 40 20 100 pA OP17 T J = 25∞C1 31 0 62 0 12 50 pA Device Operating 5 25 10 50 20 125 pA Input Bias Current I B OP15 T J = 25∞C1 ±15 ±50 ±30 ±100 ±60 ±200 pA Device Operating ±18 ±110 ±40 ±200 ±80 ±400 pA OP17 T J = 25∞C1 ±15 ±50 ±30 ±100 ±60 ±200 pA Device Operating ±20 ±130 ±40 ±250 ±80 ±500 pA Input Resistance R IN 1012 1012 1012 W Large-Signal A VO RL ≥ 2 kW 100 240 75 220 50 200 V/mV Voltage Gain V O = ±10 V Output Voltage V O RL = 10 kW± 12 ±13 ±12 ±13 ±12 ±13 V Swing R L = 2 kW± 11 ±12.7 ±11 ±12.7 ±11 ±12.7 V Slew Rate2 SR A VCL = 1, OP15 10 13 7.5 11 5 9 V/ ms AVCL = 5, OP17 45 60 35 50 25 40 V/ ms Product OP17 20 30 15 28 11 26 MHz Closed-Loop CLBW A VCL = 1, OP15 14 13 12 MHz Bandwidth A VCL = 5, OP17 11 10 9 MHz Settling Time t S OP15 To 0.01% 4.5 4.5 4.7 ms To 0.05% 1.5 1.5 1.6 ms To 0.10% 1.2 1.2 1.3 ms OP17 To 0.01% 1.5 1.5 1.6 ms To 0.05% 0.7 0.7 0.8 ms To 0.10% 0.6 0.6 0.7 ms Input Voltage Range IVR ±10.5 ±10.5 ±10.3 V Common-Mode CMRR V CM = ±10.5 V 86 100 86 100 dB Rejection Ratio V CM = ±10.3 V 82 96 dB Power Supply PSRR V S = ±10 V to ±18 V 10 5 11 0 5 1 mV/V Rejection Ratio V S = ±10 V to ±18 V 10 80 mV/V Input Noise e n fO = 100 Hz 20 20 20 nV/ ÷Hz Voltage Density f O = 1 kHz 15 15 15 nV/ ÷Hz Input Noise i n fO = 100 Hz 0.01 0.01 0.01 pA/ ÷Hz Current Density f O = 1 kHz 0.01 0.01 0.01 pA/ ÷Hz Input Capacitance C IN 33 3 p F NOTES 1Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed-up condition at 25 ∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and IOS are measured at V CM = 0. 2Settling time is defined here for a unity gain inverter connection using 2 k W resistors. It is the time required for the error voltage (the voltages at the inverting input pit on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit. 3Sample tested. 4Settling time is defined here for AV = –5 connection with RF = 2 kW. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test cir cuit. ELECTRICAL CHARACTERISTICS(@ VS = /H1155015 V, TA = 25/H11543C, unless otherwise noted)

REV. A –3– OP15/OP17

Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units Input Offset Voltage V OS RS = 50 W 0.4 0.9 mV Average Input Offset Voltage Drift 1 Without External Trim TCV OS 25 mV/∞C With External Trim TCV OS RP = 100 W 2 mV/∞C Input Offset Current2 IOS TJ = 125∞C 0.6 4.0 nA OP17 T A = 125∞C, device operating 1.0 8.5 nA Input Bias Current2 IB TJ = 125∞C ±1.2 ±5.0 nA OP17 T A = 125∞C, device operating ±2.0 ±11 nA Input Voltage Range IVR ±10.4 V Common-Mode Rejection Ratio CMRR V CM = ±10.4 V 85 97 dB Power Supply Rejection Ratio PSRR V S = ±10 V to ±18 V 15 57 mV/V Large Signal Voltage Gain A VO RL ≥ 2 kW, VO = ± 10 V 35 120 V/mV Output Voltage Swing V O RL ≥ 10 kW± 12 ±13 V NOTES 1Sample tested. 2Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed-up condition at 25 ∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and IOS are measured at V CM = 0. (@ VS = ±15 V, –55 /H11543C £ TA £ 125/H11543C, unless otherwise noted.) OP15E/OP17E OP15F/OP17F OP15G/OP17G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Average Input Offset Voltage Drift 1 Without External Trim TCVOS 25 31 0 43 0 mV/∞C With External Trim TCV OSn RP = 100 W 23 4 mV/∞C Input Voltage Range IVR ±10.4 ±10.4 ±10.25 V Common-Mode CMRR V CM = ±10.4 V 85 98 85 96 dB Rejection Ratio V CM = ±10.25 V 80 94 dB Power Supply PSRR V S = ±10 V to ±18 V 13 5 71 3 5 7 mV/V Rejection Ratio V S = ±10 V to ±15 V 20 100 mV/V Large Signal A VO RL ≥ 2 kW 65 200 50 180 35 160 V/mV Voltage Gain V O = ±10 V Output Voltage V O RL ≥ 10 kW± 12 ±13 ±12 ±13 ±12 ±13 V Swing NOTES 1Sample tested. 2Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed-up condition at 25 ∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and IOS are measured at V CM = 0. (@ VS = /H1155015 V, 0/H11543C £ TA £ 70/H11543C for E and F grades, –40 /H11543C £ TA £ 85/H11543C for G grades unless otherwise noted)

*Absolute Maximum Ratings apply to packaged parts, unless otherwise noted. printed circuit board for SO packages.

0.5 OP17EJ OP15EZ COM

1.0 OP15FJ * OP15FZ* COM

3.0 OP15GJ * OP15GZ* OP15GS* XIND

*Not recommended for new designs. Obsolete April 2002. Figure 2. Burn-In Circuit

REV. A –5– OP15/OP17 OUTPUT LOAD RESIST ANCE – /H9024 100 100 k1k PEAK-TO-PEAK OUTPUT SWING – V 10k –55/H11543C +25/H11543C +125/H11543C VS = 15V TPC 1. Maximum Output Swing vs. Load Performance SUPPL Y VOL T AGE – V 0 205 COMMON-MODE INPUT VOL T AGE RANGE – V 10 15

5 POSITIVE

TA = 25/H11543C FROM –55/H11543C TO –125/H11543C CHANGE IN CMVR IS < 0.2V TPC 2. Common-Mode Input Voltage Range vs. Supply Voltage 10G100k SOURCE RESIST ANCE – /H9024 100

0.01 INPUT NOISE VOL T AGE – /H9262V

0.1 1M 10M 100M 1G TA = 25/H11543C VS = 15V 100Hz < f < 10kHz 10Hz < f < 10kHz FOR RS > 4M/H9024 a AMPLIFIER NOISE b JOHNSON RESISTOR NOISE c AMPLIFIER NOISE MEASURED WITH SOURCE RESISTOR a c b TPC 3. Voltage Noise vs. Source Resistance INPUT COMMON-MODE VOL T AGE – V –20 –12 1 2–10 INPUT BIAS CURRENT – pA –8 –6 –4 –2 0 2 4 6 8 10 100 WARMED-UP IN FREE AIR VS = 15V TA = 25/H11543C a. UNDERCANCELLED IB = +16pA @ VCM = 0 b. PERFECTL Y CANCELLED IB = 0pA @ VCM = 0 c. UNDERCANCELLED IB = –16pA @ VCM = 0 a cb TPC 4. Input Bias Current vs. Common-Mode Voltage SUPPL Y VOL T AGE – V 10k 5 2015 OPEN-LOOP VOL T AGE GAIN – V/V 100k 200k 300k 400k 500k RL = 2k/H9024 –55/H11543C 25/H11543C 125/H11543C TPC 5. Open-Loop Voltage Gain vs. Supply Voltage SUPPL Y VOL T AGE – V 0 205 PEAK-TO-PEAK OUTPUT SWING – V 10 15 R L = 2k/H9024 TA = 25/H11543C TPC 6. Output Voltage Swing vs. Supply Voltage Typical Performance Characteristics –

REV. A OP15/OP17 –6– RP-TRIMMING POTENTIOMETER VALUE – /H9024 10k 1M 100k NULLED OFFSET VOL T AGE DRIFT – /H9262V//H11543C TYPICAL DRIFT BAND VOS TPC 7. Nulled Offset Voltage Drift vs. Potentiometer Size TEMPERA TURE – /H11543C –6–50 125 –25 OFFSET VOL T AGE – mV 02 5 5 07 5 100 VS = 15V TPC 8. Offset Voltage Drift vs. Temperature of Representative Units AMBIENT TEMPERA TURE – /H11543C 100n 10n 10p10 150 30 INPUT BIAS CURRENT – A 50 70 90 110 130 100p VS = 15V UNITS ARE WARMED UP 155A MAX 155A TYP OP15A MAXP OP15 TYP TPC 9. Input Bias Current vs. Ambient Temperature (Units Warmed Up in Free Air) TIME AFTER POWER APPLIED – s 10p 0 140120 INPUT BIAS CURRENT – A 100p VS = 15V TA = 25/H11543C ISY = 4.0mA FOR MAX CURVES 2.5mA FOR TYP CURVES 40 60 80 100 155A MAX 155A TYP OP15 TYP OP15A MAX TPC 10. OP15 Bias Current vs. Time in Free Air TIME AFTER POWER APPLIED – s 10p 01 4 0 120 INPUT BIAS CURRENT – A 100p VS = 15V TA = 25/H11543C ISY = 6.7mA FOR MAX CURVES 5.0mA FOR TYP CURVES 40 60 80 100 156A/157A TYP 156A/157A MAX OP17A TYP OP17A MAX TPC 11. OP17 Bias Current vs. Time in Free Air AMBIENT TEMPERA TURE – /H11543C 100n 10n 10p10 150 30 INPUT BIAS CURRENT – A 50 70 90 110 130 100p 155A MAX 155A TYP OP15A MAX OP15A TYP TPC 12. OP15 Input Bias Current vs. Ambient Temperature (Units Warmed Up in Free Air)

REV. A –7– OP15/OP17 AMBIENT TEMPERA TURE – /H11543C 100n 10n 10p10 150 30 INPUT BIAS CURRENT – A 50 70 90 110 130 100p 156A/157A MAX 156A/157A TYP OP17A MAX OP17A TYP TPC 13. OP1 7 Input Bias Current vs. Ambient Temperature (Units Warmed Up in Free Air) SUPPL Y VOL T AGE – V 3.5 3.0 1.5 0 205 SUPPL Y CURRENT – mA 10 15 2.5 2.0 –55/H11543C 25/H11543C 125/H11543C TPC 14. OP15 Supply Current vs. Supply Voltage SUPPL Y VOL T AGE – V 5.5 5.0 3.5 205 SUPPL Y CURRENT – mA 10 15 4.5 4.0 –55/H11543C 25/H11543C 125/H11543C TPC 15. OP17 Supply Current vs. Supply Voltage TIME – 500ns/DIV 00 0 VOLTAGE – 5V/DIV 0000 0 000 TPC 16. OP15 Large Signal Transient Response TIME – 100ns/DIV 00 0 VOLTAG E – 20mV/DIV 0000 0 000 TPC 17. OP15 Small Signal Transient Response SUPPL Y VOL T AGE – V –10 0 2.50.5 OUTPUT VOL T AGE SWING FROM 0V – V 10mV 1.0 1.5 2.0 5mV 1mV 10mV 5mV 1mV VS = 15V TA = 25/H11543C AV = –1 TPC 18 OP15 Settling Time

REV. A OP15/OP17 –8– FREQUENCY – MHz –10 1M 100M 10M VOLTAG E GAIN – dB VS = 15V TA = 25/H11543C AV > 10 AV = 1 PHASE MARGIN = 86/H11543 110 PHASE SHIFT – Degrees 130 150 170 190 100 120 140 160 180 200 TPC 19. OP15 Closed-Loop Bandwidth and Phase vs. Frequency TEMPERA TURE – /H11543C 0–50 125 –25 BANDWIDTH – MHz 02 5 5 07 5 1 0 0 CLOSED-LOOP BANDWIDTH AV = 1 GAIN BANDWIDTH PRODUCT BANDWIDTH VARIA TION FROM 5V < VS < 20V IS < 5 % VS = 15V TPC 20. OP15 Bandwidth vs. Temperature FREQUENCY – Hz 120 –20 1 100M10 OPEN-LOOP VOL T AGE GAIN – dB 100 1k 10k 100k 1M 10M 100 VS = 15V TA = 25/H11543C TPC 21. OP15 Open-Loop Gain vs. Frequency FREQUENCY – MHz 100k 10M 1M PEAK-TO-PEAK OUTPUT SWING – V VS = 15V TA = 25/H11543C AV = 1 TPC 22. OP15 Maximum Output Swing vs. Frequency AMBIENT TEMPERA TURE – /H11543C 0–50 125 –25 SLEW RA TE – V//H9262sec 02 5 5 07 5 100 NEGA TIVE POSITIVE VS = 15V AV = 1 TPC 23. OP15 Slew Rate vs. Temperature FREQUENCY – Hz 100 1 100M10 COMMON-MODE REJECTION RA TIO – dB 100 1k 10k 100k 1M 10M VS = 15V TA = 25/H11543C TPC 24. OP15 Common-Mode Rejection Ratio vs. Frequency

REV. A –9– OP15/OP17 FREQUENCY – Hz 120 POWER SUPPL Y REJECTION RA TIO – dB 100 1k 10k 100k 1M 10M TA = 25/H11543C 100 POSITIVE SUPPL Y NEGA TIVE SUPPL Y TPC 25. OP15 Power Supply Rejection Ratio vs. Frequency FREQUENCY – Hz 100 1k 10M 10k OUTPUT IMPEDANCE – /H9024 100k 1M VS = 15V TA = 25/H11543C AV = 100 AV = 10 AV = 1 TPC 26. OP15 Output Impedance vs. Frequency VOLTAGE NOISE DENSITY – nV/ Hz FREQUENCY – Hz 140 100 1k 10 M10k 100k 1M VS = 15V TA = 25/H11543C l/f CORNER FREQUENCY 120 TPC 27. OP15 Voltage Noise Density vs. Frequency TIME – 200ns/DIV 00 0 VOLTAGE – 5V/DIV 0000 0 000 TPC 28. OP17 Large Signal Transient Response TIME – 100ns/DIV 00 0 VOLTAG E – 20mV/DIV 0000 0 000 TPC 29. OP17 Small Signal Transient Response SUPPL Y VOL T AGE – V –10 02 . 5 0.5 OUTPUT VOL T AGE SWING FROM 0V – V 10mV 1.0 1.5 2.0 5mV VS = 15V TA = 25/H11543C AV = –5 10mV 5mV 1mV 1mV TPC 30. OP17 Settling Time

REV. A OP15/OP17 –10– FREQUENCY – MHz 100k 10M 1M PEAK-TO-PEAK OUTPUT SWING – V VS = 15V TA = 25/H11543C AV = 5 TPC 31. OP17 Maximum Output Swing vs. Frequency AMBIENT TEMPERA TURE – /H11543C 110 40–50 125 –25 SLEW RA TE – V//H9262sec 02 5 5 07 5 1 0 0 100 NEGA TIVE POSITIVE VS = 15V AV = 5 TPC 32. OP17 Slew Rate vs. Temperature FREQUENCY – Hz 100 1 100M10 COMMON-MODE REJECTION RA TIO – dB 100 1k 10k 100k 1M 10M VS = 15V TA = 25/H11543C TPC 33. OP17 Common-Mode Rejection Ration vs. Frequency FREQUENCY – Hz 120 POWER SUPPL Y REJECTION RA TIO – dB 100 1k 10k 100k 1M 10M TA = 25/H11543C 100 POSITIVE SUPPL Y NEGA TIVE SUPPL Y TPC 34. OP17 Power Supply Rejection Ratio vs. Frequency FREQUENCY – Hz 100 1k 10 M10k OUTPUT IMPEDANCE – /H9024 100k 1M 1.0 VS = 15V TA = 25/H11543C AV = 100 AV = 10 TPC 35. OP17 Output Impedance vs. FrequencyVOLTAGE NOISE DENSITY – nV/ Hz FREQUENCY – Hz 140 100 1k 10M 10k 100k 1M VS = 15V TA = 25/H11543C l/f CORNER FREQUENCY 120 TPC 36. OP17 Voltage Noise vs. Frequency

REV. A–12– C02789–0–9/02(A) PRINTED IN U.S.A. OP15/OP17 OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches). 8-Lead Ceramic Dip – Glass Hermetic Seal [CERDIP] (Q-8) 1 4 7.87 (0.3089) 5.59 (0.2201)PIN 1 0.13 (0.0051) MIN 1.40 (0.0551) MAX 2.54 (0.1000) BSC 8.13 (0.3201) 7.37 (0.2902) 0.38 (0.0150) 0.20 (0.0079) SEATING PLANE 5.08 (0.2000) MAX 10.29 (0.4051) MAX 3.81 (0.1500) MIN 5.08 (0.2000) 3.18 (0.1252) 0.58 (0.0228) 0.36 (0.0142) 1.78 (0.0701) 0.76 (0.0299) 1.52 (0.0600) 0.38 (0.0150) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Revision History

9/02—Data Sheet changed from REV. 0 to REV. A. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) /H11547 45/H11543 8/H11543 0/H11543 1.75 (0.0688) 1.35 (0.0532) SEATING PLANE 0.25 (0.0098) 0.10 (0.0040) 5.00 (0.1968) 4.80 (0.1890) PIN 1 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) BSC 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) COPLANARITY 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA 8-Lead Metal Can [TO-99] (H-08) 6.35 (0.2500) MIN 12.70 (0.5000) MIN4.70 (0.1850) 4.19 (0.1650) REFERENCE PLANE 1.27 (0.0500) MAX 0.48 (0.0190) 0.41 (0.0160) 0.53 (0.0210) 0.41 (0.0160) 1.02 (0.0400) 0.25 (0.0100) 1.02 (0.0400) MAX BASE & SEATING PLANE 0.86 (0.0340) 0.71 (0.0280) 1.14 (0.0450) 0.69 (0.0270) 4.06 (0.1600) 3.56 (0.1400) 2.54 (0.1000) BSC 2 8 5.08 (0.2000) BSC 2.54 (0.1000) BSC

45 BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-002AK 9.40 (0.3700) 8.51 (0.3350) 8.51 (0.3350) 7.75 (0.3050)