OP07EP

OP-07 TI1 | Alldatasheet

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OP-07 Low Offset, Low Drift Operational Amplifier Literature Number: SNOS556A

OP-07 Low Offset, Low Drift Operational Amplifier December 1994 OP-07 Low Offset, Low Drift Operational Amplifier General Description The OP-07 has very low input offset voltage which is ob- tained by trimming at the wafer stage. These low offset volt- ages generally eliminate any need for external nulling. The OP-07 also features low input bias current and high open- loop gain. The low offsets and high open-loop gain make the OP-07 particularly useful for high-gain applications. The wide input voltage range of g13V minimum combined with high CMRR of 110 dB and high input impedance pro- vide high accuracy in the non-inverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains. Stability of offsets and gain with time or variation in temper- ature is excellent. The OP-07 is available in TO-99 metal can, ceramic or molded DIP. For improved specifications, see the LM607.

Features

Y Low V OS Drift 0.6 mV/§C Max Y Ultra-Stable vs Time 1.0 mV/Month Max Y Low Noise 0.6 mVp-p Max Y Wide Input Voltage Range g14V Y Wide Supply Voltage Range g3V to g18V Y Fits 725/108A/308A, 741, AD510 Sockets Y Replaces the mA714

Applications

Y Precision Reference Buffer Y Analog Computing Functions Connection Diagram Dual-In-Line Package TL/H/10550–1 See NS Package Number N08E

Ordering Information

TA e 25§C N08E Operating VOSMax Plastic Temperature (mV) Range

75 OP07EP COM

150 OP07CP COM

150 OP07DP COM

*Also available per SMD Ý8203602 C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A. Obsolete

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage g22V Internal Power Dissipation (Note 5) 500 mW Differential Input Voltage g30V Input Voltage (Note 6) g22V Output Short-Circuit Duration Continuous Storage Temperature Range b65§Ct o a150§C Lead Temperature (Soldering, 60 sec.) 260 §C Junction Temperature b65§Ct o a150§C Operating Temperature Range OP-07E, OP-07C, OP-07D 0§Ct o a70§C Simplified Schematic TL/H/10550–3 *R2A and R2B are electronically trimmed on chip at the factory for minimum offset voltage. Obsolete

Electrical Characteristics

Unless otherwise specified, V S e g15V, T A e 25§C. Boldface type refers to limits over 0 §C s TA s 70§C Symbol Parameter Conditions OP-07E OP-07C Units Min Typ Max Min Typ Max VOS Input Offset Voltage (Note 1) 30 75 60 150 mV45 130 85 250 VOS/t Long-Term V OS (Note 2) 0.3 1.5 0.4 2.0 mV/MoStability en Input Noise Voltage f O e 10 Hz 10.3 18.0 10.5 20.0 Density fO e 100 Hz (Note 3) 10.0 13.0 10.2 13.5 nV/ 0Hz fO e 1000 Hz 9.6 11.0 9.8 11.5 inp-p Input Noise Current 0.1 Hz to 10 Hz (Note 3) 14 30 15 35 pA p-p in Input Noise Current f O e 10 Hz 0.32 0.80 0.35 0.90 Density f O e 100 Hz (Note 3) 0.14 0.23 0.15 0.27 pA/ 0Hz fO e 1000 Hz 0.12 0.17 0.13 0.18 RIN Input Resistance (Note 4) 15 50 8 33 MXDifferential-Mode RINCM Input Resistance 160 120 GXCommon-Mode IVR Input Voltage Range g13.0 g14.0 g13 g14 V CMRR Common-Mode V CM e g13V 106 123 100 120 dBRejection Ratio 103 123 97 120 PSRR Power Supply VS e g3V to g18V 5 20 7 32 mV/VRejection Ratio V S e g3V to g18V 73 2 1 0 5 1 AVO Large Signal RL t 2k X,V O e g10V 200 500 120 400 Voltage Gain R L t 2k X 180 450 100 400 V/mV RL t 500X,V O e g0.5V, 150 400 100 400VS e g3V (Note 4) VO Output Voltage Swing R L t 10 k X g12.5 g13.0 g12.0 g13.0 RL t 1k X g10.5 g12.0 g12.0 SR Slew Rate RL t 2k X (Note 3) 0.1 0.3 0.1 0.3 V/ ms BW Closed-Loop Bandwidth A VCL ea 1 (Note 3) 0.4 0.6 0.4 0.6 MHz RO Output Resistance V O e 0, I O e 06 0 6 0 X Pd Power Consumption V S e g15V, No Load 75 120 80 150 mWVS e g3V, No Load 4 6 4 8 Offset Adj. Range R P e 20 k X g4 g4m V TCVOS Average Input Offset (Note 4) 0.3 1.3 0.5 1.8 Voltage Drift Without mV/§CExternal Trim TCVOSn With External Trim R P e 20 k X (Note 4) 0.3 1.3 0.4 1.6 TCIOS Average Input Offset (Note 3) 83 5 1 2 5 0 pA/§CCurrent Drift TCIB Average Input Bias (Note 3) 13 35 18 50 pA/§CCurrent Drift Obsolete

Unless otherwise specified, V S e g15V, T A e 25§C. Boldface type refers to limits over 0 §C s TA s a 70§C Symbol Parameter Conditions OP-07D Units Min Typ Max VOS Input Offset Voltage (Note 1) 60 150 mV85 250 VOS/t Long-Term V OS Stability (Note 2) 0.5 3.0 mV/Mo IOS Input Offset Current 0.8 6.0 nA1.6 8.0 IB Input Bias Current g2.0 g12.0 nAg3.0 g14.0 enp-p Input Noise Voltage 0.1 Hz to 10 Hz (Note 3) 0.38 0.65 mVp-p en Input Noise Voltage Density f O e 10 Hz 10.5 20.0 fO e 100 Hz (Note 3) 10.3 13.5 nV/ 0Hz fO e 1000 Hz 9.8 11.5 inp-p Input Noise Current 0.1 Hz to 10 Hz (Note 3) 15 35 pAp-p in Input Noise Current Density f O e 10 Hz 0.35 0.90 pA/ 0Hz fO e 100 Hz (Note 3) 0.15 0.27 fO e 1000 Hz 0.13 0.18 RIN Input Resistance Differential-Mode (Note 4) 7 31 MX RINCM Input Resistance Common-Mode 120 GX IVR Input Voltage Range g13 g14 V CMRR Common-Mode VCM e g13V 94 110 dBRejection Ratio 94 106 PSRR Power Supply VS e g3V to g18V 7 32 mV/V Rejection Ratio 10 51 AVO Large Signal RL s 2k X,V O e g10V 120 400 Voltage Gain RL e 2k X,V O e g10V 100 400 V/mVRL t 500X,V O e g0.5V, 400VS g3V (Note 4) VO Output Voltage Swing RL t 10 k X g12.0 g13.0 RL t 2k X g11.5 g12.8 VRL t 2k X g11.0 g12.6 RL t 1k X g12.0 SR Slew Rate RL t 2k X (Note 3) 0.1 0.3 V/ ms BW Closed-Loop Bandwidth AVCL ea 1 (Note 3) 0.4 0.6 MHz RO Output Resistance VO e 0, I O e 06 0 X Pd Power Consumption VS e g15V, No Load 80 150 mWVS e g3V, No Load 4 8 Offset Adj. Range RP e 20 k X g4m V TCVOS Average Input Offset (Note 4) 0.7 2.5 mV/§C Voltage Drift Without External Trim TCVOSn With External Trim RP e 20 k X (Note 4) 0.7 2.5 mV/§C TCIOS Average Input Offset Current Drift (Note 3) 12 50 pA/§C TCIB Average Input Bias Current Drift (Note 3) 18 50 pA/§C Note 1: VOS is measured approximately 0.5 second after application of power. Note 2: Long-Term Offset Voltage Stability refers to the averaged trend line of V OS vs Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in V OS during the first 30 operating days are typically 2.5 mV. Parameter is sample tested. Note 3: Sample Tested. Note 4: Guaranteed by design. Obsolete

Offset Voltage Test Circuit TL/H/10550–4 Low Frequency Noise Test Circuit TL/H/10550–5 Optional Offset Nulling Circuit TL/H/10550–6 Obsolete

OP-07 Low Offset, Low Drift Operational Amplifier Physical Dimensions inches (millimeters) (Continued) Order Number OP-07EP, OP-07CP or OP-07DP LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Obsolete

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