OP07CSZ

OP07_06 AD | Alldatasheet

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Rev. D | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

7/06—Rev. C. to Rev D 8/03—Rev. B to Rev. C 3/03—Rev. A to Rev. B 2/02—Rev. 0 to Rev. A Edits to High-Speed, Low V

Rev. D | Page 3 of 16 SPECIFICATIONS OP07E ELECTRICAL CHARACTERISTICS VS = ±15 V , unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS TA = 25°C Input Offset Voltage1 VOS 30 75 μV Long-Term VOS Stability2 VOS/Time 0.3 1.5 μV/Month Input Offset Current IOS 0.5 3.8 nA Input Bias Current IB ±1.2 ±4.0 nA Input Noise Voltage en p-p 0.1 Hz to 10 Hz3 0.35 0.6 μV p-p Input Noise Voltage Density en fO = 10 Hz 10.3 18.0 nV/√Hz fO = 100 Hz3 10.0 13.0 nV/√Hz fO = 1 kHz 9.6 11.0 nV/√Hz Input Noise Current In p-p 14 30 pA p-p Input Noise Current Density In fO = 10 Hz 0.32 0.80 pA/√Hz fO = 100 Hz3 0.14 0.23 pA/√Hz fO = 1 kHz 0.12 0.17 pA/√Hz Input Resistance, Differential Mode4 RIN 15 50 MΩ Input Resistance, Common Mode RINCM 160 GΩ Input Voltage Range IVR ±13 ±14 V Common-Mode Rejection Ratio CMRR VCM = ±13 V 106 123 dB Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 5 20 μV/V Large Signal Voltage Gain AVO RL ≥ 2 kΩ, VO = ±10 V 200 500 V/mV RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4 150 400 V/mV 0°C ≤ TA ≤ 70°C Input Offset Voltage1 VOS 45 130 μV Voltage Drift Without External Trim4 TCVOS 0.3 1.3 μV/°C Voltage Drift with External Trim3 TCVOSN RP = 20 kΩ 0.3 1.3 μV/°C Input Offset Current IOS 0.9 5.3 nA Input Offset Current Drift TCIOS 8 35 pA/°C Input Bias Current IB ±1.5 ±5.5 nA Input Bias Current Drift TCIB 13 35 pA/°C Input Voltage Range IVR ±13 ±13.5 V Common-Mode Rejection Ratio CMRR VCM = ±13 V 103 123 dB Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 7 32 μV/V Large Signal Voltage Gain AVO RL ≥ 2 kΩ, VO = ±10 V 180 450 V/mV OUTPUT CHARACTERISTICS TA = 25°C Output Voltage Swing VO RL ≥ 10 kΩ ±12.5 ±13.0 V RL ≥ 2 kΩ ±12.0 ±12.8 V RL ≥ 1 kΩ ±10.5 ±12.0 V 0°C ≤ TA ≤ 70°C Output Voltage Swing VO RL ≥ 2 kΩ ±12 ±12.6 V

Rev. D | Page 4 of 16 Parameter Symbol Conditions Min Typ Max Unit DYNAMIC PERFORMANCE TA = 25°C Slew Rate SR RL ≥ 2 kΩ3 0.1 0.3 V/μs Closed-Loop Bandwidth BW AVOL = 15 0.4 0.6 MHz Open-Loop Output Resistance RO VO = 0, IO = 0 60 Ω Power Consumption Pd VS = ±15 V, No load 75 120 mW VS = ±3 V, No load 4 6 mW Offset Adjustment Range RP = 20 kΩ ±4 mV 1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. 2 Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is sample tested. 3 Sample tested. 4 Guaranteed by design. 5 Guaranteed but not tested. OP07C ELECTRICAL CHARACTERISTICS VS = ±15 V , unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS TA = 25°C Input Offset Voltage1 VOS 60 150 μV Long-Term VOS Stability2 VOS/Time 0.4 2.0 μV/Month Input Offset Current IOS 0.8 6.0 nA Input Bias Current IB ±1.8 ±7.0 nA Input Noise Voltage en p-p 0.1 Hz to 10 Hz3 0.38 0.65 μV p-p Input Noise Voltage Density en fO = 10 Hz 10.5 20.0 nV/√Hz fO = 100 Hz3 10.2 13.5 nV/√Hz fO = 1 kHz 9.8 11.5 nV/√Hz Input Noise Current In p-p 15 35 pA p-p Input Noise Current Density In fO = 10 Hz 0.35 0.90 pA/√Hz fO = 100 Hz3 0.15 0.27 pA/√Hz fO = 1 kHz 0.13 0.18 pA/√Hz Input Resistance, Differential Mode4 RIN 8 33 MΩ Input Resistance, Common Mode RINCM 120 GΩ Input Voltage Range IVR ±13 ±14 V Common-Mode Rejection Ratio CMRR VCM = ±13 V 100 120 dB Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 7 32 μV/V Large Signal Voltage Gain AVO RL ≥ 2 kΩ, VO = ±10 V 120 400 V/mV RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4 100 400 V/mV −40°C ≤ TA ≤ +85°C Input Offset Voltage1 VOS 85 250 μV Voltage Drift Without External Trim4 TCVOS 0.5 1.8 μV/°C Voltage Drift with External Trim3 TCVOSN RP = 20 kΩ 0.4 1.6 μV/°C Input Offset Current IOS 1.6 8.0 nA Input Offset Current Drift TCIOS 12 50 pA/°C Input Bias Current IB ±2.2 ±9.0 nA Input Bias Current Drift TCIB 18 50 pA/°C Input Voltage Range IVR ±13 ±13.5 V Common-Mode Rejection Ratio CMRR VCM = ±13 V 97 120 dB Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 10 51 μV/V Large Signal Voltage Gain AVO RL ≥ 2 kΩ, VO = ±10 V 100 400 V/mV

Rev. D | Page 5 of 16 Parameter Symbol Conditions Min Typ Max Unit OUTPUT CHARACTERISTICS TA = 25°C Output Voltage Swing VO RL ≥ 10 kΩ ±12.0 ±13.0 V RL ≥ 2 kΩ ±11.5 ±12.8 V RL ≥ 1 kΩ ±12.0 V −40°C ≤ TA ≤ +85°C Output Voltage Swing VO RL ≥ 2 kΩ ±12 ±12.6 V DYNAMIC PERFORMANCE TA = 25°C Slew Rate SR RL ≥ 2 kΩ3 0.1 0.3 V/μs Closed-Loop Bandwidth BW AVOL = 15 0.4 0.6 MHz Open-Loop Output Resistance RO VO = 0, IO = 0 60 Ω Power Consumption Pd VS = ±15 V, No load 80 150 mW VS = ±3 V, No load 4 8 mW Offset Adjustment Range RP = 20 kΩ ±4 mV 1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. 2 Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is sample tested. 3 Sample tested. 4 Guaranteed by design. 5 Guaranteed but not tested.

1 For supply voltages less than ±22 V, the absolute maximum input voltage is

equal to the supply voltage. soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance degradation or loss of functionality.

Figure 9. Input Bias Current vs. Temperature Figure 10. Input Offset Current vs. Temperature Figure 11. Low Frequency Noise Figure 12. Total Input Noise Voltage vs. Frequency Figure 13. Input Wideband Noise vs. Bandwidth,

0.1 Hz to Frequency Indicated

Figure 14. CMRR vs. Frequency

Rev. D | Page 14 of 16 ORDERING GUIDE Model Temperature Range Package Description Package Option OP07EP 0°C to 70°C 8-Lead PDIP N-8 (P-Suffix) OP07EPZ1 0°C to 70°C 8-Lead PDIP N-8 (P-Suffix) OP07CP −40°C to +85°C 8-Lead PDIP N-8 (P-Suffix) OP07CPZ1 −40°C to +85°C 8-Lead PDIP N-8 (P-Suffix) OP07CS −40°C to +85°C 8-Lead SOIC_N R-8 (S-Suffix) OP07CS-REEL −40°C to +85°C 8-Lead SOIC_N R-8 (S-Suffix) OP07CS-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 (S-Suffix) OP07CSZ1 −40°C to +85°C 8-Lead SOIC_N R-8 (S-Suffix) OP07CSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N R-8 (S-Suffix) OP07CSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N R-8 (S-Suffix) 1 Z = Pb-free part.

Rev. D | Page 15 of 16 NOTES

Rev. D | Page 16 of 16 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00316-0-7/06(D) NOTES