OP07 TGS | Alldatasheet

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AT 25°C PACKAGED DEVICES SMALL OUTLINE (D) PLASTIC DIP (P) 0°C to 70°C

150 V OP07CD

OP07 CP / DP , CDR / DDR PRECISION OPERATIONAL AMPLIFIERS Low Noise No External Components Required D OR P PACKAGE (TOP VIEW) Replaces Chopper Amplifiers at a Lower Cost Single-Chip Monolithic Fabrication Wide Input Voltage Range 0 to ± 14 V Typ Wide Supply Voltage Range ± 3 V to ± 18 V symbol OFFSET N1 IN – IN + VCC – NC – No internal connection OFFSET N1 1 OFFSET N2 VCC + OUT NC IN + 3 OUT

description

IN – 2 – OFFSET N2 These devices represent a breakthrough in operational amplifier performance. Low offset and long-term stability are achieved by means of a low-noise, chopperless, bipolar-input-transistor amplifier circuit. For most applications, external components are not required for offset nulling and frequency compensation. The true differential input, with a wide input voltage range and outstanding common-mode rejection, provides maximum flexibility and performance in high-noise environments and in noninverting applications. Low bias currents and extremely high input impedances are maintained over the entire temperature range. The OP07 is unsurpassed for low-noise, high-accuracy amplification of very low-level signals. These devices are characterized for operation from 0°C to 70°C. AVAILABLE OPTIONS TIGER ELECTRONIC CO.,LTD

OP07 CP / DP , CDR / DDR schematic OFFSET N1 1 OFFSET N2 8 IN + IN –

7 VCC +

6 OUT

4 VCC –

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC + (see Note 1) NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between V CC + and VCC – . 2. Differential voltages are at IN+ with respect to IN –. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. The output may be shorted to ground or either power supply. 5. For operation above 64 °C free-air temperature, derate the D package to 464 mW at 70°C at the rate of 5.8 mW/°C. recommended operating conditions MIN MAX UNIT Supply voltage, VCC± ± 3 ± 18 V Common-mode input voltage, VIC VCC± = ± 15 V –13 13 V Operating free-air temperature, TA 0 70 °C

electrical characteristics at specified free-air temperature, VCC ± = ± 15 V (unless otherwise noted) C C PAR AME TEST CONDITIONS† TA OP07C OP07D UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage VO = 0, R S = 50 25°C 60 150 60 150 V 0°C to 70°C 85 250 85 250 VIO Temperature coefficient of input offset VO = 0, R S = 50 0°C to 70°C 0.5 1.8 0.7 2.5 V/°C Long-term drift of input offset voltage See Note 6 0.4 0.5 V/mo Offset adjustment range RS = 20 k , See Figure 1 25°C ± 4 ± 4 mV IIO Input offset current 25°C 0.8 6 0.8 6 nA 0°C to 70°C 1.6 8 1.6 8 IIO Temperature coefficient of input offset current 0°C to 70°C 12 50 12 50 pA/°C IIB Input bias current 25°C ± 1.8 ± 7 ± 2 ± 12 nA 0°C to 70°C ± 2.2 ± 9 ± 3 ± 14 IIB Temperature coefficient of input bias current 0°C to 70°C 18 50 18 50 pA/°C VICR Common-mode input voltge range 25°C ± 13 ± 14 ± 13 ± 14 V 0°C to 70°C ± 13 ± 13.5 ± 13 ± 13.5 VOM Peak output voltage RL ε 10 k 25°C ± 12 ± 13 ± 12 ± 13 V RL ε 2 k ± 11.5 ± 12.8 ± 11.5 ± 12.8 RL ε 1 k ± 12 ± 12 RL ε 2 k 0°C to 70°C ± 11 ± 12.6 ± 11 ± 12.6 AVD Large-signal differential voltage amplification VCC ± = ± 3 V, VO = ± 0.5 V, RL ε 500 k 25°C 100 400 400 V/mV VO = ± 10 V, R L = 2 k 25°C 120 400 120 400 0°C to 70°C 100 400 100 400 B1 Unity-gain bandwidth 25°C 0.4 0.6 0.4 0.6 MHz ri Input resistance 25°C 8 33 7 31 M CMRR Common-mode rejection ratio VIC = ± 13 V, R S = 50 25°C 100 120 94 110 dB 0°C to 70°C 97 120 94 106 kSVS Supply voltage sensitivity ( VIO/ VCC) VCC ± = ± 3 V to ± 18 V, RS = 50 25°C 7 32 7 32 V/V 0°C to 70°C 10 51 10 51 PD Power dissipation VO = 0, No load 25°C 80 150 80 150 mW VCC ± = ± 3 V, VO = 0, No load 4 8 4 8

OP07 CP / DP , CDR / DDR operating characteristics, VCC ± = ± 15 V, TA = 25°C PARAMETER TEST CONDITIONS† OP07C OP07D UNIT MIN TYP MAX MIN TYP MAX Vn Equivalent input noise voltage f = 10 Hz 10.5 10.5 nV/Hzf = 100 Hz 10.2 10.3 f = 1 kHz 9.8 9.8 VN(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 0.38 0.38 V In Equivalent input noise current f = 10 Hz 0.35 0.35 pA/Hzf = 100 Hz 0.15 0.15 f = 1 kHz 0.13 0.13 IN(PP) Peak-to-peak equivalent input noise current f = 0.1 Hz to 10 Hz 15 15 pA SR Slew rate RL ε 2 k 0.3 0.3 V/ s † All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise noted. electrical characteristics, VCC ± = ± 15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS† OP07Y UNIT MIN TYP MAX VIO Input offset voltage RS = 50 60 150 V Long-term drift of input offset voltage See Note 6 0.5 V/mo Offset adjustment range RS = 20 k , See Figure 1 ± 4 mV IIO Input offset current 0.8 6 nA IIB Input bias current ± 2 ± 12 nA VICR Common-mode input voltage range ± 13 ± 14 V VOM Peak output voltage RL δ 10 k ± 12 ± 13 V RL δ 2 k ± 11.5 ± 12.8 RL δ 1 k ± 12 AVD Large-signal differential voltage amplification VCC ± = ± 3 V, VO = ± 0.5 V, R L δ 500 k 400 VO = ± 10 V, R L = 2 k 120 400 B1 Unity-gain bandwidth 0.4 0.6 MHz ri Input resistance 7 31 M CMRR Common-mode input resistance VIC = ± 13 V, R S = 50 94 110 dB kSVS Supply-voltage rejection ratio ( VCC/ VIO) VCC ± = ± 3 V to ± 18 V, R S = 50 7 32 V/V PD Power dissipation VO = 0, No load 80 150 M VCC ± = ± 3 V, VO = 0, No load 4 8

OP07 CP / DP , CDR / DDR operating characteristics, VCC ± = ± 15 V, TA = 25°C PARAMETER TEST CONDITIONS† OP07Y UNIT MIN TYP MAX Vn Equivalent input noise voltage f = 10 Hz 10.5 nV/Hzf = 1 kHz 10.3 f = 0.1 Hz to 10 Hz 9.8 VN(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 0.38 V In Equivalent input noise current f = 10 Hz 0.35 pA/Hzf = 100 Hz 0.15 f = 1 kHz 0.13 IN(PP) Peak-to-peak equivalent input noise current f = 0.1 Hz to 10 Hz 15 pA SR Slew rate RL = 2 k 0.3 V/ s † All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise noted.

APPLICATION INFORMATION

IN – Figure 1. Input Offset Voltage Null Circuit