OP07

OP07x Precision Operational Amplifiers datasheet (Rev. H)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLOS099,H]
• PDF pages: 22

Technical content

OP07x Precision Operational Amplifiers

1 Features

• Low noise
• No external components required
• Replace chopper amplifiers at a lower cost
• Wide input-voltage range:

0 V to ±14 V (typ, ±15-V supply)

• Wide supply-voltage range: ±3 V to ±18 V

2 Applications

• Analog input module
• Battery test
• Lab and field instrumentation
• Temperature transmitter
• Merchant network & server PSU

3 Description

The OP07C and OP07D (OP07x) devices offer low offset and long-term stability by means of a low- noise, chopperless, bipolar ‑input‑transistor amplifier circuit. For most applications, external components are not required for offset nulling and frequency compensation. The true differential input, with a wide input-voltage range and outstanding common- mode rejection, provides maximum flexibility and performance in high-noise environments and in noninverting applications. Low bias currents and extremely high input impedances are maintained over the entire temperature range. For improved performance and wider temperature range, see the next generation OPA207 with low power, and OPA202 with heavy capacitive load drive capability.

Package Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM) OP07C, OP07D D (SOIC, 8) 4.90 mm × 3.91 mm P (PDIP, 8) 9.81 mm × 6.35 mm PS (SO, 8) 6.20 mm × 5.30 mm (1) For all available packages and the OP07, see the orderable addendum at the end of the data sheet. OUT OFFSET N2 IN− IN+ OFFSET N1 1 Simplified Schematic OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (November 2014) to Revision H (July 2022) Page

• Changed supply voltage abbreviation from VCC+ and VCC– to VS in Absolute Maximum Ratings and
• Changed note 5 in Absolute Maximum Ratings to include a note that fast-ramping shorts to the positive
• Changed Electrostatic discharge Human-body model and Charged-device model from 1000 V to ±1000 V.... 4
• Changed parameter name from supply-voltage sensitivity to power supply rejection ratio in Electrical
• Changed parameter name from input offset voltage to Input voltage noise density in Electrical Characteristics
• Changed parameter name from large-signal differential voltage gain to open-loop voltage gain in Electrical Changes from Revision F (January 2014) to Revision G (November 2014) Page
• Added Applications, Device Information table, Pin Functions table, Handling Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Changes from Revision E (May 2004) to Revision F (January 2014) Page OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 www.ti.com

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5 Pin Configuration and Functions

IN– – IN+ + Not to scale Figure 5-1. D Package, 8-Pin SOIC, P Package, 8-Pin PDIP, and PS Package, 8-Pin SO (Top View) Table 5-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. IN+ 3 Input Noninverting input IN– 2 Input Inverting input NC 5 — Do not connect OFFSET N1 1 Input External input offset voltage adjustment OFFSET N2 8 Input External input offset voltage adjustment OUT 6 Output Output V+ 7 — Positive supply V– 4 — Negative supply www.ti.com OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: OP07 OP07C OP07D

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VS Supply voltage(2) Single supply 44 V Dual supply ±22 Input voltage Differential(3) ±30 V Single-ended(4) ±22 Output short-circuit(5) Continous TJ Operating junction temperature –55 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, unless otherwise noted, are with respect to the midpoint between V+ and V−. (3) Differential voltages are at IN+ with respect to IN−. (4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. (5) The output can be shorted to ground or to the negative power supply. Fast ramping shorts to the positive supply can cause permanent damage and eventual destruction.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VS Supply voltage Single supply 6 36 V Dual supply ±3 ±18 VCM Common-mode input voltage VS = ±15 V –13 13 V TA Operating ambient temperature 0 70 °C

6.4 Thermal Information

THERMAL METRIC(1) OP07x UNITD (SOIC) P (PDIP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 127.6 85 °C/W RθJC(top) Junction-to-case (top) thermal resistance 67.1 68.6 °C/W RθJB Junction-to-board thermal resistance 71.4 55..6 °C/W ψJT Junction-to-top characterization parameter 18.7 38.3 °C/W ψJB Junction-to-board characterization parameter 70.6 55.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 www.ti.com

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6.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 2 kΩ connected to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)(1). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage OP07C ±60 μV TA = 0°C to 70°C ±85 OP07D ±150 TA = 0°C to 70°C ±250 dVOS/dT Input offset voltage drift TA = 0°C to 70°C OP07C ±0.5 μV/°C OP07D ±2.5 Long-term drift of input offset voltage(2) ±0.4 µV/mo Offset adjustment range Rs = 20 kΩ, see Section 8.1 ±4 mV PSRR Power supply rejection ratio VS = ±3 V to ±18 V 7 32 μV/V TA = 0°C to 70°C 10 51 INPUT BIAS CURRENT IB Input bias current OP07C ±1.8 nA TA = 0°C to 70°C ±2.2 OP07D ±12 TA = 0°C to 70°C ±14 Input bias current drift OP07C ±18 pA/°C OP07D ±50 IOS Input offset current OP07C ±0.8 nA TA = 0°C to 70°C ±1.6 OP07D TA = 0°C to 70°C ±8 Input offset current drift OP07C 12 pA/°C OP07D ±50 NOISE Input voltage noise f = 0.1 Hz to 10 Hz 0.38 μVPP eN Input voltage noise density f = 10 Hz 10.5 nV/√Hzf = 100 Hz 10.2 f = 1 kHz 9.8 Input current noise f = 0.1 Hz to 10 Hz 15 pApp iN Input current noise density f = 10 Hz 0.35 pA/√Hzf = 100 Hz 0.15 f = 1 kHz 0.13 INPUT VOLTAGE RANGE VCM Common-mode voltage ±13 ±14 V TA = 0°C to 70°C ±13 ±13.5 CMRR Common-mode rejection ratio OP07C VCM = ±13 V 100 120 dB TA = 0°C to 70°C 97 120 OP07D VCM = ±13 V 94 110 TA = 0°C to 70°C 94 106 INPUT CAPACITANCE rI Input resistance 7 33 MΩ OPEN-LOOP GAIN AOL Open-loop voltage gain 1.4 V < VO < 11.4 V, RL = 500 kΩ OP07C 100 400 V/mV OP07D 400 VO = ±10 V 120 400 TA = –40°C to +125°C 100 400 www.ti.com OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: OP07 OP07C OP07D

6.5 Electrical Characteristics (continued)

at TA = 25°C, VS = ±15 V, RL = 2 kΩ connected to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)(1). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE Unity gain bandwidth 0.4 0.6 MHz SR Slew rate VS = 5 V, RL = 2 kΩ 0.3 V/μs OUTPUT Voltage output swing ±11.5 ±12.8 V TA = 0°C to 70°C ±11 ±12.6 RL = 10 kΩ ±12 ±13 RL = 1 kΩ ±12 POWER SUPPLY PD Power dissipation No load 80 150 mW VS = ±3 V, no load 4 8 (1) The specifications listed in the Electrical Characteristics apply to OP07C and OP07D. (2) Because long-term drift cannot be measured on the individual devices before shipment, this specification is not intended to be a warranty. This specification is an engineering estimate of the averaged trend line of drift versus time over extended periods after the first 30 days of operation.

6.6 Typical Characteristics

Temperature (ºC) Input Offset Voltage (µV) –50 0 50 100 150 –50 100 150 200 Low Mean High Figure 6-1. Input-Offset Voltage vs Temperature OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 www.ti.com

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7 Detailed Description

7.1 Overview

These devices offer low offset and long-term stability by means of a low-noise, chopperless, bipolar-input- transistor amplifier circuit. For most applications, external components are not required for offset nulling and frequency compensation. The true differential input, with a wide input-voltage range and outstanding common- mode rejection, provides maximum flexibility and performance in high-noise environments and in noninverting applications. Low bias currents and extremely high input impedances are maintained over the entire temperature range. These devices are characterized for operation from 0°C to 70°C.

7.2 Functional Block Diagram

V OFFSET N1 OFFSET N2 IN+ IN OUT

7.3 Feature Description

7.3.1 Offset-Voltage Null Capability

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current- gain betas ( β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for these mismatches by external circuitry. See Section 8 for more details on design techniques.

7.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change the output when there is a change on the input. The OP07x have a 0.3-V/μs slew rate.

7.4 Device Functional Modes

The OP07x are powered on when the supply is connected. The devices can be operated as single-supply operational amplifiers or dual-supply amplifiers, depending on the application. www.ti.com OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: OP07 OP07C OP07D

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current- gain betas ( β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for these mismatches with external circuitry. Figure 8-1 shows how these input mismatches can be adjusted by putting resistors or a potentiometer between the null pins. Use a potentiometer to fine tune the circuit during testing or for applications that require precision offset control. For more information about designing using the input-offset pins, see the Nulling Input Offset Voltage of Operational Amplifiers application report. V OUT OFFSET OFFSET N1 IN+ IN 7 6 20 kΩ Figure 8-1. Input Offset-Voltage Null Circuit

8.2 Typical Application

The voltage follower configuration of the operational amplifier is used for applications where a weak signal is used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The inputs of an operational amplifier have a very high resistance that puts a negligible current load on the voltage source. The output resistance of the operational amplifier is almost negligible, so the amplifier can provide as much current as necessary to the output load. 12 V VIN VOUT 10 k Figure 8-2. Voltage Follower Schematic

8.2.1 Design Requirements

• Output range of 2 V to 11 V
• Input range of 2 V to 11 V OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 www.ti.com

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8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Swing

The output voltage of an operational amplifier is limited by the internal circuitry to some level less than the supply rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output voltage requirements.

8.2.2.2 Supply and Input Voltage

For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to 11 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail, rather than ground, allows the amplifier to maintain linearity for inputs below 2 V.

8.2.3 Application Curves

VOUT (V) VIN (V) C001 Figure 8-3. Output Voltage vs Input Voltage ±0.3 ±0.2 ±0.1 0.0 0.1 0.2 0.3 0.4 0 2 4 6 8 10 12 IIO (mA) VIN (V) C002 Figure 8-4. Current Drawn by the Input of the Voltage Follower (IIO) vs Input Voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 2 4 6 8 10 12 ICC (mA) VIN (V) C003 Figure 8-5. Current Drawn from Supply (ICC) vs Input Voltage

8.3 Power Supply Recommendations

The OP07x operate from ±3 V to ±18 V supplies; many specifications apply from 0°C to 70°C. CAUTION Supply voltages larger than ±22 V can permanently damage the device. See also Section 6.1. Place 0.1- μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more details on bypass capacitor placement, see Section 8.4.1. www.ti.com OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: OP07 OP07C OP07D

8.4 Layout

8.4.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. On multilayer PCBs, one or more layers are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as opposed to in parallel, with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Section 8.4.2.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

8.4.2 Layout Example

Figure 8-6. Operational Amplifier Schematic for Noninverting Configuration OFFSET N1 V+IN− IN+ OFFSET N2 OUT NC RG RIN RF GND VIN VS-GND VS+ GND Run the input traces as far away from the supply lines as possible Only needed for dual-supply operation Use low-ESR, ceramic bypass capacitor (or GND for single supply) Ground (GND) plane on another layer VOUT Place components close to device and to each other to reduce parasitic errors Figure 8-7. Operational Amplifier Board Layout for Noninverting Configuration OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 www.ti.com

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9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. www.ti.com OP07, OP07C, OP07D SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: OP07 OP07C OP07D

www.ti.com 23-Aug-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) OP-07DP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 OP-07DP OP-07DP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 OP-07DP OP-07DPS Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D OP-07DPS.A Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D OP-07DPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D OP-07DPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D OP07-W Active Production WAFERSALE (YS) | 0 3603 | null - Call TI Call TI - OP07CD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 OP07C OP07CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C OP07CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C OP07CDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C OP07CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 OP07CP OP07CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 OP07CP OP07CP.B Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 OP07CP OP07DD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D OP07DD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D OP07DDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D OP07DDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D OP07DP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 OP07DP OP07DP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 OP07DP OP07DPE4 Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 OP07DP (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 23-Aug-2026 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OP-07DPSR SO PS 8 2000 353.0 353.0 32.0 OP07CDR SOIC D 8 2500 340.5 338.1 20.6 OP07CDR SOIC D 8 2500 353.0 353.0 32.0 OP07CDR SOIC D 8 2500 353.0 353.0 32.0 OP07DDR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) OP-07DP P PDIP 8 50 506 13.97 11230 4.32 OP-07DP.A P PDIP 8 50 506 13.97 11230 4.32 OP-07DPS PS SOP 8 80 530 10.5 4000 4.1 OP-07DPS.A PS SOP 8 80 530 10.5 4000 4.1 OP07CP P PDIP 8 50 506 13.97 11230 4.32 OP07CP.A P PDIP 8 50 506 13.97 11230 4.32 OP07CP.B P PDIP 8 50 506 13.97 11230 4.32 OP07DD D SOIC 8 75 507 8 3940 4.32 OP07DD.A D SOIC 8 75 507 8 3940 4.32 OP07DP P PDIP 8 50 506 13.97 11230 4.32 OP07DP.A P PDIP 8 50 506 13.97 11230 4.32 OP07DPE4 P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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