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Femtoclocks™ Crystal-to-3.3V LVPECL Clock Generator NV021 Data Sheet ©2016 Integrated Device Technology, Inc Revision B January 26, 20161 GENERAL DESCRIPTION The NV021 is a Fibre Channel Clock Generator and a member of the family of high performance devices from IDT. The NV021 can synthesize 98.304MHz, 100MHz, and 106.25MHz from a 24.576MHz, 25MHz, and 26.5625MHz crystals respectively. The NV021 is packaged in a small 8-pin SOIC, making it ideal for use in systems with limited board space.

FEATURES

  • 1 differential 3.3V LVPECL output
  • Crystal frequency range: 23.33MHz - 28.33MHz
  • Output frequencies: 98.304MHz, 100MHz. 106.25MHz
  • VCO range: 560MHz - 680MHz
  • Low RMS phase jitter
  • 3.3V operating supply
  • Available in RoHS/Lead-Free compliant package
  • -30°C to 85°C ambient operating temperature FREQUENCY TABLE NV021 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View BLOCK DIAGRAM P IN ASSIGNMENT VCCA VEE XTAL_OUT XTAL_IN VCC nQ0 nc Crystal (MHz) Output Frequency (MHz) 24.576 98.304 25 100 26.5625 106.25

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 1V CCA Power Analog supply pin. 2V EE Power Negative supply pin. 6, 7 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. 8V CC Power Core supply pin.

NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -30°C TO 85°C TABLE 4. CRYSTAL CHARACTERISTICS conditions for extended periods may affect product reliability. NOTE 1: Please refer to the Phase Noise Plot.

©2016 Integrated Device Technology, Inc Revision B January 26, 20164 TYPICAL PHASE NOISE AT 100MHZ OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M dBc Hz NOISE POWER Filter Raw Phase Noise Data Phase Noise Result by adding a Filter to raw data 100MHz RMS Phase Noise Jitter 637kHz to 10MHz = <2ps (typical)

©2016 Integrated Device Technology, Inc Revision B January 26, 20165 PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER

©2016 Integrated Device Technology, Inc Revision B January 26, 20167 TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. INPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated.

©2016 Integrated Device Technology, Inc Revision B January 26, 20168 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the NV021. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the NV021 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 90mA = 311.85mW
  • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 311.85mW + 30mW = 341.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). TABLE 6A. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6B. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION

©2016 Integrated Device Technology, Inc Revision B January 26, 201610 RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for NV021 is: 1839 TABLE 7A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θJA by Velocity (Linear Feet per Minute) TABLE 7B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

©2016 Integrated Device Technology, Inc Revision B January 26, 201611 PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 8A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-012 SYMBOL Millimeters MINIMUN MAXIMUM A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-153 SYMBOL Millimeters Minimum Maximum A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10

TABLE 8. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision B January 26, 201613 REVISION HISTORY SHEET Rev Table Page Description of Change Date BT 4 Features section and Frequency Table - added 98.304MHz and 106.25MHz output frequencies, and added 24.576MHz and 26.5625MHz crystal frequencies. Crystal Characteristics - added Drive Level. AC Characteristics - added 98.304MHz and 106.25MHz to RMS Phase Jitter. Added Recommendations for Unused Input and Output Pins. 7/26/05 B Updated datasheet format to IDT. Removed TSSOP package information. Table 8, Ordering Information - removed leaded and TSSOP devices. 4/2/14 B T8 Removed reference to leaded package. Ordering Information - removed quantity from tape and reel. Deleted LF note below the table. Updated header and footer. 1/26/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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