NPS1000 NEXPERIA | Alldatasheet
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0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch Rev. 1 — 29 March 2024 Product data sheet 1. General description NPS1000 is a low voltage, single-channel load switch with a low RDS,ON (11 mΩ) to minimize IR drop and power loss. It supports up to 0.6 A RMS current and a peak current of 1.5 A. The switch is controlled by an EN input which is compatible with 1.2 V logic levels. When the load switch is enabled, the internal switch charges the output capacitor with a controlled inrush current. When the switch is disabled, an 8 Ω on-chip resistor discharges the output to ground and keeps it from floating. The IC is powered from a separate BIAS pin which is rated for 2.3 V to 5.0 V operation. NPS1000 has an over-temperature protection that latches the device OFF when the internal junction temperature is above the set point (Tth(OTLO)). At this time, the internal switch is turned off and the output discharge element turns on to discharge the output capacitor. The load switch can be enabled again by toggling the EN pin. NPS1000 is available in an ultra-small, space saving, wafer level chip-scale package; 8 bumps; 1.42 mm × 0.72 mm × 0.465 mm body and is characterized for operation over junction temperature range of –40 °C to 105 °C. NPS1000 Control block GND COUT ROUT OUTIN VIN CIN BIAS EN VBIAS CBIAS aaa-038741 2. Features and benefits
- 0.5 V – 1.0 V operation voltage
- Low RDS,ON: 11 mΩ typical at 25 °C, 16 mΩ (maximum) at 85 °C
- Enable logic supports 1.2 V logic levels
- 0.6 A RMS and 1.5 A peak current capability
- Controlled start-up
- <200 µs from enable to full enhancement of power FET
- Output short tolerant
- When supplied by a 4.5 A current limited power supply
- Over-temperature shutdown and input UVLO protection
- 8 Ω discharge while disabled
- Small package footprint
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C2a exceeds 500 V
- Specified from TJ = -40 °C to +105 °C 3. Applications
- Mobile phones
- Wearables
Table 1. Ordering information Table 2. Marking
Table 3. Pin description IN B1, C1 I Device input. Apply a 0.5 V to 1.0 V voltage source. Bypass with a low ESR capacitor to GND. OUT B2, C2 O Device output. Connect to the load. Bypass with a low ESR capacitor to GND. BIAS A1 I Power supply for the IC. Bypass with a low ESR capacitor to GND.
designed for very low inputs of 0.5 V to 1.0 V and the logic input is designed to compatible to 1.2 V logic levels. controlled manner to control the inrush current. the OTP threshold. The power FET can be turned back on by toggling the EN input. at BIAS exceeds UVLOrise, the QOD FET is turned ON to pull OUT to ground and the pass-FET is turned off. resistance. Pulling EN low will turn off the pass-FET and turn on the QOD FET to discharge the output capacitor. turns off the pass-FET and turns on the QOD FET. It remains latched in the off-state till the EN pin is toggled externally. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1] TJ(max) internally limited by OTP threshold. Table 5. ESD ratings
- Recommended operating conditions
Table 6. Recommended operating conditions Electrical Characteristics in Section 14. Table 7. Recommended components Table 8. Thermal information 1 oz Cu for inner layers with no vias. Pads are connected to 0.25 mm copper traces.
- Electrical characteristics
Table 9. Electrical characteristics TJ = -40 °C to +105 °C unless otherwise specified. VIN=1.0 V, VBIAS= 3.4 V, unless otherwise specified. [1] Typical numbers are mean values at 25 °C. [2] Obtained through simulation and characterization, but not tested in production.
Table 10. Dynamic characteristics VIN = 1.0 V, VBIAS = 3.4 V, VEN = 0 V/1.2 V, COUT = 60 μF, ROUT= open, unless otherwise specified. [1] Typical values are measured at TJ = 25 °C. [2] Design guidance for customer.
0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch NPS1000 Control block GND COUT ROUT OUTIN VIN CIN BIAS EN VBIAS CBIAS aaa-038741 (1) Rise and fall times of the control signal (VEN) are 100 ns (10% - 90% measurement). Fig. 5. Test circuit 15.2. Typical characteristics Unless otherwise noted, VIN = 1.0 V, CIN = 1.0 μF, VBIAS = 3.4 V, CBIAS = 0.1 μF, COUT = 66 μF, ROUT = open aaa-038088 0.5 1.5 2.5 VBIAS (V) ISH,BIASISH,BIAS (µA)(µA) (1)(1) (2)(2) (3)(3) (4)(4) VIN = 1 V; VEN = 0 V (1) TJ = -40 °C (2) TJ = 25 °C (3) TJ = 85 °C (4) TJ = 105 °C Fig. 6. Bias shutdown current (ISH,BIAS) versus bias voltage aaa-038089 VBIAS (V) IQ,BIASIQ,BIAS (µA)(µA) (1)(1) (2)(2) (3)(3) (4)(4) VIN = 1 V; VEN = 1.2 V (1) TJ = -40 °C (2) TJ = 25 °C (3) TJ = 85 °C (4) TJ = 105 °C Fig. 7. BIAS quiescent current (IQ,BIAS) versus bias voltage NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 8 / 18
0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch aaa-038090 0.2 0.4 0.6 0.8 VIN (V) IIN,OFFIIN,OFF (µA)(µA) (1)(1) (2)(2) (3)(3) VBIAS = 3.4 V; VEN = 0 V (1) TJ = -40 °C (2) TJ = 25 °C (3) TJ = 85 °C Fig. 8. Input leakage current (IIN,OFF) versus input voltage with EN = LOW aaa-038091 0.4 0.8 1.2 1.6 VIN (V) IIN,OFFIIN,OFF (µA)(µA) (1)(1) (2)(2) (3)(3) VBIAS = 3.4 V; VEN = 1.2 V (1) TJ = -40 °C (2) TJ = 25 °C (3) TJ = 85 °C Fig. 9. Input quiescent current (IIN,Q) versus input voltage with EN = HIGH aaa-038092 -40 -15 10 35 60 85 TJ (°C) RDS,ONRDS,ON (mΩ)(mΩ) VIN = 1.0 V; VBIAS = 3.4 V Fig. 10. RDS,ON resistance versus junction temperature aaa-038093 -40 -15 10 35 60 85 110 TJ (°C) RQODRQOD (mΩ)(mΩ) VOUT = 1.0 V; VBIAS = 3.4 V Fig. 11. RQOD resistance versus junction temperature NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 9 / 18
0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch aaa-038094 -40 -15 10 35 60 85 110 130 135 140 145 150 155 160 TJ (°C) TENHTENH (µs)(µs) VIN = 1.0 V; VBIAS = 3.4 V Fig. 12. Enhancement time (TENH) versus junction temperature 15.3. Typical waveforms aaa-038606 VIN VOUT VEN IIN Time scale: 50 µs/div Fig. 13. Output voltage ramp and inrush current aaa-038607 VIN VOUT VEN IIN Time scale: 200 µs/div Fig. 14. Output discharge using QOD FET aaa-038608 VOUT VEN Time scale: 50 µs/div Fig. 15. Turn-on delay aaa-038609 VOUT VEN Time scale: 50 µs/div Fig. 16. Turn-off delay NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 10 / 18
0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch aaa-038610 VIN VOUT VEN IIN Time scale: 500 µs/div Fig. 17. EN toggling at 500 μs ON / 500 μs OFF aaa-038611 VIN VOUT VEN IIN Time scale: 500 µs/div Fig. 18. EN toggling at 500 μs ON / 200 μs OFF aaa-038612 VIN VIN- VOUT IIN Time scale: 1 ms/div Fig. 19. Load step response from 0 A to 1 A aaa-038613 VIN VIN- VOUT IIN Time scale: 1 ms/div Fig. 20. Load step response from 0 A to 1.5 A aaa-038614 VIN VIN- VOUT IIN Time scale: 50 µs/div Fig. 21. Load step response rising edge from 0 A to 1 A aaa-038615 VIN VIN- VOUT IIN Time scale: 50 µs/div Fig. 22. Load step response rising edge from 0 A to 1.5 A NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 11 / 18
0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch aaa-038616 VIN VIN- VOUT IIN Time scale: 50 µs/div Fig. 23. Load step response falling edge from 1 A to 0 A aaa-038617 VIN VIN- VOUT IIN Time scale: 50 µs/div Fig. 24. Load step response falling edge from 1.5 A to 0 A NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 12 / 18
0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch 16. Application information 16.1. Typical application diagram NPS1000 Control block Step down regulator MCU SoC or module EN BIAS IN CIN COUT CBIAS GND aaa-039146 Fig. 25. Application diagram 16.2. Inrush current The NPS1000 does not directly control the inrush current at startup. Instead, it controls the output slew rate by controlling the slew rate of the gate voltage for the power FET. The pass device acts as a source follower during startup and the output slew rate follows the slew rate of the pass-FET’s gate voltage. The inrush current at any given condition is thus a function of the input voltage and the load capacitance. The following graphs (Fig. 26 and Fig. 27) show how the peak inrush current varies with the operating conditions. aaa-038116 0 20 40 60 80 100 0.25 0.5 0.75 1.25 Load capacitance (μF) IINRUSHIINRUSH (A)(A) (1)(1) (2)(2) VBIAS = 3.4 V (1) VIN = 0.5 V (2) VIN = 1.0 V Fig. 26. Peak inrush current (IINRUSH) versus load capacitance aaa-038117 0 20 40 60 80 100 Load capacitance (μF) SROUTSROUT (V/ms)(V/ms) (1)(1) (2)(2) VBIAS = 3.4 V (1) VIN = 0.5 V (2) VIN = 1.0 V Fig. 27. Output slew rate versus load capacitance NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 13 / 18
0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch 17. Design and assembly recommendations 17.1. PCB design guidelines For best performance, all traces must be kept as short as possible. The input and output capacitors must be placed close to the device to minimize effects of parasitic trace inductances on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects. A minimum 1 μF capacitor is recommended from IN to GND as well as OUT to GND, and these should be placed as close to the IC as possible as shown in Section 17.2. 17.2. PCB layout example A typical layout example if shown in Fig. 28. At least a 2-layer PCB is recommended for best layout practices. The top layer is used for routing the signals as shown in the figure (gray areas are copper planes on the top layer). The bottom layer (or second layer in a multi-layer PCB) is used for a copper plane connected to GND (yellow area). Multiple vias are recommended (number depends on manufacturing guidelines). COUTCIN CBIASCBIAS VIA to GND plane VIA to GND plane VIA to GND plane BIAS IN IN EN GND OUT OUT GND aaa-038749 Fig. 28. PCB layout example NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 14 / 18
0.5 V to 1.0 V, 1.5 A peak, 11 mΩ, load switch 18. Package outline ReferencesOutline version European projection Issue date IEC JEDEC JEITA WLCSP8_SOT8068 wlcsp8_sot8068_po 24-01-22 Unit mm max nom min 0.465 0.245 0.015 0.03 0.06 A Dimensions (mm are the original dimensions) 0.290 b D E e v u y 0.05 1.42 BSC0.145 0.2050.240 0 2 mm scale WLCSP8: wafer level chip-scale package; 8 bumps; 1.42 × 0.72 × 0.465 mm body WLCSP8_SOT8068 1.05 BSC Dh 0.72 BSC 0.35 BSC bump A1 index area D E B A M Cy1 C Cu Cy seating plane (8×) A detail M Back side coating e D C B A 1 2 Dh e Ø b (8×) AC BØ v Fig. 29. Package outline WLCSP8_SOT8068 (WLCSP8) NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 15 / 18
Table 11. Abbreviations Table 12. Revision history
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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NPS1000 Submit document feedback All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved Product data sheet Rev. 1 — 29 March 2024 17 / 18