Logic IC

NPL0013A

Texas Instruments

4-A, 6-A, 2.5-kVRMS Isolated Dual-Channel Gate Driver in LGA

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UCC21225A TI1 | Alldatasheet

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Disable, UVLO and Deadtime 4,7 GND INB DT DIS INA VCCI Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC21225A SLUSCV6 – APRIL 2017 UCC21225A4-A,6-A,2.5-kVRMSIsolatedDual-ChannelGateDriverinLGA

1 Features

1• Universal: Dual Low-Side, Dual High-Side or Half- Bridge Driver

5 x 5 mm, Space-Saving LGA-13 Package
Operating Temperature Range –40°C to +125°C
Switching Parameters: – 19-ns Typical Propagation Delay – 10-ns Minimum Pulse Width – 5-ns Maximum Delay Matching – 6-ns Maximum Pulse-Width Distortion
Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
Surge Immunity up to 4600-V
4-A Peak Source, 6-A Peak Sink Output
TTL and CMOS Compatible Inputs
3-V to 18-V Input VCCI Range to Interface with Both Digital and Analog Controllers
Up to 25-V VDD Output Drive Supply with 5-V UVLO
Programmable Dead Time
Rejects Input Pulses and Noise Transients Shorter than 5-ns
Fast Disable for Power Sequencing
Safety-Related and Regulatory Approvals: – 3535-VPK Isolation per DIN V VDE V 0884-10 and DIN EN 61010-1 (Planned) – 2500-VRMS Isolation for 1 Minute per UL 1577 (Planned) – CSA Component Acceptance Notice 5A, IEC 60950-1 IEC 61010-1 End Equipment Standards (Planned) – CQC Certification per GB4943.1-2011 (Planned)

2 Applications

Server, Telecom, IT and Industrial Infrastructures
Isolated Converters in Offline AC-to-DC Power Supplies
Motor Drive and DC-to-AC Solar Inverters
LED Lighting
HEV and BEV Battery Chargers

3 Description

The UCC21225A is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current in a space-saving 5 mm x 5 mm LGA-13 package. It is designed to drive power MOSFETs, IGBTs, and SiC MOSFETs up to 5-MHz with best-in-class propagation delay and pulse-width distortion, in applications requiring the highest power density. The input side is isolated from the two output drivers by a 2.5-kVRMS reinforced isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 700-VDC. This driver can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). A disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded. As a fail-safe measure, primary-side logic failures force both outputs low. The device accepts VDD supply voltages up to 25-V. A wide input VCCI range from 3-V to 18-V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection. With all these advanced features, the UCC21225A enables high power density, high efficiency, and robustness in a wide variety of power applications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) UCC21225ANPL NPL LGA (13) 5 mm x 5 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram

6.11 Insulation Characteristics and Thermal Derating

13 Mechanical, Packaging, and Orderable

4 Revision History

April 2017 * Initial release.

9 OUTB

10 VDDB

11 VSSA

12 OUTA

13 VDDA

5 Pin Configuration and Functions

I/O(1) DESCRIPTION NAME NO. DISABLE 5 I Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. DT 6 I Programmable dead time function. Tying DT to VCCI allows the outputs to overlap. Leaving DT open sets the dead time to <15 ns. Placing a 500-Ω to 500-kΩ resistor (RDT) between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is recommended to parallel a ceramic capacitor , 2.2 nF or above, close to DT pin to achieve better noise immunity. GND 1 P Primary-side ground reference. All signals in the primary side are referenced to this ground. INA 2 I Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. INB 3 I Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. OUTA 12 O Output of driver A. Connect to the gate of the A channel FET or IGBT. OUTB 9 O Output of driver B. Connect to the gate of the B channel FET or IGBT. VCCI 4 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible. VCCI 7 P Primary side supply voltage. This pin is internally shorted to PIN 4. VDDA 13 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible. VDDB 10 P Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor located as close to the device as possible. VSSA 11 P Ground for secondary-side driver A. Ground reference for secondary side A channel. VSSB 8 P Ground for secondary-side driver B. Ground reference for secondary side B channel.

SLUSCV6 – APRIL 2017 www.ti.com Product Folder Links: UCC21225A Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) To maintain the recommended operating conditions for TJ, see the Thermal Information.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input bias pin supply voltage VCCI to GND –0.3 20 V Driver bias supply VDDA-VSSA, VDDB-VSSB –0.3 30 V Output signal voltage OUTA to VSSA, OUTB to VSSB –0.3 VVDDA+0.3, VVDDB+0.3 V OUTA to VSSA, OUTB to VSSB, Transient for 200 ns –2 VVDDA+0.3, VVDDB+0.3 V Input signal voltage INA, INB, DIS, DT to GND –0.3 VVCCI+0.3 V INA, INB Transient for 50ns –5 VVCCI+0.3 V Channel to channel voltage VSSA-VSSB, VSSB-VSSA 700 V Junction temperature, TJ (2) –40 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1500

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCCI VCCI Input supply voltage 3 18 V VDDA, VDDB Driver output bias supply 6.5 25 V TA Ambient Temperature –40 125 °C TJ Junction Temperature –40 130 °C

www.ti.com SLUSCV6 – APRIL 2017 Product Folder Links: UCC21225A Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Standard JESD51-9 Area Array SMT Test Board (2s2p) in still air, with 12-mil dia. 1-oz copper vias connecting VSSA and VSSB to the plane immediately below (three vias for VSSA, three vias for VSSB).

6.4 Thermal Information

THERMAL METRIC(1) UCC21225A UNIT LGA (13)(2) RθJA Junction-to-ambient thermal resistance 98.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.8 RθJB Junction-to-board thermal resistance 78.9 ψJT Junction-to-top characterization parameter 26.2 ψJB Junction-to-board characterization parameter 76.8

6.5 Power Ratings

PD Power dissipation by UCC21225A VCCI = 18 V, VDDA/B = 12 V, INA/B = 3.3 V,

4.15 MHz 50% duty cycle square wave 1-nF

1.25 W PDI Power dissipation by transmitter side of UCC21225A 0.05 PDA, PDB Power dissipation by each driver side of UCC21225A 0.60

SLUSCV6 – APRIL 2017 www.ti.com Product Folder Links: UCC21225A Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. (2) Package dimension tolerance ± 0.05mm. (3) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (4) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (5) Apparent charge is electrical discharge caused by a partial discharge (pd). (6) All pins on each side of the barrier tied together creating a two-terminal device.

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT CLR External clearance(1)(2) Shortest pin-to-pin distance through air 3.5 mm CPG External creepage(1)(2) Shortest pin-to-pin distance across the package surface 3.5 mm DTI Distance through the insulation Minimum internal gap (internal clearance) >21 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664-1 I Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150 VRMS I-IV Rated mains voltage ≤ 300 VRMS I-III DIN V VDE 0884-10 (VDE V 0884-10): 2006-2012(3) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 792 VPK VIOWM Maximum isolation working voltage AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test, (See Figure 1)

560 VRMS

792 VDC

Maximum transient isolation voltage VTEST = VIOTM t = 60 sec (qualification) t = 1 sec (100% production)

3535 VPK

voltage(4) Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM (qualification) 3535 VPK qpd Apparent charge(5) Method a, After Input/Output safety test subgroup 2/3. Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 X VIORM, tm = 10s pC Method a, After environmental tests subgroup 1. Vini = VIOTM, tini = 60s; Vpd(m) = 1.3 X VIORM, tm = 10s Method b1; At routine test (100% production) and preconditioning (type test) Vini = VIOTM; tini = 1s; Vpd(m) = 1.5 X VIORM, tm = 1s CIO Barrier capacitance, input to output(6) VIO = 0.4 sin (2πft), f =1 MHz 1.2 pF RIO Isolation resistance, input to output(6) VIO = 500 V at TA = 25°C > 1012 ΩVIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011 VIO = 500 V at TS =150°C > 109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage VTEST = VISO = 2500 VRMS, t = 60 sec. (qualification), VTEST = 1.2 × VISO = 3000VRMS, t = 1 sec (100% production) 2500 VRMS

6.7 Safety-Related Certifications

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411- 1):2011-07 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1 Certified according to UL 1577 Component Recognition Program Certified according to GB4943.1-2011 Basic Insulation Maximum Transient Overvoltage, 3535 VPK; Maximum Repetitive Peak Voltage, 792 VPK; Maximum Surge Isolation Voltage, Basic insulation and Reinforced insulation per CSA 60950-1- 07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2; Basic insulation per CSA 61010-1-12 and IEC 61010-1 3rd Ed. Single protection, 2500 VRMS Basic Insulation, Altitude ≤ 5000 m, Tropical Climate Agency Qualification Planned Agency Qualification Planned Agency Qualification Planned Agency Qualification Planned

6.8 Safety-Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS SIDE MIN TYP MAX UNIT IS Safety output supply current RθJA = 98.0ºC/W, VDDA/B = 12 V, TA = 25°C, TJ = 150°C See Figure 2 DRIVER A, DRIVER B 50 mA RθJA = 98.0ºC/W, VDDA/B = 25 V, TA = 25°C, TJ = 150°C DRIVER A, DRIVER B 24 mA PS Safety supply power RθJA = 98.0ºC/W, TA = 25°C, TJ = 150°C See Figure 3 INPUT 0.05 W DRIVER A 0.60 DRIVER B 0.60 TOTAL 1.25 TS Safety temperature 150 °C The safety-limiting constraint is the maximum junction temperature specified in the datasheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. More detailed information about junction temperature prediction can be found in Estimating Junction Temperature

6.9 Electrical Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.5 2.0 mA IVDDA, IVDDB VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.0 1.8 mA IVCCI VCCI operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.0 mA IVDDA, IVDDB VDDA and VDDB operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.5 mA VCCI SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS VVCCI_ON Rising threshold 2.55 2.7 2.85 V VVCCI_OFF Falling threshold VCCI_OFF 2.35 2.5 2.65 V VVCCI_HYS Threshold hysteresis 0.2 V VDD SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS VVDDA_ON, VVDDB_ON Rising threshold VDDA_ON, VDDB_ON 5.7 6.0 6.3 V VVDDA_OFF, VVDDB_OFF Falling threshold VDDA_OFF, VDDB_OFF 5.4 5.7 6 V VVDDA_HYS, VVDDB_HYS Threshold hysteresis 0.3 V INA, INB AND DISABLE VINAH, VINBH, VDISH Input high voltage 1.6 1.8 2 V VINAL, VINBL, VDISL Input low voltage 0.8 1 1.2 V VINA_HYS, VINB_HYS, VDIS_HYS Input hysteresis 0.8 V VINA, VINB Negative transient, ref to GND, 50 ns pulse Not production tested, bench test only –5 V

www.ti.com SLUSCV6 – APRIL 2017 Product Folder Links: UCC21225A Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT IOA+, IOB+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 4 A IOA-, IOB- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 6 A ROHA, ROHB Output resistance at high state IOUT = –10 mA, TA = 25°C, ROHA, ROHB do not represent drive pull- up performance. See tRISE in Switching Characteristics and Output Stage for details. 5 Ω ROLA, ROLB Output resistance at low state IOUT = 10 mA, TA = 25°C 0.55 Ω VOHA, VOHB Output voltage at high state VVDDA, VVDDB = 12 V, IOUT = –10 mA, TA = 25°C 11.95 V VOLA, VOLB Output voltage at low state VVDDA, VVDDB = 12 V, IOUT = 10 mA, TA = 25°C 5.5 mV DEADTIME AND OVERLAP PROGRAMMING Dead time Pull DT pin to VCCI Overlap determined by INA INB - DT pin is left open, min spec characterized only, tested for outliers 0 8 15 ns RDT = 20 kΩ 160 200 240 ns

6.10 Switching Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tRISE Output rise time, 20% to 80% measured points COUT = 1.8 nF 6 16 ns tFALL Output fall time, 90% to 10% measured points COUT = 1.8 nF 7 12 ns tPWmin Minimum pulse width Output off for less than minimum, COUT = 0 pF 20 ns tPDHL Propagation delay from INx to OUTx falling edges 19 30 ns tPDLH Propagation delay from INx to OUTx rising edges 19 30 ns tPWD Pulse width distortion |tPDLH – tPDHL| 6 ns tDM Propagation delays matching between VOUTA, VOUTB 5 ns CMTI Static common-mode transient immunity (See CMTI Testing) PWM is tied to GND or VCCI, VCM=1200V. 100 V/ns

6.11 Insulation Characteristics and Thermal Derating Curves

Figure 1. Isolation Capacitor Life Time Projection Figure 2. Thermal Derating Curve for Figure 3. Thermal Derating Curve for

6.12 Typical Characteristics

VDDA = VDDB = 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted. Figure 4. Per Channel Current Consumption vs. Frequency Figure 5. Per Channel Current Consumption (IVDDA/B) vs. Figure 6. Per Channel Current Consumption (IVDDA/B) vs. Figure 7. Per Channel (IVDDA/B) Supply Current Vs. Figure 8. Per Channel (IVDDA/B) Quiescent Supply Current vs Figure 9. IVCCI Quiescent Supply Current vs Temperature

7 Parameter Measurement Information

7.1 Propagation Delay and Pulse Width Distortion

disabling the dead time function by shorting the DT Pin to VCC. Figure 24. Overlapping Inputs, Dead Time Disabled

7.2 Rising and Falling Time

short rising and falling times are achieved see Output Stage. Figure 25. Rising and Falling Time Criteria

7.3 Input and Disable Response Time

Figure 26 shows the response time of the disable function. For more information, see Disable Pin . Figure 26. Disable Pin Timing

7.4 Programable Dead Time

more details on dead time, refer to Programmable Dead Time (DT) Pin. Figure 27. Dead-Time Switching Parameters

7.5 CMTI Testing

Figure 28 is a simplified diagram of the CMTI testing configuration. Figure 28. Simplified CMTI Testing Setup

4,7 GND INB DT DIS INA VCCI Copyright © 2017, Texas Instruments Incorporated 200 k: 200 k: 200 k: UVLO VCCI UCC21225A www.ti.com SLUSCV6 – APRIL 2017 Product Folder Links: UCC21225A Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

There are several instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors. This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V logic signal capable of delivering only a few mA. In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are often placed between the output of control devices and the gates of power transistors. The UCC21225A is a flexible dual gate driver which can be configured to fit a variety of power supply and motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. UCC21225A has many features that allow it to integrate well with control circuitry and protect the gates it drives such as: resistor- programmable dead time (DT) control, a DISABLE pin, and under voltage lock out (UVLO) for both input and output voltages. The UCC21225A also holds its outputs low when the inputs are left open or when the input pulse is not wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital and analog power controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing full and independent control of each of the outputs.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

the status of the input pins (INA and INB). channel safety supply power, the ambient temperature, and the 6A peak sink current rating. Figure 29. Simplified Representation of Active Pull Down Feature occurs when the device starts switching and operating current consumption increases suddenly. operation during VCCI or VDD brownouts.

The UCC21225A can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI. Table 1. UCC21225A VCCI UVLO Feature Logic Table 2. UCC21225A VDD UVLO Feature Logic

(1) "X" means L, H or left open.

8.3.2 Input and Output Logic Table

(UVLO) for more information on UVLO operation modes. Table 3. INPUT/OUTPUT Logic Table(1)

8.3.3 Input Stage

Diagram). However, it is still recommended to ground an input if it is not being used for improved noise immunity. said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than VCCI.

8.3.4 Output Stage

resistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated. parameter, yielding a faster turn-on. The turn-on phase output resistance is the parallel combination ROH||RNMOS. Figure 30. Output Stage

20 V 20 V

8.3.5 Diode Structure in UCC21225A

provides a pictorial representation of the absolute maximum rating for the device. Figure 31. ESD Structure

8.4 Device Functional Modes

8.4.1 Disable Pin

8.4.2 Programmable Dead Time (DT) Pin

8.4.2.1 Tying the DT Pin to VCC

Outputs completely match inputs, so no dead time is asserted by the IC. This allows outputs to overlap.

8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins

time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time. Figure 32. Input and Output Logic Relationship With Input Signals time to OUTA. OUTA is allowed to go high after the programmed dead time. dead time to OUTB. OUTB is allowed to go high after the programmed dead time. when INA goes high, it immediately sets OUTA high. OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high. OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

automotive, and industrial applications with a faster time to market.

9.2 Typical Application

boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications. Figure 33. Typical Application Schematic

9.2.1 Design Requirements

high side-low side configuration. Table 4. UCC21225A Design Requirements

9.2.2 Detailed Design Procedure

9.2.2.1 Designing INA/INB Input Filter

non-ideal layout or long PCB traces. example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.

9.2.2.2 Select External Bootstrap Diode and Series Resistor

in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop. 400-VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin. Therefore, a 600-V ultrafast diode, MURA160T3G, is chosen in this example. used. In the example, a current limiting resistor of 2.7 Ω is selected to limit the inrush current of bootstrap diode.

VBDF is the estimated bootstrap diode forward voltage drop at 4 A. (2)

OL OFF ON GFET _ Int V VI min 6A, R R R R/c45 /c230 /c246 /c45/c61 /c231 /c247 /c231 /c247 /c43 /c43/c232 /c248 DD BDF GDF OA OL OFF ON GFET _ Int V V VI min 6A, R R R R/c45 /c230 /c246 /c45 /c45/c61 /c231 /c247 /c231 /c247 /c43 /c43/c232 /c248 DD OB NMOS OH ON GFET _ Int V 12 VI 2.5 AR R R R 1.47 5 2.2 1.5/c43 /c61 /c61 /c187 /c43 /c43 /c87 /c87 /c43 /c87 /c43 /c87 DD BDF OA NMOS OH ON GFET _ Int /c45 /c45/c61 /c61 /c187 /c43 /c43 /c87 /c87 /c43 /c87 /c43 /c87 DD OB NMOS OH ON GFET _ Int VI min 4A, R R R R/c43 /c230 /c246 /c61 /c231 /c247/c231 /c247/c43 /c43/c232 /c248 DD BDF OA NMOS OH ON GFET _ Int V VI min 4A, R R R R/c43 /c230 /c246/c45/c61 /c231 /c247/c231 /c247/c43 /c43/c232 /c248 UCC21225A SLUSCV6 – APRIL 2017 www.ti.com Product Folder Links: UCC21225A Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

9.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, RON/ROFF, are used to: 1. Limit ringing caused by parasitic inductances/capacitances. 2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery. 3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss. 4. Reduce electromagnetic interference (EMI). As mentioned in Output Stage, the UCC21225A has a pull-up structure with a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak source current can be predicted with: (3) where

RON: External turn-on resistance.
RGFET_Int: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the calculated value based on the gate drive loop resistance. (4) In this example: (5) (6) Therefore, the high-side and low-side peak source currents are 2.2 A and 2.5 A respectively. Similarly, the peak sink current can be calculated with: (7) where
ROFF: External turn-off resistance.
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an MSS1P4.
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated value based on the gate drive loop resistance. (8)

GSWP 2 12 V 100 nC 200 kHz 480 mW/c61 /c180 /c180 /c180 /c61 GSW DD G SWP 2 V Q f/c61 /c180 /c180 /c180 GDQ VCCI VCCI VDDA VDDA VDDB VDDBP V I V I V I 46 mW/c61 /c180 /c43 /c180 /c43 /c180 /c187 DD GDF OB OL OFF ON GFET _ Int V V 12 V 0.75 VI 5.5 AR R R R 0.55 0 1.5/c45 /c45 /c45/c61 /c61 /c187 /c43 /c43 /c87 /c43 /c87 /c43 /c87 DD BDF GDF OA OL OFF ON GFET _ Int /c45 /c45 /c45 /c45/c61 /c61 /c187 /c43 /c43 /c87 /c43 /c87 /c43 /c87 UCC21225A www.ti.com SLUSCV6 – APRIL 2017 Product Folder Links: UCC21225A Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated In this example, (9) (10) Therefore, the high-side and low-side peak sink currents are 5.1 A and 5.5 A respectively. Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the parasitic ringing period.

9.2.2.4 Estimate Gate Driver Power Loss

The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21225A (PGD) and the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in PG and is not discussed in this section. PGD is the key power loss which determines the thermal safety-related limits of the UCC21225A, and it can be estimated by calculating losses from several components. The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and ambient temperature. Figure 4 shows the per output channel current consumption vs. operating frequency with no load. In this example, VVCCI = 5 V and VVDD = 12 V. The current on each power supply, with INA/INB switching from 0 V to 3.3 V at 200 kHz, is measured to be IVCCI = 2 mA, and IVDDA = IVDDB = 1.5 mA. Therefore, the PGDQ can be calculated with (11) The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be estimated with where

QG is the gate charge of the power transistor at VVDD. (12) If a split rail is used for turn on and turn off, then VVDD is the total difference between the positive rail to the negative rail. So, for this example application: (13)

J C JT GDT T P/c61 /c43 /c89 /c180 GD GDQ GDOP P P 46 mW 120 mW 166 mW/c61 /c43 /c61 /c43 /c61 /c40 /c41 R _ Sys F _ Sys A /B A /B T T GDO SW DD OUT OUT 0 0 P 2 f 4 A V V (t) dt 6 A V (t) dt /c233 /c249 /c234 /c250/c61 /c180 /c180 /c180 /c45 /c43 /c180 /c234 /c250 /c234 /c250/c235 /c251 /c242 /c242 GDO /c230 /c246/c87 /c87 /c87/c61 /c43 /c187/c231 /c247/c231 /c247/c87 /c87 /c43 /c87 /c43 /c87 /c87 /c43 /c87 /c43 /c87/c232 /c248 OH NMOSGSW OL GDO OH NMOS ON GFET _ Int OL OFF ON GFET _ Int R RP RP 2 R R R R R R R R /c230 /c246 /c61 /c43/c231 /c247/c231 /c247/c43 /c43 /c43 /c43/c232 /c248 UCC21225A SLUSCV6 – APRIL 2017 www.ti.com Product Folder Links: UCC21225A Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated QG represents the total gate charge of the power transistor switching 400 V at 14 A, and is subject to change with different testing conditions. The UCC21225A gate driver loss on the output stage, PGDO, is part of PGSW. PGDO will be equal to PGSW if the external gate driver resistances and power transistor internal resistances are 0- Ω, and all the gate driver loss will be dissipated inside the UCC21225A. If there are external turn-on and turn-off resistances, the total loss will be distributed between the gate driver pull-up/down resistances, external gate resistances, and power transistor internal resistances. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios. Case 1 - Linear Pull-Up/Down Resistor: (14) In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21225A gate driver loss can be estimated with: (15) Case 2 - Nonlinear Pull-Up/Down Resistor: where

VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off period. In cases where the output is saturated for some time, this can be simplified as a constant current source (4 A at turn-on and 6 A at turn-off) charging/discharging a load capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted. (16) For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull- down based on the above discussion. The total gate driver loss dissipated in the gate driver UCC21225A, PGD, is: (17)

9.2.2.5 Estimating Junction Temperature

The junction temperature (TJ) of the UCC21225A can be estimated with: where

TC is the UCC21225A case-top temperature measured with a thermocouple or some other instrument, and
ΨJT is the Junction-to-top characterization parameter from the Thermal Information table. (18) Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance (RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy leaving through the top of the IC will be similar in both the testing environment and the application environment. As long as the recommended layout guidelines are observed, junction temperature estimates can be made accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package Thermal Metrics application report.

Q 107.5 nCC 0.22 F V 0.5 V/c61 /c61 /c187 /c109/c68 VDD Total G SW I @ 200 kHz (No Load) 1.5 mAQ Q 100 nC 107.5 nC f 200 kHz/c61 /c43 /c61 /c43 /c61 UCC21225A www.ti.com SLUSCV6 – APRIL 2017 Product Folder Links: UCC21225A Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

9.2.2.6 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500-nF when a DC bias of 15-VDC is applied.

9.2.2.6.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100-nF is recommended for this application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or electrolytic capacitor, with a value over 1-µF, should be placed in parallel with the MLCC.

9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for gate drive current transients up to 6-A, and needs to maintain a stable gate drive voltage for the power transistor. The total charge needed per switching cycle can be estimated with where

QG: Gate charge of the power transistor at VVDD
IVDD: The channel self-current consumption with no load at 200-kHz. (19) Therefore, the absolute minimum CBoot requirement is: where
ΔVVDDA is the voltage ripple at VDDA, which is 0.5-V in this example. (20) In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients. Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example. (21) To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance. NOTE Too much CBOOT can be detrimental. CBOOT may not be charged within the first few cycles and VBOOT could stay below UVLO. As a result, the high-side FET will not follow input signal commands for several cycles. Also during initial CBOOT charging cycles, the bootstrap diode has highest reverse recovery current and losses.

Setting Re q F _ Sys R _ Sys D(on)DT DT T T T/c61 /c43 /c43 /c45 UCC21225A SLUSCV6 – APRIL 2017 www.ti.com Product Folder Links: UCC21225A Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

9.2.2.6.3 Select a VDDB Capacitor

Channel B has the same current requirements as Channel A. Therefore, a VDDB capacitor (shown as CVDD in Figure 33) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 0.22-µF MLCC are chosen for CVDD. If the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor, with a value over 10-µF, should be used in parallel with CVDD.

9.2.2.7 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor is important for preventing shoot-through during dynamic switching. The UCC21225A dead time specification in the electrical table is defined as the time interval from 90% of one channel’s falling edge to 10% of the other channel’s rising edge (see Figure 27). This definition ensures that the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing. However, this dead time setting may not reflect the dead time in the power converter system, since the dead time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as well as the input capacitance of the load transistor. Here is a suggestion on how to select an appropriate dead time for UCC21225A: where

DTSetting: UCC21225A dead time setting in ns, DTSetting = 10 × RDT (in kΩ).
DTReq: System required dead time between the real VGS signal of the top and bottom switch with enough margin, or ZVS requirement.
TF_Sys: In-system gate turn-off falling time at worst case of load, voltage/current conditions.
TR_Sys: In-system gate turn-on rising time at worst case of load, voltage/current conditions.
TD(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold. (22) In the example, DTSetting is set to 250 ns. It should be noted that the UCC21225A dead time setting is decided by the DT pin configuration (See Programmable Dead Time (DT) Pin), and it cannot automatically fine-tune the dead time based on system conditions. It is recommended to parallel a ceramic capacitor, 2.2 nF or above, close to DT pin to achieve better noise immunity and dead time matching.

9.2.2.8 Application Circuits with Output Stage Negative Bias

the threshold. Below are a few examples of implementing negative gate drive bias. supply, VA, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V –5.1 V ≈ 20 V. a half-bridge configuration, and there will be steady state power consumption from RZ. Figure 34. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which means the negative bias

resonant converters or phase shift converters favor this solution.

The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range, which means the low side

for the high side, like in the other two example circuits. Figure 36. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

9.2.3 Application Curves

these conditions: VCC = 5 V, VDD = 12 V, fSW = 200 kHz, VDC-Link = 400 V. Channel 1 (Indigo): UCC21225A INA pin signal. Channel 2 (Cyan): UCC21225A INB pin signal. Channel 3 (Magenta): Gate-source signal on the high side power transistor. Channel 4 (Green): Gate-source signal on the low side power transistor. bandwidth differential probes are required, which limits the achievable accuracy of the measurement. falling time (25 ns) are observed in Figure 38. Figure 37. Bench Test Waveform for INA/B and OUTA/B Figure 38. Zoomed-In bench-test waveform

10 Power Supply Recommendations

The recommended input supply voltage (VCCI) for UCC21225A is between 3 V and 18 V. The lower end of the output bias supply voltage (VDDA/VDDB) range is governed by the internal under voltage lockout (UVLO) protection feature of the device. VDD and VCCI should not fall below their respective UVLO thresholds for normal operation, or else gate driver outputs can become clamped low for >50µs by the UVLO protection feature. (For more information on UVLO see VDD, VCCI, and Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by UCC21225A, and should not exceed the recommended maximum VDDA/VDDB of 25-V. A local bypass capacitor should be placed between the VDD and VSS pins, with a value of between 220 nF and 10 µF for device biasing. It is further suggested that an additional 100-nF capacitor be placed in parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be positioned as close to the device as possible. Low ESR, ceramic surface mount capacitors are recommended. Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of UCC21225A, this bypass capacitor has a minimum recommended value of 100 nF.

11 Layout

11.1 Layout Guidelines

Designers must pay close attention to PCB layout in order to achieve optimum performance for the UCC21225A. Below are some key points. Component Placement:

Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins and between the VDD and VSS pins to bypass noise and to support high peak currents when turning on the external power transistor.
To avoid large negative transients on VSS pins connected to the switch node, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized.
It is recommended to place the dead time setting resistor, RDT, and its bypassing capacitor close to DT pin of UCC21225A. Grounding Considerations:
It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the transistors. The gate driver must be placed as close as possible to the transistors.
Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB- referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and area on the circuit board is important for ensuring reliable operation. High-Voltage Considerations:
To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB traces or copper below the driver device. PCB cutting or scoring beneath the IC are not recommended, since this can severely exacerbate board warping and twisting issues.
For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could operate with a DC-link voltage up to 700 VDC, one should try to increase the creepage distance of the PCB layout between the high and low-side PCB traces. Thermal Considerations:
A large amount of power may be dissipated by the UCC21225A if the driving voltage is high, the load is heavy, or the switching frequency is high (Refer to Estimate Gate Driver Power Loss for more details). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance (θJB).
Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority on maximizing the connection to VSSA and VSSB (see Figure 40 and Figure 41). However, high voltage PCB considerations mentioned above must be maintained.
If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and VSSB pins to internal ground or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to maximize thermal conductivity. However, keep in mind that there shouldn’t be any traces/coppers from different high voltage planes overlapping.

11.2 Layout Example

Figure 39 shows a 2-layer PCB layout example with the signals and key components labeled. Figure 39. Layout Example Figure 40 and Figure 41 shows top and bottom layer traces and copper. ensures isolation performance.

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

Isolation Glossary

12.2 Certifications

Pending agency approval.

12.2.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 9-May-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples UCC21225ANPLR ACTIVE VLGA NPL 13 3000 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 125 UCC21225A UCC21225ANPLT ACTIVE VLGA NPL 13 250 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 125 UCC21225A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 9-May-2017 Addendum-Page 2

www.ti.com PACKAGE OUTLINE C 3.9 12X 0.65 (0.1) TYP 13X 0.7 0.6

1 MAX

13X 0.35 0.25 2.075 4.15 B 5.1 4.9 A 5.1 4.9 (0.7) VLGA - 1 max heightNPL0013A LAND GRID ARRAY 4222800/B 04/2017 PIN 1 INDEX AREA

0.08 C SEATING PLANE

0.15 C A B

0.08 C SYMM SYMM

0.15 C B A

NOTE 3NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Pin 1 indicator is electrically connected to pin 1. 0.08 C SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 13X (0.65)

0.07 MAX

0.07 MIN

13X (0.3) (4.15) 10X (0.65) (R0.05) TYP VLGA - 1 max heightNPL0013A LAND GRID ARRAY 4222800/B 04/2017 SYMM SYMM LAND PATTERN EXAMPLE 1:1 RATIO WITH PACKAGE SOLDER PADS SCALE:15X NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE METAL UNDER SOLDER MASK SOLDER MASK OPENING SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 13X (0.65) 13X (0.3) 10X (0.65) (4.15) (R0.05) VLGA - 1 max heightNPL0013A LAND GRID ARRAY 4222800/B 04/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM SYMM

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Product Information

NPL0013A specifications and overview.

Summary

4-A, 6-A, 2.5-kVRMS Isolated Dual-Channel Gate Driver in LGA

Description

4-A, 6-A, 2.5-kVRMS Isolated Dual-Channel Gate Driver in LGA

Source title NPL0013A Datasheet(PDF) - Texas Instruments

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