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Technical content

Features

  • Fixed−Frequency Current−Mode Operation (65 kHz and 100 kHz frequency options)
  • Frequency Foldback then Skip Mode for Maximized Performance in Light Load and Standby Conditions
  • Timer−Based Overload Protection with Latched (Options A/C) or Auto−Recovery (Options B/D) Operation
  • High−voltage Current Source with Brown−Out Detection and Dynamic Self−Supply, Simplifying the Design of the VCC Circuitry
  • Frequency Modulation for Softened EMI Signature
  • Adjustable Overpower Protection Dependant on the Bulk V oltage
  • Latch−off Input Combined with the Overpower Protection Sensing Input
  • VCC Operation up to 28 V , With Overvoltage Detection
  • 500/800 mA Source/Sink Drive Peak Current Capability
  • 10 ms Soft−Start
  • Internal Thermal Shutdown
  • No−Load Standby Power < 30 mW
  • X2 Capacitor in EMI Filter Discharging Feature
  • These Devices are Pb−Free and Halogen Free/BFR Free Typical Applications
  • AC−DC Adapters for Notebooks, LCD, and Printers
  • Offline Battery Chargers
  • Consumer Electronic Power Supplies
  • Auxiliary/Housekeeping Power Supplies
  • Offline Adapters for Notebooks SOIC−7 CASE 751U MARKING DIAGRAM http://onsemi.com 47Xff ALYWX /C0071 47Xff = Specific Device Code X = A, B, C or D ff = 65 or 100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071 = Pb−Free Package See detailed ordering and shipping information in the package dimensions section on page 41 of this data sheet.

ORDERING INFORMATION

(Top View) Latch CS HV PIN CONNECTIONS 2FB GND DRV VCC

Figure 1. Flyback Converter Application Using the NCP1247 allows the direct connection of an NTC for over temperature detection. goes to the low consumption Off mode if the FB input pin is pulled to GND.

3 CS Current Sense This Input senses the Primary Current for current−mode operation, and

offers an overpower compensation adjustment.

4 GND − The controller ground

5 DRV Drive output Drives external MOSFET

another circuit to this pin to keep low input power consumption.

8 HV High−voltage pin Connects to the rectified AC line to perform the functions of Start−up

purposes. It is not allowed to connect this pin to DC voltage.

Figure 2. Simplified Internal Block Schematic

http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit DRV (pin 5) Maximum voltage on DRV pin (Dc−Current self−limited if operated within the allowed range) (Note 1) –0.3 to 20 ±1000 (peak) V mA VCC (pin 6) VCCPower Supply voltage, VCC pin, continuous voltage Power Supply voltage, VCC pin, continuous voltage (Note 1) –0.3 to 28 ±30 (peak) V mA HV (pin 8) Maximum voltage on HV pin (Dc−Current self−limited if operated within the allowed range) –0.3 to 500 ±20 V mA Vmax Maximum voltage on low power pins (except pin 5, pin 6 and pin 8) (Dc−Current self−limited if operated within the allowed range) (Note 1) –0.3 to 10 ±10 (peak) V mA R/C0113J−A Thermal Resistance SOIC−7 Junction-to-Air, low conductivity PCB (Note 2) Junction-to-Air, medium conductivity PCB (Note 3) Junction-to-Air, high conductivity PCB (Note 4) 162 147 115 °C/W R/C0113J−C Thermal Resistance Junction−to−Case 73 °C/W TJMAX Operating Junction Temperature −40 to +150 °C TSTRGMAX Storage Temperature Range −60 to +150 °C ESD Capability, HBM model (All pins except HV) per JEDEC Standard JESD22, Method A114E > 2000 V ESD Capability, Machine Model per JEDEC Standard JESD22, Method A115A > 200 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above t he Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78. 2. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm 2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow. 3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow. 4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow.

http://onsemi.com ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Characteristics Test Condition Symbol Min Typ Max Unit HIGH VOLTAGE CURRENT SOURCE Minimum voltage for current source operation VHV(min) − 30 40 V Current flowing out of VCC pin (X2 discharge current value is equal to Istart2) VCC = 0 V VCC = VCC(on) − 0.5 V Istart1 Istart2 0.2 0.5 0.8 mA Off−state leakage current VHV = 500 V, VCC = 15 V Istart(off) 10 25 50 /C0109A Off−mode HV supply current VHV = 141 V, VHV = 325 V, VCC loaded by 4.7 /C0109F cap IHV(off) − /C0109A SUPPLY HV current source regulation threshold VCC(reg) 8 11 − V Turn−on threshold level, VCC going up HV current source stop threshold VCC(on) 11.0 12.0 13.0 V HV current source restart threshold VCC(min) 9.5 10.5 11.5 V Turn−off threshold VCC(off) 8.5 8.9 9.3 V Overvoltage threshold VCC(ovp) 25 26.5 28 V Blanking duration on VCC(off) and VCC(ovp) detection tVCC(blank) − 10 − /C0109s VCC decreasing level at which the internal logic resets VCC(reset) 4.8 7.0 7.7 V VCC level for ISTART1 to ISTART2 transition VCC(inhibit) 0.2 0.8 1.25 V Internal current consumption (Note 5) DRV open, VFB = 3 V, 65 kHz DRV open, VFB = 3 V, 100 kHz Cdrv = 1 nF, VFB = 3 V, 65 kHz Cdrv = 1 nF, VFB = 3 V, 100 kHz Off mode (skip or before start−up) Fault mode (fault or latch) ICC1 ICC1 ICC2 ICC2 ICC3 ICC4 1.3 1.3 1.8 2.3 0.67 0.3 1.85 1.85 2.6 2.9 0.9 0.6 2.2 2.2 3.0 3.5 1.13 0.9 mA BROWN−OUT Brown−Out thresholds (A/B versions) VHV going up VHV going down VHV(start) VHV(stop) 102 111 103 120 112 V Brown−Out thresholds (C/D versions) VHV going up VHV going down VHV(start) VHV(stop) 103 V Timer duration for line cycle drop−out tHV 52 73 94 ms X2 DISCHARGE Comparator hysteresis observed at HV pin VHV(hyst) 1.5 3.5 5 V HV signal sampling period Tsample − 1.0 − ms Timer duration for no line detection tDET 21 32 43 ms Discharge timer duration tDIS 21 32 43 ms OSCILLATOR Oscillator frequency fOSC 58 100 109 kHz Maximum on time for TJ = 25°C to +125°C only fOSC = 65 kHz fOSC = 100 kHz tONmax(65kHz) tONmax(100kHz) 11.5 7.5 12.3 8.0 13.1 8.5 /C0109s 5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only). 6. Guaranteed by design. 7. CS pin source current is a sum of I bias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.

http://onsemi.com ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Characteristics UnitMaxTypMinSymbolTest Condition OSCILLATOR Maximum on time fOSC = 65 kHz fOSC = 100 kHz tONmax(65kHz) tONmax(100kHz) 11.3 7.4 12.3 8.0 13.1 8.5 /C0109s Maximum duty cycle (corresponding to maximum on time at maximum switching frequency) fOSC = 65 kHz fOSC = 100 kHz DMAX − 80 − % Frequency jittering amplitude, in percentage of F OSC Ajitter ±4 ±6 ±8 % Frequency jittering modulation frequency Fjitter 85 125 165 Hz FREQUENCY FOLDBACK Feedback voltage threshold below which frequency foldback starts VFB(foldS) 1.8 2.0 2.2 V Feedback voltage threshold below which frequency foldback is complete VFB(foldE) 0.8 0.9 1.0 V Minimum switching frequency VFB = Vskip(in) + 0.1 fOSC(min) 23 27 32 kHz OUTPUT DRIVER Rise time, 10% to 90% of VCC VCC = VCC(min) + 0.2 V, CDRV = 1 nF trise − 40 70 ns Fall time, 90% to 10% of VCC VCC = VCC(min) + 0.2 V, CDRV = 1 nF tfall − 40 70 ns Current capability VCC = VCC(min) + 0.2 V, CDRV = 1 nF DRV high, VDRV = 0 V DRV low, VDRV = VCC IDRV(source) IDRV(sink) 500 800 mA Clamping voltage (maximum gate voltage) VCC = VCCmax – 0.2 V, DRV high, RDRV = 33 k/C0087, Cload = 220 pF VDRV(clamp) 11 13.5 16 V High−state voltage drop VCC = VCC(min) + 0.2 V, RDRV = 33 k/C0087, DRV high VDRV(drop) − − 1 V CURRENT SENSE Input Pull−up Current VCS = 0.7 V Ibias − 1 − /C0109A Maximum internal current setpoint VFB > 3.5 V VILIM 0.66 0.70 0.74 V Propagation delay from VIlimit detection to DRV off VCS = VILIM tdelay − 80 110 ns Leading Edge Blanking Duration for VILIM tLEB 200 250 320 ns Threshold for immediate fault protection activation VCS(stop) 0.95 1.05 1.15 V Leading Edge Blanking Duration for VCS(stop) (Note 6) tBCS 90 120 150 ns Soft−start duration From 1st pulse to VCS = VILIM tSSTART 8 11 14 ms Frozen current setpoint VI(freeze) 275 300 325 mV INTERNAL SLOPE COMPENSATION Slope of the compensation ramp Scomp(65kHz) Scomp(100kHz) −32.5 −50 mV / /C0109s FEEDBACK Internal pull−up resistor TJ = 25°C RFB(up) 15 20 25 k/C0087 5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only). 6. Guaranteed by design. 7. CS pin source current is a sum of I bias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.

http://onsemi.com ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Characteristics UnitMaxTypMinSymbolTest Condition FEEDBACK VFB to internal current setpoint division ratio KFB 4.7 5 5.3 − Internal pull−up voltage on the FB pin (Note 6) VFB(ref) 4.5 5 5.5 V Feedback voltage below which the peak current is frozen VFB(freeze) 1.35 1.5 1.65 V SKIP CYCLE MODE Feedback voltage thresholds for skip mode VFB going down VFB going up Vskip(in) Vskip(out) 0.63 0.72 0.70 0.80 0.77 0.88 V REMOTE CONTROL ON FB PIN The voltage above which the part enters the on mode VCC > VCC(off), VHV = 60 V VON − 2.2 − V The voltage below which the part enters the off mode VCC > VCC(off) VOFF 0.35 0.40 0.45 V Minimum hysteresis between the VON and VOFF VCC > VCC(off), VHV = 60 V VHYST 500 − − mV Pull−up current in off mode VCC > VCC(off) IOFF − 5 − /C0109A Go To Off mode timer VCC > VCC(off) tGTOM 100 150 300 ms OVERLOAD PROTECTION Fault timer duration tfault 108 128 178 ms Autorecovery mode latch−off time duration tautorec 0.85 1.00 1.35 s OVERPOWER PROTECTION VHV to IOPC conversion ratio KOPC − 0.54 − /C0109A / V Current flowing out of CS pin (Note 7) VHV = 125 V VHV = 162 V VHV = 325 V VHV = 365 V IOPC(125) IOPC(162) IOPC(325) IOPC(365) 105 110 130 150 /C0109A FB voltage above which IOPC is applied VHV = 365 V VFB(OPCF) 2.12 2.35 2.58 V FB voltage below which is no IOPC applied VHV = 365 V VFB(OPCE) − 2.15 − V LATCH−OFF INPUT High threshold VLatch going up VOVP 2.35 2.5 2.65 V Low threshold VLatch going down VOTP 0.76 0.8 0.84 V Current source for direct NTC connection During normal operation During soft−start VLatch = 0 V INTC INTC(SSTART) 130 190 105 210 /C0109A Blanking duration on high latch detection 65 kHz version 100 kHz version tLatch(OVP) 35 /C0109s Blanking duration on low latch detection tLatch(OTP) − 350 − /C0109s Clamping voltage ILatch = 0 mA ILatch = 1 mA Vclamp0(Latch) Vclamp1(Latch) 1.0 1.8 1.2 2.4 1.4 3.0 V TEMPERATURE SHUTDOWN Temperature shutdown TJ going up TTSD − 150 − °C Temperature shutdown hysteresis TJ going down TTSD(HYS) − 30 − °C 5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only). 6. Guaranteed by design. 7. CS pin source current is a sum of I bias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.

http://onsemi.com

APPLICATION INFORMATION

The NCP1247 includes all necessary features to build a safe and efficient power supply based on a fixed−frequency flyback converter. The NCP1247 is a multimode controller as illustrated in Figure 45. The mode of operation depends upon line and load condition. Under all modes of operation, the NCP1247 terminates the DRV signal based on the switch current. Thus, the NCP1247 always operates in current mode control so that the power MOSFET current is always limited. Under normal operating conditions, the FB pin commands the operating mode of the NCP1247 at the voltage thresholds shown in Figure 45. At normal rated operating loads (from 100% to approximately 33% full rated power) the NCP1247 controls the converter in fixed frequency PWM mode. It can operate in the continuous conduction mode (CCM) or discontinuous conduction mode (DCM) depending upon the input voltage and loading conditions. If the controller is used in CCM with a wide input voltage range, the duty−ratio may increase up to 50%. The build−in slope compensation prevents the appearance of sub−harmonic oscillations in this operating area. For loads that are between approximately 32% and 10% of full rated power, the converter operates in frequency foldback mode (FFM). If the feedback pin voltage is lower than 1.5 V the peak switch current is kept constant and the output voltage is regulated by modulating the switching frequency for a given and fixed input voltage V HV. Effectively, operation in FFM results in the application of constant volt −seconds to the flyback transformer each switching cycle. V oltage regulation in FFM is achieved by varying the switching frequency in the range from 65 kHz (or 100 kHz) to 27 kHz. For extremely light loads (below approximately 6% full rated power), the converter is controlled using bursts of 27 kHz pulses. This mode is called as skip mode. The FFM, keeping constant peak current and skip mode allows design of the power supplies with increased efficiency under the light loading conditions. Keep in mind that the aforementioned boundaries of steady−state operation are approximate because they are subject to converter design parameters. Figure 45. Mode Control with FB pin voltage voltage increases above the 2.2 V level.

Figure 46. Operating Status Diagram for the Fully Latched Versions A/C of the Device

Figure 47. Operating Status Diagram for the Autorecovery Versions B/D of the Device

device by the remote control being in off mode. controller actually starts the next time VCC reaches VCC(on). increases before the current−mode control takes over. Figure 48. VCC Start−up Timing Diagram

http://onsemi.com For safety reasons, the start−up current is lowered when VCC is below VCC(inhibit), to reduce the power dissipation in case the VCC pin is shorted to GND (in case of VCC capacitor failure, or external pull −down on V CC to disable the controller). There is only one condition for which the current source doesn’t turn on when VCC reaches VCC(inhibit): the voltage on HV pin is too low (below VHV(min)). HV Sensing of Rectified AC Voltage The NCP1247 features on its HV pin a true ac line monitoring circuitry. It includes a minimum start −up threshold and an autorecovery brown−out protection; both of them independent of the ripple on the input voltage. It is allowed only to work with an unfiltered, rectified ac input to ensure the X2 capacitor discharge function as well, which is described in following. The brown −out protection thresholds are fixed, but they are designed to fit most of the standard ac−dc conversion applications. When the input voltage goes below V HV(stop), a brown−out condition is detected, and the controller stops. The HV current source maintains VCC at VCC(min) level until the input voltage is back above VHV(start).

Figure 49. Ac Line Drop−out Timing Diagram

Figure 50. Ac Line Drop−out Timing Diagram with the Parasitic Spike

Figure 51. Detailed Timing Diagram of the Device Restart After the Short ac Line Drop−out

http://onsemi.com X2 Cap Discharge Feature The X2 capacitor discharging feature is offered by usage of the NCP1247. This feature save approx. 16 mW − 25 mW input power depending on the EMI filter X2 capacitors volume and it saves the external components count as well. The discharge feature is ensured via the start −up current source with a dedicated control circuitry for this function. The X2 capacitors are being discharged by current defined as I start2 when this discharge event is detected. There is used a dedicated structure called ac line unplug detector inside the X2 capacitor discharge control circuitry. See the Figure 52 for the block diagram for this structure and Figures 53, 54, 55 and 56 for the timing diagrams. The basic idea of ac line unplug detector lies in comparison of the direct sample of the high voltage obtained via the high voltage sensing structure with the delayed sample of the high voltage. The delayed signal is created by the sample & hold structure. The comparator used for the comparison of these signals is without hysteresis inside. The resolution between the slopes of the ac signal and dc signal is defined by the sampling time T SAMPLE and additional internal offset NOS. These parameters ensure the noise immunity as well. The additional offset is added to the picture of the sampled HV signal and its analog sum is stored in the C 1 storage capacitor. If the voltage level of the HV sensing structure output crosses this level the comparator CMP output signal resets the detection timer and no dc signal is detected. The additional offset N OS can be measured as the V HV(hyst) on the HV pin. If the comparator output produces pulses it means that the slope of input signal is higher than set resolution level and the slope is positive. If the comparator output produces the low level it means that the slope of input signal is lower than set resolution level or the slope is negative. There is used the detection timer which is reset by any edge of the comparator output. It means if no edge comes before the timer elapses there is present only dc signal or signal with the small ac ripple at the HV pin. This type of the ac detector detects only the positive slope, which fulfils the requirements for the ac line presence detection. In case of the dc signal presence on the high voltage input, the direct sample of the high voltage obtained via the high voltage sensing structure and the delayed sample of the high voltage are equivalent and the comparator produces the low level signal during the presence of this signal. No edges are present at the output of the comparator, that’s why the detection timer is not reset and dc detect signal appears. The minimum detectable slope by this ac detector is given by the ration between the maximum hysteresis observed at HV pin V HV(hyst),max and the sampling time: Smin /C0043 VHV(hyst),max Tsample (eq. 1) Than it can be derived the relationship between the minimum detectable slope and the amplitude and frequency of the sinusoidal input voltage: Vmax /C0043 VHV(hyst),max 2 /C0064/C0112/C0064f /C0064Tsample /C0043 5 2 /C0064/C0112/C006435 /C00641 /C006410−3 (eq. 2) /C004322.7 V The minimum detectable AC RMS voltage is 16 V at frequency 35 Hz, if the maximum hysteresis is 5 V and sampling time is 1 ms. The X2 capacitor discharge feature is available in any controller operation mode to ensure this safety feature. The detection timer is reused for the time limiting of the discharge phase, to protect the device against overheating. The discharging process is cyclic and continues until the ac line is detected again or the voltage across the X2 capacitor is lower than V HV(min). This feature ensures to discharge quite big X2 capacitors used in the input line filter to the safe level. It is important to note that it is not allowed to connect HV pin to any dc voltage due this feature. e.g. directly to bulk capacitor. During the HV sensing or X2 cap discharging the VCC net is kept above the VCC(off) voltage by the Self−Supply in any mode of device operation to supply the control circuitry. During the discharge sequence is not allowed to start−up the device.

Figure 54. The ac Line Unplug Detector Timing Diagram Detail with Noise Effects

Figure 55. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is

Figure 56. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is decreases below the 0.4 V the controller enters the off mode. start, if the FB pin voltage increases above the 2.2 V level. See Figure 57 for timing diagrams. features are disabled in this mode.

28 V, but most of the MOSFETs that will be connected to the

and 800 mA for sink current. input of the PWM comparator through a 250 ns LEB block. current sense is 0.7 V , and it is set by a dedicated comparator. by the soft−start (the two comparators outputs are OR’ed). Figure 63. Soft−Start Feature

http://onsemi.com Overcurrent Protection with Fault timer The overload protection depends only on the current sensing signal, making it able to work with any transformer, even with very poor coupling or high leakage inductance. When an overcurrent occurs on the output of the power supply, the FB loop asks for more power than the controller can deliver, and the CS setpoint reaches VILIM. When this event occurs, an internal tfault timer is started: once the timer times out, DRV pulses are stopped and the controller is either latched off (latched protection, options A/C) or this latch can be released in autorecovery mode (options B/D), the controller tries to restart after t autorec. Other possibilities of the latch release are the brown −out condition or the V CC power on reset. The timer is reset when the CS setpoint goes back below VILIM before the timer elapses. The fault timer is also started if the driver signal is reset by the maximum on time. The controller also enters the same protection mode if the voltage on the CS pin reaches 1.5 times the maximum internal setpoint V CS(stop) (allows to detect winding short−circuits) or there appears low V CC supply. See Figures 71 and 72 for the timing diagram. In autorecovery mode if the fault has gone, the supply resumes operation; if not, the system starts a new burst cycle.

Figure 70. Overpower Compensation Timing Diagram

http://onsemi.com PROTECTION MODES AND THE LATCH MODE RELEASES Event Timer Protection Next Device Status Release to Normal Operation Mode Overcurrent VILIM > 0.7 V Fault timer Latch Autorecovery – B/D version Brown−out VCC < VCC(reset) Maximum on time Fault timer Latch Autorecovery – B/D version Brown−out VCC < VCC(reset) Winding short Vsense > VCS(stop) Immediate reaction Latch Autorecovery – B/D version Brown−out VCC < VCC(reset) Low supply VCC < VCC(off) 10 /C0109s timer Latch Autorecovery – B/D version Brown−out VCC < VCC(reset) External OTP, OVP 55 /C0109s (35 /C0109s at 100 kHz) Latch Brown−out VCC < VCC(reset) High supply VCC > VCC(ovp) 10 /C0109s timer Latch Brown−out VCC < VCC(reset) Brown−out VHV < VHV(stop) HV timer Device stops (VHV > VHV(start)) & (VCC > VCC(on)) Internal TSD 10 /C0109s timer Device stops, HV start−up current source stops (VHV > VHV(start)) & (VCC > VCC(on)) & TSDb Off mode VFB < VOFF 150 ms timer Device stops and internal VCC is turned off (VHV > VHV(start)) & (VCC > VCC(on)) & (VFB > VON)

Figure 71. Latched Timer−Based Overcurrent Protection (Options A/C)

Figure 72. Timer−Based Protection Mode with Autorecovery Release from Latch−off (Options B/D)

Figure 73. Latch Detection Schematic

http://onsemi.com Figure 74. Latch Timing Diagram status diagrams at the Figures 46 and 47. Ordering Part No. Overload Protection Switching Frequency Package Shipping† NCP1247AD065R2G Latched 65 kHz SOIC−7 (Pb−Free) 2500 / Tape & Reel NCP1247BD065R2G Autorecovery NPC1247CD065R2G Latched NCP1247DD065R2G Autorecovery NCP1247AD100R2G Latched 100 kHz SOIC−7 (Pb−Free) 2500 / Tape & Reel NCP1247BD100R2G Autorecovery NCP1247CD100R2G Latched NCP1247DD100R2G Autorecovery †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

http://onsemi.com PACKAGE DIMENSIONS SOIC−7 CASE 751U ISSUE E SEATING PLANE R J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. S DH C DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −A− −B− G MBM0.25 (0.010) −T− BM0.25 (0.010) T S A S M7 PL /C0095/C0095/C0095/C0095 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a numb er of patents, trademarks, reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 NCP1247/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative