NP5Q128A13ESFC0E NUMONYX | Alldatasheet
Document overview
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- PDF pages: 56
Technical content
Datasheet sections
- 1 Description
- 1.1 Introduction
- 1.2 Product Description
- 2 Signal descriptions
- 2.1 Serial data input (D/DQ0)
- 2.2 Serial data output (Q/DQ1)
- 2.3 Serial Clock (C)
- 2.4 Chip Select (S
- 2.5 Hold (HOLD /DQ3)
- 2.6 Write protect (W /DQ2)
- 2.7 V CC supply voltage
- 2.8 V SS ground
- 3 SPI modes
- 4 Operating features
- 4.1 Page programming
- 4.2 Dual input fast program
- 4.3 Quad input fast program
- 4.4 Sector erase and bulk erase
- 4.5 Polling during a write, program or erase cycle
- 4.6 Active power and standby power
- 4.7 Status register
- 4.8 Protection modes
- 4.8.1 Protocol-related protections
- 4.9 Hold condition
- 5 Memory organization
- 6 Instructions
- 6.1 Write enable (WREN)
Features
SPI bus compatible serial interface Maximum Clock Frequency – 66MHz (0 to +70 oC) – 33MHz (-30 to +85 oC) 2.7 V to 3.6 V single supply voltage Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol Quad I/O frequency of 50MHz, resulting in an equivalent clock frequency up to 200 MHz: Dual I/O frequency of 66MHz, resulting in an equivalent clock frequency up to 132 MHz: Continuous read of entire memory via single instruction: – Quad & Dual Output Fast Read – Quad & Dual Input Fast Program Uniform 128-Kbyte sectors (flash emulation) Write Operations – 128-Kbyte sectors erase (emulated) – Legacy Flash Page Program – Bit-alterable Page Writes – Page Program on all 1s (PreSet Writes) Write protections – Protected area size defined by four non- volatile bits (BP0, BP1, BP2, and BP3) Electronic signature – JEDEC standard two-byte signature (DA18h) Density and Packaging – 128 Mbit density with SOIC16 package More than 1,000,000 write cycles Phase Change Memory (PCM) – Chalcogenide phase change storage element – Bit alterable write operation SO16 (MF) 300 mils width www.numonyx.com
Numonyx® Omneo™ P5Q Datasheet Contents
Description Numonyx® Omneo™ P5Q Datasheet
1 Description
1.1 Introduction
Numonyx® Omneo™ Phase Change Memory for embedded applications offers all of the best attributes from other memory types in a new, highly scalable and flexible technology. Omneo™ P5Q PCM is a new type of nonvol atile semiconductor memory that stores information through a reversible structural phase change in a chalcogenide material. The material exhibits a change in material properties, both electrical and optical, when changed from the amorphous (disordered) to the polycrystalline (regularly ordered) state. In the case of Phase Change Memory, information is stored via the change in resistance the chalcogenide material experiences upon undergoing a phase change. The material also changes optical properties after experiencing a phase change, a characteristic that has been successfully mastered for use in current rewritable optical storage devices such as rewritable CDs and DVDs. The Omneo™ P5Q PCM storage elem ent consists of a thin film of chalcogenide contacted by a resistive heating element. In PCM, the phase change is induced in the memory cell by highly localized Joule heating caused by an induced current at the material junction. During a write operation, a small volume of the chalcogenide material is made to change phase. The phase change is a reversible process, and is modulated by the magnitude of injected current, the applied voltage, and the duration of the heating pulse. Omneo™ P5Q PCM combines the benefits of tr aditional floating gate flash, both NOR-type and NAND-type, with some of the key attributes of RAM and EEpROM. Like NOR flash and RAM technology, PCM offers fast random access times. Like NAND flash, PCM has the ability to write moderately fast. And like RAM and EEpROM, PCM supports bit alterable writes (overwrite). Unlike flash, no separate erase step is required to change information from 0 to 1 and 1 to 0. Unlike RAM, however, the technology is nonvolatile with data retention comparable NOR flash. However, at the current time, PCM technology appears to have a write cycling endurance better than that of NAND or NOR flash, but less than that of RAM. Unlike other proposed alternative memories, Omneo™ P5Q PCM technology uses a conventional CMOS process with the addition of a few additional layers to form the memory storage element. Overall, the basic memory manufacturing process used to make PCM is less complex than that of NAND, NOR or DRAM. Historically, systems have adopted many different types of memory to meet different needs within a design. Some systems might include boot memory, configuration memory, data storage memory, high speed execution memory, and dynamic working memory. The demands of many of today’s designs require better performance from the memory subsystem and a reduction in the overall component count. PCM provides many of the attributes of different kinds of memory found in a typical design, enabling the opportunity to consolidate or eliminate of different types of memory.
Numonyx® Omneo™ P5Q Datasheet Description
1.2 Product Description
The Omneo™ P5Q PCM s a 128-Mbit (16 Mb x 8) SPI phase change memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. Omneo™ P5Q PCM product supports four new, high-performance dual and quad input/output instructions: – Dual output fast read (DOFR) instruction used to read data at up to 66 MHz by using both DQ0 and DQ1 pins as outputs – Quad output fast read (QOFR) instruction used to read data at up to 50 MHz by using DQ0, DQ1, DQ2(W) and DQ3(HOLD) pins as outputs – Dual input fast program (DIFP) instruction used to program data at up to 66 MHz by using both DQ0 and DQ1 pins as inputs – Quad input fast program (QIFP) instructio n used to program data at up to 50 MHz by using DQ0, DQ1, DQ2(W) and DQ3(HOLD) pins as inputs These new instructions double or quadruple the transfer bandwidth for read and program operations. The memory can be programmed 1 to 64 bytes at a time, using the page program, dual input fast program and quad input fast program instructions. The memory is organized as 128 sectors that are further divided into 1,024 pages each (131,072 pages in total). For compatibility with flash memory devices, Omneo™ P5Q PCM supports sector erase (128-Kbyte sector) and bulk erase instructions. It can be write protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 128 Kbytes (sector granularity).
Figure 1. Logic diagram
- Serves as an input during Dual Input Fast Program (DIFP) and Quad Input Fast Program (QIFP)
Figure 2. SO16 connections
- DU = don’t use. User must float this pins.
- See Package mechanical section for package dimensions, and how to identify pin-1.
- For SO8 packing solutions please contact you local Numonyx field representative.
Signal descriptions Numonyx® Omneo™ P5Q Datasheet
2 Signal descriptions
2.1 Serial data input (D/DQ0)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). During the dual output fast read (DOFR) and quad output fast read (QOFR) instructions, this pin is used as an output (DQ0). Data is shifted out on the falling edge of the Serial Clock (C).
2.2 Serial data output (Q/DQ1)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). During the dual input fast program (DIFP) and quad input fast program (QIFP) instructions, this pin is used for data input (DQ1). It is latched on the rising edge of the Serial Clock (C). During the dual output fast read (DOFR) and quad output fast read (QOFR) instructions, this pin is used as data output (DQ1). Data is shifted out on the falling edge of Serial Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data on serial data output (DQ1) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S )
When this input signal is High, the device is deselected and serial data output (DQ1) is at high impedance. Unless an internal program, erase, or write status register cycle is in progress, the device will be in the standby power mode. Driving Chip Select (S ) Low enables the device, placing it in the active power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
Numonyx® Omneo™ P5Q Datasheet Signal descriptions
2.5 Hold (HOLD /DQ3)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the hold condition, the serial data output (DQ1) is high impedance, and serial data input (DQ0) and Serial Clock (C) are don’t care. To start the hold condition, the device must be selected, with Chip Select (S) driven Low. During the quad input fast program (QIFP) instruction, this pin is used for data input (DQ3). It is latched on the rising edge of the Serial Clock (C). During the quad output fast read (QOFR) instructions, this pin is used for data output (DQ3). Data is shifted out on the falling edge of Serial Clock (C).
2.6 Write protect (W /DQ2)
This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP3, BP2, BP1 and BP0 bits of the status register). During the quad input fast program (QIFP) instruction, this pin is used for data input (DQ2). It is latched on the rising edge of the Serial Clock (C). During the quad output fast read (QOFR) instructions, this pin is used for data output (DQ2). Data is shifted out on the falling edge of Serial Clock (C).
2.7 V CC supply voltage
VCC is the supply voltage.
2.8 V SS ground
VSS is the reference for the VCC supply voltage.
3 SPI modes
output data is available from the falling edge of Serial Clock (C). Figure 3. Bus master and memory devices on the SPI bus
- The Write Protect (W ) and Hold (HOLD) signals should be driven, High or Low as appropriate.
master leaves the SPI bus in high impedance. Figure 4. SPI modes supported
Operating features Numonyx® Omneo™ P5Q Datasheet
4 Operating features
Note: Definition of ‘Program’, ‘Bit-alt erable Write’ and ‘Program on All 1s’: – Program on Omneo™ P5Q PCM devices writes only 0s of the user data to the array and treats 1s as data masks. This is similar to programming on a floating gate flash device. – Bit-alterable Write on Omneo™ P5Q PCM devices involves writing both 0s and 1s of the user data to the array. – Program on all 1s is similar to ‘program’ where only 0s are written to the array and 1s are treated as data masks. Program on all 1s also requires that the entire page being written is previously set to all 1s. Program on all 1s is also referred to as PreSET Write.
4.1 Page programming
To program/write one data byte, two instructions are required: write enable (WREN), which is one byte, and a page program (PP) sequence, which consists of four bytes plus data byte. This is followed by the internal program cycle (of duration tPP). To spread this overhead, the page program (PP) instruction allows up to 64 bytes to be programmed/written at a time, provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Page program (PP) and Table 15: AC characteristics).
4.2 Dual input fast program
The dual input fast program (DIFP) instruction makes it possible to program/write up to 64 bytes using two input pins at the same time. For optimized timings, it is recommended to use the dual input fast program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather than using several dual input fast program (DIFP) sequences each containing only a few bytes (see Section 6.11: Dual input fast program (DIFP)).
4.3 Quad input fast program
The quad input fast program (QIFP) instruction makes it possible to program/write up to 64 bytes using four input pins at the same time. For optimized timings, it is recommended to use the quad input fast program (QIFP) instruction to program all consecutive targeted bytes in a single sequence rather than using several quad input fast program (QIFP) sequences each containing only a few bytes (see Section 6.12: Quad input fast program (QIFP)).
Numonyx® Omneo™ P5Q Datasheet Operating features
4.4 Sector erase and bulk erase
A sector can be erased to all 1s (FFh) at a time using the sector erase (SE) instruction. The entire memory can be erased using the bulk erase (BE) instruction. This starts an internal erase cycle (of duration tSE or tBE). The erase instruction must be preceded by a write enable (WREN) instruction.
4.5 Polling during a write, program or erase cycle
A further improvement in the time to write status register (WRSR), page program (PP), dual input fast program (DIFP), quad input fast program (QIFP), or erase (SE or BE) can be achieved by not waiting for the worst case delay (t W, tPP, tSMEN, tSMEX, tSE, or tBE). The write in progress (WIP) bit is provided in the status register so that the application program can monitor its value, polling it to establish when the previous write cycle, program cycle, or erase cycle is complete.
4.6 Active power and standby power
When Chip Select (S) is Low, the device is selected, and in the active power mode. When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). The device then goes in to the standby power mode. The device consumption drops to I CC1.
4.7 Status register
The status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.4: Read status register (RDSR) for a detailed description of the status register bits.
Operating features Numonyx® Omneo™ P5Q Datasheet
4.8 Protection modes
There are protocol-related and specific hardware and software protection modes. They are described below.
4.8.1 Protocol-rel ated protections
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the Omneo™ P5Q PCM features the follo wing data protection mechanisms: n Power on reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification n Program, erase, and write status register are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution n All instructions that modify data must be preceded by a write enable (WREN) instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state by the following events: – Power-up – Write disable (WRDI) instruction completion – Write status register (WRSR) instruction completion – Page program (PP) instruction completion – Dual input fast program (DIFP) instruction completion – Quad input fast program (QIFP) instruction completion – Sector erase (SE) instruction completion – Bulk erase (BE) instruction completion n The Block Protect bits (see Section 6.4.3: BP3, BP2, BP1, BP0 bits) and top/bottom bit (see Section 6.4.4: Top/bottom bit) allow part of the memory to be configured as read- only. This is the Software Protect Mode (SPM). n The Write Protect (W) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits, Top/Bottom (TB) bit and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). For more details, see Section 6.5: Write status register (WRSR).
Table 1. Protected area sizes
- The device is ready to accept a bulk erase instruction if, and only if, all block protect (BP3, BP2, BP1, BP0) are 0
4.9 Hold condition
write status register, program or erase cycle that is currently in progress. coincides with Serial Clock (C) being Low (as shown in Figure 5). coincides with Serial Clock (C) being Low. Low (this is shown in Figure 5). input (DQ0) and Serial Clock (C) are don’t care. from the moment of entering the hold condition. the device from going back to the hold condition. Figure 5. Hold condition activation
5 Memory organization
bulk erasable (bits are erased from ‘0’ to ‘1’). Table 2. Memory organization
127 FE0000 FFFFFF 102 CC0000 CDFFFF
126 FC0000 FDFFFF 101 CA0000 CBFFFF
125 FA0000 FBFFFF 100 C80000 C9FFFF
124 F80000 F9FFFF 99 C60000 C7FFFF
123 F60000 F7FFFF 98 C40000 C5FFFF
122 F40000 F5FFFF 97 C20000 C3FFFF
121 F20000 F3FFFF 96 C00000 C1FFFF
120 F00000 F1FFFF 95 BE0000 BFFFFF
119 EE0000 EFFFFF 94 BC0000 BDFFFF
118 EC0000 EDFFFF 93 BA0000 BBFFFF
117 EA0000 EBFFFF 92 B80000 B9FFFF
116 E80000 E9FFFF 91 B60000 B7FFFF
115 E60000 E7FFFF 90 B40000 B5FFFF
114 E40000 E5FFFF 89 B20000 B3FFFF
113 E20000 E3FFFF 88 B00000 B1FFFF
112 E00000 E1FFFF 87 AE0000 AFFFFF
111 DE0000 DFFFFF 86 AC0000 ADFFFF
110 DC0000 DDFFFF 85 AA0000 ABFFFF
109 DA0000 DBFFFF 84 A80000 A9FFFF
108 D80000 D9FFFF 83 A60000 A7FFFF
107 D60000 D7FFFF 82 A40000 A5FFFF
106 D40000 D5FFFF 81 A20000 A3FFFF
105 D20000 D3FFFF 80 A00000 A1FFFF
104 D00000 D1FFFF 79 9E0000 9FFFFF
103 CE0000 CFFFFF 78 9C0000 9DFFFF
Table 2. Memory organization (continued)
Table 3. Organization of Super Page regions
Instructions Numonyx® Omneo™ P5Q Datasheet
6 Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial data input DQ0 is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input DQ0, each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ), dual output fast read (DOFR), quad output fast read (QOFR), read status register (RDSR) or read identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a page program (PP), dual input fast program (DIFP), quad input fast program (QIFP), sector erase (SE), bulk erase (BE), write status register (WRSR), write enable (WREN), write disable (WRDI), Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a write status register cycle, program cycle erase cycle are ignored, and the internal write status register cycle, program cycle, erase cycle continues unaffected. Note: Output Hi-Z is defined as the point where data out is no longer driven.
Table 4. Instruction set
6.1 Write enable (WREN)
The write enable (WREN) instruction (Figure 6) sets the write enable latch (WEL) bit. instruction code, and then driving Chip Select (S) High. Figure 6. Write enable (WREN) instruction sequence
6.2 Write disable (WRDI)
The write disable (WRDI) instruction (Figure 7) resets the write enable latch (WEL) bit. instruction code, and then driving Chip Select (S) High. Figure 7. Write disable (WRDI) instruction sequence
6.3 Read identification (RDID)
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. not decoded, and has no effect on the cycle that is in progress. The instruction sequence is shown in Figure 8. any time during data output. Figure 8. Read identification (RDID) instruction sequence and data-out sequence Table 5. Read identification (RDID) data-out sequence
6.4 Read status register (RDSR)
read the status register continuously, as shown in Figure 9. register operation is in progress.
6.4.1 WIP bit
no such cycle is in progress.
6.4.2 WEL bit
reset and no write status register, program, erase instruction is accepted.
6.4.3 BP3, BP2, BP1, BP0 bits
protect (BP3, BP2, BP1, BP0) bits are 0. Table 6. Status register format
6.4.4 Top/bottom bit
from the bottom of the memory array (see Table 1: Protected area sizes).
6.4.5 SRWD bit
and the write status register (WRSR) instruction is no longer accepted for execution. Figure 9. Read status register (RDSR) instruction sequence and data-out sequence
6.5 Write status register (WRSR)
the device sets the write enable latch (WEL). followed by the instruction code and the data byte on serial data input (DQ0). The instruction sequence is shown in Figure 10. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. (S) is driven High, the self-timed write status register cycle (whose duration is tW) is initiated. completed, the write enable latch (WEL) is reset. progress; all other instructions are ignored. Figure 10. Write status register (WRSR) instruction sequence
The protection features of the device are summarized in Table 7. status register, are also hardware protected against data modification. Table 7. Protection modes
- As defined by the values in the bl ock protect (BP3, BP2, BP1, BP0) bits of the status register, as shown in
(BP3, BP2, BP1, BP0) bits of the status register, can be used.
6.6 Read data bytes (READ)
R, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 11. to be continued indefinitely. effects on the cycle that is in progress. Figure 11. Read data bytes (READ) instruction sequence and data-out sequence
6.7 Read data bytes at higher speed (FAST_READ)
C, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction. the read sequence to be continued indefinitely. is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read data bytes at higher speed (FAST_READ) instruction sequence
6.8 Dual output fast read (DOFR)
The instruction sequence is shown in Figure 13. memory can, therefore, be read with a single dual output fast read (DOFR) instruction. the read sequence can be continued indefinitely. Figure 13. Dual output fast read instruction sequence
6.9 Quad output fast read (QOFR)
speed (FAST_READ) instruction. during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. 00 0000h, so that the read sequence can be continued indefinitely. Figure 14. Quad output fast read instruction sequence
- After 40 clock cycles (cycle label ed 39 in the figured), data inputs (DQi) must be released because they
- Once 6Bh command is recognized, W and HOLD functionality is automatically disabled.
Numonyx® Omneo™ P5Q Datasheet Instructions
6.10 Page program (PP)
Note: This definition applies to all flavors of Pa ge Program: Legacy Program, Bit-alterable Write and Program on all 1s. The page program (PP) instruction allows bytes to be programmed/written in the memory. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (DQ0). If the 6 least significant address bits (A5-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 6 least significant bits (A5-A0) are all zero). Chip Select (S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. If more than 64 bytes are sent to the device, previously latched data are discarded and the last 64 data bytes are guaranteed to be programmed/written correctly within the same page. If less than 64 data bytes are sent to device, they are correctly programmed/written at the requested addresses without having any effects on the other bytes of the same page. (With Program on all 1s, the entire page should already have been set to all 1s (FFh).) For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Table 15: AC characteristics). Chip Select (S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the page program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the page program cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while a Page Program operation is in progress; all other instructions are ignored. A page program (PP) instruction applied to a page which is protected by the block protect (BP3, BP2, BP1, BP0) bits (see Table 1 and Table 2) is not executed.
Figure 15. Page program ( PP) instruction sequence
Numonyx® Omneo™ P5Q Datasheet Instructions
6.11 Dual input f ast program (DIFP)
Note: This definition applies to all flavors of Dual input fast program: Legacy Program, Bit- alterable Write and Program on all 1s. The dual input fast program (DIFP) instruction is very similar to the page program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the page program (PP) instruction. The dual input fast program (DIFP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (DQ0). If the 6 least significant address bits (A5-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 6 least significant bits (A5-A0) are all zero). Chip Select (S must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. If more than 64 bytes are sent to the device, previously latched data are discarded and the last 64 data bytes are guaranteed to be programmed/written correctly within the same page. If less than 64 data bytes are sent to device, they are correctly programmed/written at the requested addresses without having any effects on the other bytes in the same page. (With Program on all 1s, the entire page should already have been set to all 1s (FFh).) For optimized timings, it is recommended to use the dual input fast program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several dual input fast program (DIFP) sequences each containing only a few bytes (see Table 15: AC characteristics). Chip Select (S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the dual input fast program (DIFP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the dual input fast program (DIFP) cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while a dual input fast program operation is in progress; all other instructions are ignored. A dual input fast program (DIFP) instruction applied to a page that is protected by the block protect (BP3, BP2, BP1, BP0) bits (see Table 1) is not executed.
Figure 16. Dual input fast program (DIFP) instruction sequence
Numonyx® Omneo™ P5Q Datasheet Instructions
6.12 Quad input fast program (QIFP)
Note: The following description app lies to all flavors of Quad input fast program: Legacy Program, Bit-alterable Write and Program on all 1s. The quad input fast program (QIFP) instruction is very similar to the page program (PP) instruction, except that the data are entered on four pins (pin DQ0, DQ1, DQ2 and DQ3) instead of only one. Inputting the data on four pins instead of one quadruples the data transfer bandwidth compared to the page program (PP) instruction. The quad input fast program (QIFP) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (DQ0). If the 6 least significant address bits (A5-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 6 least significant bits (A5-A0) are all zero). Chip Select (S must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. If more than 64 bytes are sent to the device, previously latched data are discarded and the last 64 data bytes are guaranteed to be programmed correctly within the same page. If less than 64 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. (With Program on all 1s, the entire page should already have been set to all 1s (FFh).) For optimized timings, it is recommended to use the quad input fast program (QIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several quad input fast program (QIFP) sequences each containing only a few bytes (see Table 15: AC characteristics). Chip Select (S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the quad input fast program (QIFP) instruction is not executed As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the quad input fast program (DIFP) cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while a quad input fast program operation is in progress; all other instructions are ignored. A quad input fast program (QIFP) instruction applied to a page that is protected by the block protect (BP3, BP2, BP1, BP0) bits (see Table 1) is not executed
Figure 17. Quad input fast program (QIFP) instruction sequence
- Once 32h is recognized, W and HOLD functionality is automatically disabled.
6.13 Sector erase (SE)
can be accepted, a write enable (WREN) instruction must previously have been executed. must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 18. (BP3, BP2, BP1, BP0) bits (see Table 1 and Table 2) is not executed. Figure 18. Sector erase (SE) instruction sequence
6.14 Bulk erase (BE)
(WREN) instruction has been decoded, the device sets the write enable latch (WEL). The instruction sequence is shown in Figure 19. while device is busy with erase operation; all other instructions are ignored. bits are 0. The bulk erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 19. Bulk erase (BE) instruction sequence
Numonyx® Omneo™ P5Q Datasheet Power-up and power-down
7 Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC until VCC reaches the correct value: –V CC(min) at power-up, and then for a further delay of tVSL –V SS at power-down. A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power-up, a power on reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the power on reset (POR) threshold voltage, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all write enable (WREN), page program (PP), dual input fast program (DIFP), sector erase (SE), bulk erase (BE), write status register (WRSR) instructions until a time delay of t PUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No write status register, program, erase instructions should be sent until the later of: –t PUW after VCC has passed the VWI threshold –t VSL after VCC has passed the VCC(min) level. These values are specified in Table 8. If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected for read instructions even if the tPUW delay has not yet fully elapsed. After power-up, the device is in the following state: – The device is in the standby power mode – The write enable latch (WEL) bit is reset – The write in progress (WIP) bit is reset Normal precautions must be taken for supply line decoupling, to stabilize the V CC supply. Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nF). At power-down, when VCC drops from the operating voltage, to below the power on reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction (the designer needs to be aware that if power-down occurs while a write, program or erase cycle is in progress, some data corruption may result).
Figure 20. Power-up timing
8 Initial delivery state
contains FFh). The status register contains 00h (all status register bits are 0). Table 8. Power-up timing and V WI threshold
- These parameters are characterized only.
9 Maximum ratings
and other relevant quality documents. Table 9. Absolute maximum ratings
10 DC and AC parameters
match the measurement conditions when relying on the quoted parameters. “write cycle” is defined as any time a bit changes within a 32-byte page. Figure 21. AC measurement I/O waveform Table 10. Operating conditions Table 11. Endurance Specification
- In typical operation VPP program voltage is V PPL.
Table 12. AC measurement conditions
Table 13. Capacitance (1)
- Sampled only, not 100% tested, at T A=25 °C and a frequency of 33 MHz.
Table 14. DC characteristics
66 MHz, DQ1 = open 16 mA
33 MHz, DQ1 = open 7 mA
66 MHz, DQ0=DQ1 = open 20 mA
50 MHz,
Table 15. AC characteristics (1)
Figure 22. Serial input timing
- Typical values given for T A = 25° C @ nominal VCC.
- t CH + tCL must be greater than or equal to 1/ fC.
- Value guaranteed by characterization, not 100% tested in production.
- Expressed as a slew-rate.
- Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
- When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one
sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 64). Table 15. AC characteristics (1) (continued)
Figure 25. Output timing
conditions are also marked on the inner box label. Figure 26. SO16 wide - 16-lead plastic sm all outline, 300 mils body width, package Table 16. SO16 wide - 16-lead plastic small outline, 300 mils body width,
This section defines all active line items that can be ordered. Note: For SO8 packaging solutions please contact your local Numonyx representative for details. Table 17. Active Line Item Ordering Table
Table 18. Document revision history