NAND128-A STMICROELECTRONICS | Alldatasheet
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NAND128-A, NAND256-A NAND512-A, NAND01G-A
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)
528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories FEATURES SUMMARY ■ HIGH DENSITY NAND FLASH MEMORIES – Up to 1 Gbit memory array – Up to 32 Mbit spare area – Cost effective solutions for mass storage
applications
■ NAND INTERFACE – x8 or x16 bus width – Multiplexed Address/ Data – Pinout compatibility for all densities ■ SUPPLY VOLTAGE – 1.8V device: VDD = 1.7 to 1.95V – 3.0V device: VDD = 2.7 to 3.6V ■ PAGE SIZE – x8 device: (512 + 16 spare) Bytes – x16 device: (256 + 8 spare) Words ■ BLOCK SIZE – x8 device: (16K + 512 spare) Bytes – x16 device: (8K + 256 spare) Words ■ PAGE READ / PROGRAM – Random access: 12µs (max) – Sequential access: 50ns (min) – Page program time: 200µs (typ) ■ COPY BACK PROGRAM MODE – Fast page copy without external buffering ■ FAST BLOCK ERASE – Block erase time: 2ms (Typ) ■ STATUS REGISTER ■ ELECTRONIC SIGNATURE ■ CHIP ENABLE ‘DON’T CARE’ OPTION – Simple interface with microcontroller ■ SERIAL NUMBER OPTION ■ HARDWARE DATA PROTECTION – Program/Erase locked during Power transitions Figure 1. Packages
Table 1. Product List
NAND128-A, NAND256-A, NAND512-A, NAND01G-A SUMMARY DESCRIPTION The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page family. The de- vices range from 128Mbits to 1Gbit and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data In- put/Output signals on a multiplexed x8 or x16 In- put/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to imple- ment an Error Correction Code (ECC). A Write Protect pin is available to give a hardware protec- tion against program and erase operations. The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be pro- grammed in another page without having to re- send the data to be programmed. The devices are available in the following packag- es: ■ TSOP48 12 x 20mm for all products ■ USOP48 12 x 17 x 0.65mm for 128Mb, 256Mb and 512Mb products ■ VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array, 0.8mm pitch) for 128Mb and 256Mb products ■ TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for 512Mb Dual Die product ■ VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array, 0.8mm pitch) for the 512Mb product ■ TFBGA63 (9 x 11 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for the 1Gb Dual Die product Two options are available for the NAND Flash family: Chip Enable Don’t Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation. A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest ST Sales office. For information on how to order these options refer to Table 28., Ordering Information Scheme. De- vices are shipped from the factory with Block 0 al- ways valid and the memory content bits, in valid blocks, erased to ’1’. See Table 2., Product Description, for all the de- vices available in the family.
Table 2. Product Description Figure 2. Logic Diagram Table 3. Signal Names
1024 Blocks
2048 Blocks
4096 Blocks
8192 Blocks
Figure 3. Logic Block Diagram
Figure 6. FBGA55 Connections, x8 devices (Top view through package)
Figure 7. FBGA55 Connections, x16 devices (Top view through package)
Figure 8. FBGA63 Connections, x8 devices (Top view through package)
Figure 9. FBGA63 Connections, x16 devices (Top view through package)
where 16 cells are connected in series. into two areas, the main area and the spare area. during the lifetime of the device. Table 4. shows the minimum number of valid Table 4. Valid Blocks Figure 10. Memory Array Organization
512 Bytes
256 Words
NAND128-A, NAND256-A, NAND512-A, NAND01G-A SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, and Table 3., Signal Names, for a brief overview of the sig- nals connected to this device. Inputs/Outputs (I/O0-I/O7).Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/ O7 are left floating when the device is deselected or the outputs are disabled. Inputs/Outputs (I/O8-I/O15).Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data during a Read operation or input data during a Write operation. Command and Address Inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when the de- vice is deselected or the outputs are disabled. Address Latch Enable (AL).The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When AL is high, the inputs are latched on the rising edge of Write En- able. Command Latch Enable (CL).The Command Latch Enable activates the latching of the Com- mand inputs in the Command Interface. When CL is high, the inputs are latched on the rising edge of Write Enable. Chip Enable (E ).The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. When Chip Enable is low, VIL, the device is selected. While the device is busy programming or erasing, Chip Enable transitions to High, VIH, are ignored and the device does not revert to the Standby mode. While the device is busy reading: ■ the Chip Enable input should be held Low during the whole busy time (tBLBH1 ) for devices that do not present the Chip Enable Don’t Care option. Otherwise, the read operation in progress is interrupted and the device reverts to the Standby mode. ■ for devices that feature the Chip Enable Don't Care option, Chip Enable going High during the busy time (t BLBH1 ) will not interrupt the read operation and the device will not revert to the Standby mode. Read Enable (R).The Read Enable, R, controls the sequential data output during Read opera- tions. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one. Write Enable (W).The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write En- able. During power-up and power-down a recovery time of 1µs (min) is required before the Command Inter- face is ready to accept a command. It is recom- mended to keep Write Enable high during the recovery time. Write Protect (WP). The Write Protect pin is an input that gives a hardware protection against un- wanted program or erase operations. When Write Protect is Low, VIL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down. Ready/Busy (RB).The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R Controller is currently active. When Ready/Busy is Low, VOL , a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH . The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Refer to the Ready/Busy Signal Electrical Charac- teristics section for details on how to calculate the value of the pull-up resistor. V DD Supply Voltage.VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever VDD is below 2.5V (for 3V devices) or 1.5V (for 1.8V devices) to protect the device from any involuntary program/erase during power-tran- sitions. Each device in a system should have VDD decou- pled with a 0.1µF capacitor. The PCB track widths should be sufficient to carry the required program and erase currents VSS Ground. Ground, VSS, is the reference for the power supply. It must be connected to the sys- tem ground.
ing edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. to Tables 6 and 7, Address Insertion). Latch Enable is Low and Read Enable is High. tails of the timings requirements. Electronic Signature and the Serial Number. Command Latch Enable is Low. the memory against program or erase operations. are disabled and power consumption is reduced. Table 5. Bus Operations Note: 1. Only for x16 devices.
- WP must be VIH when issuing a program or erase command.
Table 6. Address Insertion, x8 Devices Note: 1. A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
- Any additional address input cycles will be ignored.
- The 4th cycle is only required for 512Mb and 1Gb devices.
Table 7. Address Insertion, x16 Devices Note: 1. A8 is Don’t Care in x16 devices.
- Any additional address input cycles will be ignored.
- The 01h Command is not used in x16 devices.
- The 4th cycle is only required for 512Mb and 1Gb devices.
Table 8. Address Definitions
imposed to maximize data security. Table 9. Commands Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.
- Any undefined command sequence will be ignored by the device.
lect the most significant column address). on the bus width of the device. main area) that is Words 0 to 255. gram command 80h is issued (see Figure 12.). Figure 11. Pointer Operations
Figure 12. Pointer Operations for Programming Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted. Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program. Only Areas C can be programmed. Subsequent 50h commands can be omitted.
NAND128-A, NAND256-A, NAND512-A, NAND01G-A Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section. Once the area (main or spare) has been selected using the Read A, Read B or Read C commands four bus cycles (for 512Mb and 1Gb devices) or three bus cycles (for 128Mb and 256Mb devices) are required to input the ad- dress (refer to Table 6.) of the data to be read. The device defaults to Read A mode after power- up or a Reset operation. When reading the spare area addresses: ■ A0 to A3 (x8 devices) ■ A0 to A2 (x16 devices) are used to set the start address of the spare area while addresses: ■ A4 to A7 (x8 devices) ■ A3 to A7 (x16 devices) are ignored. Once the Read A or Read C commands have been issued they do not need to be reissued for subsequent read operations as the pointer re- mains in the respective area. However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A and so another Read B command is required to start an- other read operation in Area B. Once a read command is issued three types of op- erations are available: Random Read, Page Read and Sequential Row Read. Random Read. Each time the command is is- sued the first read is Random Read. Page Read. After the Random Read access the page data is transferred to the Page Buffer in a time of tWHBH (refer to Table 21. for value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequen- tially (from selected column address to last column address) by pulsing the Read Enable signal. Sequential Row Read.After the data in last col- umn of the page is output, if the Read Enable sig- nal is pulsed and Chip Enable remains Low then the next page is automatically loaded into the Page Buffer and the read operation continues. A Sequential Row Read operation can only be used to read within a block. If the block changes a new read command must be issued. Refer to Figure 15. and Figure 16. for details of Se- quential Row Read operations. To terminate a Sequential Row Read operation set the Chip Enable signal to High for more than tEHEL . Sequential Row Read is not available when the Chip Enable Don't Care option is enabled.
ation to program data to the memory array. 528) or words (1 to 264) can be programmed. operations can take place in that page. tions section and Figure 12. for details.
- one bus cycle is required to setup the Page
- four bus cycles are then required to input the
- the data is then input (up to 528 Bytes/ 264
- one bus cycle is required to issue the confirm
command to start the P/E/R Controller.
- The P/E/R Controller then programs the data
ed, all other commands will be ignored. Figure 17. Page Program Operation Note: Before starting a Page Program operation a Pointer operation can be performed. Refer to Pointer Operations section for details.
to the newly assigned block.
- The source page must be read using the Read
- When the device returns to the ready state
same for the Source and Target pages.
- Then the confirm command is issued to start
til the block has been erased. Table 10. Copy Back Program Addresses Figure 18. Copy Back Operation
128 Mbit A23
256 Mbit A24
512 Mbit A25
512 Mbit DD
1 Gbit DD(1) A25, A26
NAND128-A, NAND256-A, NAND512-A, NAND01G-A Read Status Register The device contains a Status Register which pro- vides information on the current or previous Pro- gram or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register in- formation is present on the output data bus (I/O0- I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read En- able signals to update the contents of the Status Register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore if a Read Status Register command is issued during a Random Read cycle a new read command must be issued to continue with a Page Read or Sequential Row Read operation. The Status Register bits are summarized in Table 11., Status Register Bits. Refer to Table 11. in conjunction with the following text descriptions. Write Protection Bit (SR7).The Write Protection bit can be used to identify if the device is protected or not. If the Write Protection bit is set to ‘1’ the de- vice is not protected and program or erase opera- tions are allowed. If the Write Protection bit is set to ‘0’ the device is protected and program or erase operations are not allowed. P/E/R Controller Bit (SR6).The Program/Erase/ Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive (device is ready). Error Bit (SR0).The Error bit is used to identify if any errors have been detected by the P/E/R Con- troller. The Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to ‘0’ the oper- ation has completed successfully. SR5, SR4, SR3, SR2 and SR1 are Reserved.
Table 11. Status Register Bits
- first use one Bus Write cycle to issue the Read
- then perform two Bus Read operations – the
Table 12. Electronic Signature
source line by a select transistor. the 1st page does not contain FFh is a Bad Block. table following the flowchart shown in Figure 20. be replaced by copying the data to a valid block. copy the data to a valid block. Table 13. Block Failure Figure 20. Bad Block Management Flowchart
NAND128-A, NAND256-A, NAND512-A, NAND01G-A Hardware Simulation Models Behavioral simulation models.Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hard- ware. IBIS simulations models.IBIS (I/O Buffer Infor- mation Specification) models describe the behav- ior of the I/O buffers and electrical characteristics of Flash devices. These models provide information such as AC characteristics, rise/fall times and package me- chanical data, all of which are measured or simu- lated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connec- tions and can be used to resolve compatibility is- sues when upgrading devices. They can be imported into SPICETOOLS.
Table 14. Program, Erase Times and Program Erase Endurance Cycles Table 15. Absolute Maximum Ratings shoot to VDD + 2V for less than 20ns during transitions on I/O pins.
16., Operating and AC Measurement Conditions. tions when relying on the quoted parameters. Table 16. Operating and AC Measurement Conditions Table 17. Capacitance Note: TA = 25°C, f = 1 MHz. CIN and CI/O are not 100% tested.
Table 18. DC Characteristics, 1.8V Devices
Table 19. DC Characteristics, 3V Devices
Table 20. AC Characteristics for Command, Address, Data Input Note: 1. If tELWL is less than 10ns, tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns.
Table 21. AC Characteristics for Operations Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 34, 35 and 36.
- To break the sequential read cycle, E must be held High for longer than tEHEL .
- ES = Electronic Signature.
Figure 29. Page Read A/ Read B Operation AC Waveform Note: Address cycle 4 is only required for 512Mb and 1Gb devices.
Figure 30. Read C Operation, One Page AC Waveform Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’.
Figure 31. Page Program AC Waveform Note: Address cycle 4 is only required for 512Mb and 1Gb devices.
Figure 37. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline Note: Drawing is not to scale. Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Figure 38. USOP48 – lead Plastic Ultra Thin Small Outline,12 x 17mm, Package Outline Table 23. USOP48 – lead Plastic Ultra Thin Small Outline, 12 x 17mm, Package Mechanical Data
Figure 39. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline Table 24. VFBGA55 8 x 10mm - 6x8 ball array, 0.80mm pitch, Package Mechanical Data
Figure 40. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data
Figure 41. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline Note: Drawing is not to scale. Table 26. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
Figure 42. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline Table 27. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
Table 28. Ordering Information Scheme Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest ST Sales Office.
NAND128-A, NAND256-A, NAND512-A, NAND01G-A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America