NAND256-M STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Summary description
  • 2 Maximum rating
  • 3 Package Mechanical
  • 4 Part Numbering
  • 5 Revision history

Features

■ Multi-Chip Packages – 1 die of 256 Mb, 512 Mb (x8/ x16) NAND Flash + 1 die of 256 Mb (x16) SDR LPSDRAM – 1 die of 256 Mb, 512 Mb (x8/ x16) NAND Flash + 2 dice of 256 Mb (x16) SDR LPSDRAMs – 1 die of 256 Mb, 512 Mb (x8/ x16) NAND Flash +1 die of 256 Mb (x16) DDR LPSDRAM – 1 die of 512 Mb (x16) NAND Flash + 1 die of 256 Mb or 512 Mb (x16) DDR LPSDRAM ■ Supply voltages –V DDF = 1.7V to 1.95V or 2.5V to 3.6V –V DDD = VDDQD = 1.7V to 1.9V ■ Electronic Signature ■ ECOPACK ® packages ■ Temperature range – -30 to 85°C Flash Memory ■ NAND Interface – x8 or x16 bus width – Multiplexed Address/ Data ■ Page size – x8 device: (512 + 16 spare) Bytes – x16 device: (256 + 8 spare) Words ■ Block size – x8 device: (16K + 512 spare) Bytes – x16 device: (8K + 256 spare) Words ■ Page Read/Program – Random access: 15µs (max) – Sequential access: 50ns (min) – Page program time: 200µs (typ) ■ Copy Back Program mode – Fast page copy without external buffering ■ Fast Block Erase – Block erase time: 2ms (typ) ■ Status Register ■ Data integrity – 100,000 Program/Erase cycles – 10 years Data Retention LPSDRAM ■ Interface: x16 or x 32 bus width ■ Deep Power Down mode ■ 1.8v LVCMOS interface ■ Quad internal Banks controlled by BA0 and BA1 ■ Automatic and controlled Precharge ■ Auto Refresh and Self Refresh – 8,192 Refresh cycles/64ms – Programmable Partial Array Self Refresh – Auto Temperature Compensated Self Refresh ■ Wrap sequence: sequential/interleave ■ Burst Termination by Burst Stop command and Precharge command TFBGA107 10.5 x 13 x 1.2mm TFBGA149 10 x 13.5 x 1.2mm LFBGA137 10.5 x 13 x 1.4mm TFBGA137 10.5 x 13 x 1.2 mm(1) FBGA (1) Preliminary specifications.

Table 1. Product List

Summary description NAND2 56-M, NAND512-M, NAND01G-M

1 Summary description

The NAND256-M, NAND512-M and NAND01G-M are Multi-Chip Packages which combine up to 512 Mbit LPSDRAM with a 256 Mbit, 512 Mbit or 1 Gbit NAND Flash memory. This combination of LPSDRAM and NAND Flash can result in up to 1 Gbit of memory. The NAND Flash memory and LPSDRAM components have separate power supplies and grounds. They also have separate control, address and input/output signals, which allows simultaneous access to both devices at any moment. They are distinguished by two chip enable inputs: E F for the NAND Flash memory and ED for the LPSDRAM. See Figure 1: Logic Diagram: NAND Flash & 1 x SDR LPSDRAM and Table 2: Signal Names: NAND Flash & 1 x SDR LPSDRAM for an overview of the signals attached to each component. The NAND256-M, NAND512-M and NAND01G-M are available with a 1.8 or 3V voltage supply. See Table 1: Product List for a complete list of the products available. The devices are offered in the following Multi-Chip packages:

  • TFBGA107 (10.5 x 13 x 1.2mm)
  • LFBGA137 (10.5 x 13 x 1.4mm)
  • TFBGA149 (10 x 13.5 x 1.2mm)
  • TFBGA137 (10.5 x 13 x 1.2mm) In order to meet environmental requirements, ST offers the NAND256-M, NAND512-M and NAND01G-M devices in ECOPACK® package. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. The memories are supplied with all the NAND Flash memory bits erased (set to ‘1’). This datasheet should be read in conjunction with the NAND Flash and LPSDRAM datasheets. NAND Flash Component The NAND256-M, NAND512-M and NAND01G-M devices contain a 1.8V, 256 Mbit or 512 Mbit, x8 528 Byte Page or x16 264 Word Page, NAND Flash memory with the Chip Enable Don’t Care option. For detailed information on how to use the devices, see the NANDxxx-A and NAND01GWxA2B-KGD datasheets.
  • one M65KA256AL: 256Mbit (x16) Single Data Rate (SDR) LPSDRAM
  • two M65KA256AL: 256Mbit (x16) Single Data Rate (SDR) LPSDRAMs (SDR0 and SDR 1)
  • one M65KG256AF: 256Mbit (x16) Double Data Rate (DDR) LPSDRAM
  • one M65KG512AB: 512Mbit (x16) Double Data Rate (DDR) LPSDRAM
  • one M65KC512AB: 512Mbit (x32) Single Data Rate (SDR) LPSDRAM Refer to Table 1: Product List, for a description of the memories contained in the NAND256- M, NAND256-M and NAND01G-M devices. For detailed information on how to use the SDR LPSDRAM devices, refer to the M65KA256AL and M65KC512AB datasheets which are available from your local STMicroelectronics distributor. For detailed information on how to use the DDR LPSDRAM device, refer to the M65KG256AB datasheet which is available from your local STMicroelectronics distributor.

Figure 1. Logic Diagram: NAND Flash & 1 x SDR LPSDRAM

Table 2. Signal Names: NAND Flash & 1 x SDR LPSDRAM

Figure 2. Logic Diagram: NAND Flash & 2 x SDR LPSDRAMs

Table 3. Signal Names: NAND Flash & 2 x SDR LPSDRAMs

Figure 3. Logic Diagram: NAND Flash & DDR LPSDRAM

Table 4. Signal Names - NAND Flash & DDR LPSDRAM A10 determines the Precharge mode.

Figure 4. TFBGA107 Connections (Top view through package)

Figure 5. TFBGA149 Connections (Top view through package)

  1. Balls shaded in gray are only present for NAND + DDR devices delivered in the TFBGA149 package.

Figure 6. LFBGA137 and TFBGA137 Connections (Top view through package)

2 Maximum rating

Program and other relevant quality documents. Table 5. Absolute Maximum Ratings

  1. TBD stands for To Be Defined.
  2. Minimum Voltage may undershoot to -2V for less than 20ns during transitions on input and I/O pins.

Maximum voltage may overshoot to VDD + 2V for less than 20ns during transitions on I/O pins.

3 Package Mechanical

Figure 7. TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, Bottom Outline Table 6. TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, Mechanical Data

Figure 8. TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, Bottom Outline Table 7. TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, Mechanical Data

Figure 9. LFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Bottom Outline

  1. Subject to change without prior notice.

Table 8. LFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Mechanical Data(1)

  1. Subject to change without prior notice.

Figure 10. TFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Bottom Outline

  1. Subject to change without prior notice.

Table 9. TFBGA137 10.5x13mm - 10x13 active ball array, 0.80mm pitch

4 Part Numbering

Table 10. Ordering Information Scheme

5 Revision history

Table 11. Document Revision History 06-Feb-2006 1.0 First Issue. 09-Feb-2006 2.0 Reference M65KG256AD changed to M65KG256AB. Temperature range -25 to 85°C removed for 512 Mbit LPSDRAMs. NAND512W3M2 part number added in Table 1: Product List. Figure 5: TFBGA149 Connections (Top view through package) updated. LPSDRAM supply voltage changed to 1.7 to 1.9V. 133MHz LPSDRAM added for NAND01GW3M2.