NAND01G-B2B NUMONYX | Alldatasheet
Document overview
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- PDF pages: 60
Technical content
Datasheet sections
- 1 Description
- 2 Memory array organization
- 2.1 Bad blocks
- 3 Signals description
- 3.1 Inputs/outputs (I/O0-I/O7)
- 3.2 Inputs/outputs (I/O8-I/O15)
- 3.3 Address Latch Enable (AL)
- 3.4 Command Latch Enable (CL)
- 3.5 Chip Enable (E
- 3.6 Read Enable (R )
- 3.7 Write Enable (W )
- 3.8 Write Protect (WP )
- 3.9 Ready/Busy (RB )
- 3.10 V DD supply voltage
- 3.11 V SS ground
- 4 Bus operations
- 4.1 Command input
- 4.2 Address input
- 4.3 Data input
- 4.4 Data output
- 4.5 Write Protect
- 4.6 Standby
- 5 Command set
- 6 Device operations
- 6.1 Read memory array
- 6.1.1 Random read
- 6.1.2 Page read
Datasheet sections
- 12 Package mechanical
- 13 Ordering information
- 14 Revision history
Features
■ High density NAND flash memories – Up to 2 Gbits of memory array – Cost effective solutions for mass storage
applications
■ NAND interface – x8 or x16 bus width – Multiplexed address/ data – Pinout compatibility for all densities ■ Supply voltage: 1.8 V/3.0 V ■ Page size – x8 device: (2048 + 64 spare) bytes – x16 device: (1024 + 32 spare) words ■ Block size – x8 device: (128 K + 4 K spare) bytes – x16 device: (64 K + 2 K spare) words ■ Page read/program – Random access: 25 µs (max) – Sequential access: 30 ns (min) – Page program time: 200 µs (typ) ■ Copy back program mode ■ Cache program and cache read modes ■ Fast block erase: 2 ms (typ) ■ Status register ■ Electronic signature ■ Chip enable ‘don’t care’ ■ Serial number option ■ Data protection – Hardware block locking – Hardware program/erase locked during power transitions ■ Data integrity – 100 000 program/erase cycles per block (with ECC) – 10 years data retention ■ ECOPACK® packages ■ Development tools – Error correction code models – Bad blocks management and wear leveling algorithms – Hardware simulation models FBGA TSOP48 12 x 20 mm VFBGA63 9.5 x 12 x 1 mm VFBGA63 9 x 11 x 1 mm Table 1. Device summary
- x16 organization only available for MCP products.
NAND01G-B2B, NAND02G-B2C Contents
Table 28. VFBGA63 9 x 11 mm - 6 x 8 active ball array, 0.80 mm pitch, package mechanical data . 57
NAND01G-B2B, NAND02G-B2C Description
1 Description
NAND01G-B2B and NAND02G-B2C flash 2112-byte/1056-word page is a family of non- volatile flash memories that uses NAND cell technology. The devices range from 1 Gbit to 2 Gbits and operate with either a 1.8 V or 3 V voltage supply. The size of a page is either 2112 bytes (2048 + 64 spare) or 1056 words (1024 + 32 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 100 000 cycles (with ECC on). To extend the lifetime of NAND flash devices it is strongly recommended to implement an error correction code (ECC). The devices feature a write protect pin that allows performing hardware protection against program and erase operations. The devices feature an open-drain ready/busy output that can be used to identify if the program/erase/read (P/E/R) controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. A Copy Back Program command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. Each device has cache program and cache read features which improve the program and read throughputs for large files. During cache programming, the device loads the data in a cache register while the previous data is transferred to the page buffer and programmed into the memory array. During cache reading, the device loads the data in a cache register while the previous data is transferred to the I/O buffers to be read. All devices have the chip enable don’t care feature, which allows code to be directly downloaded by a microcontroller, as chip enable transitions during the latency time do not stop the read operation. All devices have the option of a unique identifier (serial number), which allows each device to be uniquely identified. The unique identifier options is subject to an NDA (non disclosure agreement) and so not described in the datasheet. For more details of this option contact your nearest Numonyx sales office. The devices are available in the following packages:
- TSOP48 (12 x 20 mm)
- VFBGA63 (9.5 x 12 x 1 mm, 0.8 mm pitch) for NAND02G-B2C devices
- VFBGA63 (9 x 11 x 1 mm, 0.8 mm pitch) for NAND01G-B2B devices. For information on how to order these options refer to Table 29: Ordering information scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table 2: Product description, for all the devices available in the family.
Figure 1. Logic block diagram Table 2. Product description
1.95 V 25 µs 50 ns
3.6 V 25 µs 30 ns TSOP48
1.95 V 25 µs 50 ns (1)
3.6 V 25 µs 30 ns (1)
- x16 organization only available for MCP.
Figure 2. Logic diagram
- x16 organization only available for MCP.
Table 3. Signal names
Figure 3. TSOP48 connections
- Available only for NAND01GW3B2 B and NAND02GW3B2C 8-bit devices.
Figure 4. VFBGA63 connections (top view through package)
- Available only for NAND01GR3B2B and NAND02GR3B2C 8-bit devices.
2 Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series. flags or bad block identification. the x16 devices the pages are split into a 1,024-word main area and a 32-word spare area. Refer to Figure 5: Memory array organization.
2.1 Bad blocks
blocks may develop during the lifetime of the device. management for more details). blocks that could develop later on. error correction codes (refer to Section 8: Software algorithms). Table 4. Valid blocks
2 Gbits 2008 2048
1 Gbit 1004 1024
Figure 5. Memory array organization
Signals description NAND 01G-B2B, NAND02G-B2C
3 Signals description
See Figure 2: Logic diagram, and Table 3: Signal names, for a brief overview of the signals connected to this device.
3.1 Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a read operation or input a command or data during a write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled.
3.2 Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They are used to output the data during a read operation or input data during a write operation. Command and address Inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when the device is deselected or the outputs are disabled.
3.3 Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.4 Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.5 Chip Enable (E )
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, V IL, the device is selected. If Chip Enable goes High, vIH, while the device is busy, the device remains selected and does not go into standby mode.
3.6 Read Enable (R )
The Read Enable pin, R, controls the sequential data output during read operations. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one.
NAND01G-B2B, NAND02G-B2C Signals description
3.7 Write Enable (W )
The Write Enable input, W, controls writing to the command interface, input address and data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 10 µs (min) is required before the command interface is ready to accept a command. It is recommended to keep Write Enable High during the recovery time.
3.8 Write Protect (WP )
The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, V IL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.9 Ready/Busy (RB )
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Refer to the Section 11.1: Ready/Busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor. During power-up and power-down a minimum recovery time of 10 µs is required before the command interface is ready to accept a command. During this period the RB signal is Low, VOL.
3.10 V DD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever VDD is below VLKO (see Table 22 and Table 23) to protect the device from any involuntary program/erase during power-transitions. Each device in a system should have VDD decoupled with a 0.1 µF capacitor. The PCB track widths should be sufficient to carry the required program and erase currents.
3.11 V SS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system ground.
Bus operations NAND01G-B2B, NAND02G-B2C
4 Bus operations
There are six standard bus operations that control the memory. Each of these is described in this section, see Table 5: Bus operations, for a summary. Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations.
4.1 Command input
Command input bus operations are used to give commands to the memory. Commands are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure 19 and Table 24 for details of the timings requirements.
4.2 Address input
Address input bus operations are used to input the memory addresses. Four bus cycles are required to input the addresses for 1-Gbit devices whereas five bus cycles are required for the 2-Gbit device (refer to Table 6 and Table 7, Address insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure 20 and Table 24 for details of the timings requirements.
4.3 Data input
Data input bus operations are used to input the data to be programmed. Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 21 and Table 24 and Table 25 for details of the timings requirements.
4.4 Data output
Data output bus operations are used to read: the data in the memory array, the status register, the lock status, the electronic signature and the unique identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure 22 and Table 25 for details of the timings requirements.
4.5 Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6 Standby
outputs are disabled and power consumption is reduced. Table 5. Bus operations
- WP must be VIH when issuing a program or erase command.
Table 6. Address insertion, x8 devices
- Any additional address input cycles will be ignored.
- The fifth cycle is valid for 2-Gbit dev ices. A28 is for 2-Gbit devices only.
Table 7. Address insertion, x16 devices
- Any additional address input cycles will be ignored.
- The fifth cycle is valid for 2-Gbit devices. A27 is for 2-Gbit devices only.
Table 8. Address definitions, x8 Table 9. Address definitions, x16
5 Command set
program and erase operations are imposed to maximize data security. The commands are summarized in Table 10: Commands. Table 10. Commands
- The bus cycles are only shown for issuing t he codes. The cycles required to input the
addresses or input/output data are not shown.
- Only during Cache Read busy.
Device operations NAND 01G-B2B, NAND02G-B2C
6 Device operations
The following section gives the details of the device operations.
6.1 Read memory array
At power-up the device defaults to read mode. To enter read mode from another mode the Read command must be issued, see Table 10: Commands. Once a Read command is issued two types of operations are available: random read and page read.
6.1.1 Random read
Each time the Read command is issued the first read is random read.
6.1.2 Page read
After the first random read access, the page data (2112 bytes or 1056 words) is transferred to the page buffer in a time of t WHBH (refer to Table 25 for value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. The device can output random data in a page, instead of the consecutive sequential data, by issuing a Random Data Output command. The Random Data Output command can be used to skip some data during a sequential data output. The sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the Random Data Output command. The Random Data Output command can be issued as many times as required within a page. The Random Data Output command is not accepted during cache read operations.
Figure 6. Read operations
- Highest address depends on device density.
Figure 7. Random data output during sequential data output
5 Add cycles
6.2 Cache read
the next page into the cache register.
- One bus cycle is required to setup the Cache Read command (the same as the
- Four or five (refer to Table 6 and Table 7) bus cycles are then required to input the start
- One bus cycle is required to issue the Cache Read Confirm command to start the
the device is internally downloading page n+1. pages n and n+1 will not be output. Figure 8. Cache read operation
Device operations NAND 01G-B2B, NAND02G-B2C
6.3 Page program
The page program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however the device does support random input within a page. It is recommended to address pages sequentially within a given block. The memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed. The maximum number of consecutive partial page program operations allowed in the same page is four. After exceeding this a Block Erase command must be issued before any further program operations can take place in that page.
6.3.1 Sequential input
To input data sequentially the addresses must be sequential and remain in one block. For sequential input each page program operation consists of five steps (see Figure 9): 1. one bus cycle is required to setup the Page Program (sequential input) command (see Table 10) 2. four or five bus cycles are then required to input the program address (refer to Table 6 and Table 7) 3. the data is then loaded into the data registers 4. one bus cycle is required to issue the Page Program Confirm command to start the P/E/R controller. The P/E/R will only start if the data has been loaded in step 3 5. the P/E/R controller then programs the data into the array.
6.3.2 Random data input in a page
During a sequential input operation, the next sequential address to be programmed can be replaced by a random address, by issuing a Random Data Input command. The following two steps are required to issue the command: 1. one bus cycle is required to setup the Random Data Input command (see Table 10) 2. two bus cycles are then required to input the new column address (refer to Table 6). Random Data Input can be repeated as often as required in any given page. Once the program operation has started the status register can be read using the Read Status Register command. During program operations the status register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High. The device remains in read status register mode until another valid command is written to the command interface.
Figure 9. Page program operation Figure 10. Random data input during sequential data input
6.4 Copy back program
reprogram it in another page. needs to be copied to the newly assigned block.
- The first step reads the source page. The operation copies all 1056 words/ 2112 bytes
- When the device returns to the ready state (Ready/Busy High), the next bus write cycle
- Then the confirm command is issued to start the P/E/R controller.
program operation refer to Figure 11. Table 11. Copy back program x8 addresses
1 Gbit no constraint
2 Gbits A28
Table 12. Copy back program x16 addresses
2 Gbits A27
6.5 Cache program
was transferred to the page buffer is programmed into the memory array.
- First of all the program setup command is issued: one bus cycle to issue the program
- One bus cycle is required to issue the confirm command to start the P/E/R controller
- The P/E/R controller then transfers the data to the page buffer. During this the device is
- Once the data is loaded into the page buffer the P/E/R controller programs the data into
to ‘1', while if the error has been detected on page N the error bit SR0 will be set to '1’. last page of data must be programmed with the Page Program Confirm command (10h). be polled to find out if the last programming is finished before starting any other operations. Figure 13. Cache program operation
- Up to 64 pages can be programm ed in one cache program operation.
- t CACHEPG is the program time for the last page + the program time for the (last − 1)th page − (Program command cycle time
+ Last page data loading time).
6.6 Block erase
addressed block to ‘1’. All previous data in the block is lost.
- One bus cycle is required to setup the Block Erase command. Only addresses A18-
- Two or three bus cycles are th en required to load the address of the block to be erased.
- One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
is issued. The P/E/R controller handles block erase and implements the verify process. be accepted, all other commands will be ignored. SR0 is ‘0’, otherwise it is set to ‘1’. Figure 14. Block erase operation
6.7 Reset
modified will no longer be valid as the data will be partially programmed or erased. If the device has already been reset then the new Reset command will not be accepted. issued, refer to Table 25: AC characteristics for operations for the values.
Device operations NAND 01G-B2B, NAND02G-B2C
6.8 Read status register
The device contains a status register which provides information on the current or previous program or erase operation. The various bits in the status register convey information and errors on the operation. The status register is read by issuing the Read Status Register command. The status register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the status register. After the Read Status Register command has been issued, the device remains in read status register mode until another command is issued. Therefore if a Read Status Register command is issued during a random read cycle a new Read command must be issued to continue with a page read operation. The Status Register bits are summarized in Table 13: Status register bits,. Refer to Table 13 in conjunction with the following text descriptions.
6.8.1 Write protection bit (SR7)
The write protection bit can be used to identify if the device is protected or not. If the write protection bit is set to ‘1’ the device is not protected and program or erase operations are allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase operations are not allowed.
6.8.2 P/E/R controller and cac he ready/busy bit (SR6)
Status register bit SR6 has two different functions depending on the current operation. During cache program operations SR6 acts as a cache program ready/busy bit, which indicates whether the cache register is ready to accept new data. When SR6 is set to '0', the cache register is busy and when SR6 is set to '1', the cache register is ready to accept new data. During all other operations SR6 acts as a P/E/R controller bit, which indicates whether the P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
6.8.3 P/E/R contro ller bit (SR5)
The program/erase/read controller bit indicates whether the P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
6.8.4 Cache program error bit (SR1)
SR1 is set to ‘0’ the operation has completed successfully. operations it is don’t care.
6.8.5 Error bit (SR0)
bit SR0, in a cache program operation, indicates a failure on page N.
6.8.6 SR4, SR3 and SR2 are reserved
Table 13. Status register bits
- Only valid for cache program operations, for other operations it is same as SR6.
- Only valid for cache operations, fo r other operations it is don’t care.
6.9 Read electronic signature
- One bus write cycle to issue the Read Electronic Signature command (90h)
- One bus write cycle to input the address (00h)
- Four bus read cycles to sequentially output the data (as shown in Table 14: Electronic
Table 14. Electronic signature Table 15. Electronic signature byte 3
Table 16. Electronic signature byte/word 4
64 Kbytes
128 Kbytes
256 Kbytes
Data protection NAND01G-B2B, NAND02G-B2C
7 Data protection
The device has hardware features to protect against program and erase operations. It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations. It is recommended to keep WP at VIL during power-up and power- down. In addition, to protect the memory from any involuntary program/erase operations during power-transitions, the device has an internal voltage detector which disables all functions whenever VDD is below VLKO (see Table 22 and Table 23).
NAND01G-B2B, NAND02G-B2C Software algorithms
8 Software algorithms
This section gives information on the software algorithms that Numonyx recommends to implement to manage the bad blocks and extend the lifetime of the NAND device. NAND flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. For this reason, the number of program and erase cycles is limited (see Table 18 for value) and it is recommended to implement garbage collection, a wear-leveling algorithm and an error correction code, to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application, Numonyx can provide a file system OS native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details.
8.1 Bad block management
Devices with bad blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The bad block information is written prior to shipping. Any block, where the 1st and 6th bytes, or 1st word, in the spare area of the 1st page, does not contain FFh, is a bad block. The bad block Information must be read before any erase is attempted as the bad block information may be erased. For the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in Figure 15.
8.2 NAND flash memory failure modes
Over the lifetime of the device additional bad blocks may develop. To implement a highly reliable system, all the possible failure modes must be considered:
- Program/erase failure: in this case the block has to be replaced by copying the data to a valid block. These additional bad blocks can be identified as attempts to program or erase them will give errors in the status register As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See Section 6.4: Copy back program for more details
- Read failure: in this case, ECC correction must be implemented. To efficiently use the memory space, it is recommended to recover single-bit error in read by ECC, without replacing the whole block. Refer to Table 17 for the procedure to follow if an error occurs during an operation.
NAND01G-B2B, NAND02G-B2C Software algorithms
8.3 Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a garbage collection algorithm. In a garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 16).
8.4 Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. In memories that do not use a wear-leveling algorithm not all blocks get used at the same rate. Blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. The wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels:
- First level wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles
- Second level wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently-changed data. The second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold.
8.5 Error correction code
An error correction code (ECC) can be implemented in the NAND flash memories to identify and correct errors in the data. For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for line parity plus 6 bits for column parity). An ECC model is available in VHDL or Verilog. Contact the nearest Numonyx sales office for more details.
Figure 17. Error detection
8.6 Hardware simulation models
8.6.1 Behavioral simulation models
software to be developed before hardware.
8.6.2 IBIS simulations models
and electrical characteristics of flash devices. wider than those allowed by target specifications. issues when upgrading devices. They can be imported into SPICETOOLS.
9 Program and erase times and endurance cycles
Table 18. Program, erase times and program erase endurance cycles
10 Maximum ratings
extended periods may affect device reliability. Table 19. Absolute maximum ratings
- Minimum voltage may undershoot to –2 V for less t han 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
11 DC and AC parameters
Table 20. Operating and AC measurement conditions
1.8 V devices 30 pF
1.8 V devices 0 V DD V
Table 21. Capacitance (1)
- T A = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
- Input/output capacitances double in stacked devices.
Figure 18. Equivalent testing circuit for AC characteristics measurement
Table 22. DC characteristics, 1.8 V devices
- Leakage current and standby current double in stacked devices.
Table 23. DC characteristics, 3 V devices
- Leakage current and standby current double in stacked devices.
Table 24. AC characteristics for command, address, data input
Table 25. AC characteristics for operations (1)
- The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See Figure 31, Figure 32 and
- t WHWH is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
- During a program/erase enable operation, t WW is the delay from WP high to W High.
During a program/erase disable Operation, tWW is the delay from WP Low to W High.
- ES = electronic signature.
Figure 25. Page read operation AC waveforms
- A fifth address cycle is requ ired for 2-Gbit devices only.
Figure 26. Page program AC waveforms
- A fifth address cycle is requ ired for 2-Gbit devices only.
Figure 29. Program/erase enable waveforms Figure 30. Program/erase disable waveforms
11.1 Ready/Busy signal electrical characteristics
max is determined by the maximum value of tr.
Figure 33. Resistor value versus waveform timings for Ready/Busy signal
11.2 Data protection
A VDD detection circuit disables all NAND operations, if VDD is below the VLKO threshold. Figure 34. Data protection
Figure 35. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline Table 26. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
Figure 36. VFBGA63 9.5 x 12 mm - 6 x 8 active ball array, 0.80 mm pitch, package outline Table 27. VFBGA63 9.5 x 12 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical data
Figure 37. VFBGA63 9 x 11 mm - 6 x 8 active ball array, 0.80 mm pitch, package outline Table 28. VFBGA63 9 x 11 mm - 6 x 8 active ball array, 0.80 mm pitch, package mechanical data
Table 29. Ordering information scheme
- x16 organization only avai lable for MCP products.
- For NAND02G-B2C devices only.
- For NAND01G-B2B devices only.
Table 30. Document revision history 18-May-2006 0.1 Initial release. 01-Jun-2006 1 Document status changed to preliminary data. and VFBGA63 9.5 x 12 x 1 mm dedicated to NAND02G-B2C devices. Note 2 below Commands removed. 100 000 program/erase cycles per block. Section 3.9: Ready/Busy (RB) modified. Table 25: AC characteristics for operations. Note removed below Figure 11: Copy back program. 14-Apr-2008 5 Applied Numonyx branding.