NA555DR

SA555DR UMW | Alldatasheet

Document overview

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Technical content

S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Features Description These devices are precision timing circuits capable of 1• Timing From Microseconds to Hours producing accurate time delays or oscillation. In the• Astable or Monostable Operation time-delay or mono-stable mode of operation, the

• Adjustable Duty Cycle timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode• TTL-Compatible Output Can Sink or Source of operation, the frequency and duty cycle can beUp to 200 mA controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two- thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. IfApplications the trigger input is above the trigger level and the
• Fingerprint Biometrics threshold input is above the threshold level, the flip- flop is reset and the output is low. The reset (RESET)• Iris Biometrics input can override all other inputs and can be used to• RFID Reader initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs. Simplified Schematic UMW R SA555 w ww.umw-ic.com 1 友台半导体有限公司

V CC NC NC RESET NC NC – No internal connection NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) SE555...FK PACKAGE (TOP VIEW) Pin Configuration and Functions Pin Functions PIN D, P, PS, FK I/O DESCRIPTIONPW, JGNAME NO. Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitorCONT 5 12 I/Oconnection DISCH 7 17 O Open collector output to discharge timing capacitor GND 1 2 – Ground 1, 3, 4, 6, 8, 9, 11, 13,NC – No internal connection14, 16, 18, OUT 3 7 O High current timer output signal RESET 4 10 I Active low reset input forces output and discharge low. THRES 6 15 I End of timing input. THRES > CONT sets output low and discharge low TRIG 2 5 I Start of timing input. TRIG < ½ CONT sets output high and discharge open VCC 8 20 – Input supply voltage, 4.5 V to 16 V. (SA555 maximum is 18 V)w ww.umw-ic.com 2 友台半导体有限公司 UMW R SA555

Absolute Maximum Ratings(1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage(2) 18 V VI Input voltage CONT, RESET, THRES, TRIG VCC V IO Output current ±225 mA D package 97 P package 85 θJA Package thermal impedance(3)(4) °C/W PS package 95 PW package 149 FK package 5.61 θJC Package thermal impedance(5)(6) °C/W JG package 14.5 TJ Operating virtual junction temperature 150 °C Case temperature for 60 s FK package 260 °C Lead temperature 1,6 mm (1/16 in) from case for 60 s JG package 300 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND. (3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) - TC) / θJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (6) The package thermal impedance is calculated in accordance with MIL-STD-883. Handling Ratings PARAMETER DEFINITION MIN MAX UNIT Tstg Storage temperature range –65 150 °C Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT NA555, NE555, SA555 4.5 16 VCC Supply voltage V SE555 4.5 18 VI Input voltage CONT, RESET, THRES, and TRIG VCC V IO Output current ±200 mA NA555 –40 105 NE555 0 70 TA Operating free-air temperature °C SA555 –40 85 SE555 –55 125w ww.umw-ic.com 3 友台半导体有限公司 UMW R SA555

Electrical Characteristics

VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) NA555 SE555 NE555 PARAMETER TEST CONDITIONS UNITSA555 MIN TYP MAX MIN TYP MAX VCC = 15 V 9.4 10 10.6 8.8 10 11.2 THRES voltage level V THRES current(1) 30 250 30 250 nA 4.8 5 5.2 4.5 5 5.6 VCC = 15 V TA = –55°C to 125°C 3 6 TRIG voltage level V VCC = 5 V TA = –55°C to 125°C 1.9 TRIG current TRIG at 0 V 0.5 0.9 0.5 2 μA 0.3 0.7 1 0.3 0.7 1 RESET voltage level V TA = –55°C to 125°C 1.1 RESET at VCC 0.1 0.4 0.1 0.4 RESET current mA RESET at 0 V –0.4 –1 –0.4 –1.5 DISCH switch off-state 20 100 20 100 nAcurrent DISCH switch on-state VCC = 5 V, IO = 8 mA 0.15 0.4 Vvoltage 9.6 10 10.4 9 10 11 VCC = 15 V VCC = 5 V TA = –55°C to 125°C 2.9 3.8 0.1 0.15 0.1 0.25 VCC = 15 V, IOL = 10 mA TA = –55°C to 125°C 0.2 0.4 0.5 0.4 0.75 VCC = 15 V, IOL = 50 mA TA = –55°C to 125°C 1 2 2.2 2 2.5 VCC = 15 V, IOL = 100 mA Low-level output voltage TA = –55°C to 125°C 2.7 V VCC = 15 V, IOL = 200 mA 2.5 2.5 VCC = 5 V, IOL = 3.5 mA TA = –55°C to 125°C 0.35 0.1 0.2 0.1 0.35 VCC = 5 V, IOL = 5 mA TA = –55°C to 125°C 0.8 VCC = 5 V, IOL = 8 mA 0.15 0.25 0.15 0.4 13 13.3 12.75 13.3 VCC = 15 V, IOH = –100 mA TA = –55°C to 125°C 12 High-level output voltage VCC = 15 V, IOH = –200 mA 12.5 12.5 V 3 3.3 2.75 3.3 VCC = 5 V, IOH = –100 mA TA = –55°C to 125°C 2 VCC = 15 V 10 12 10 15 Output low, No load VCC = 5 V 3 5 3 6 Supply current mA VCC = 15 V 9 10 9 13 Output high, No load VCC = 5 V 2 4 2 5 (1) This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ.w ww.umw-ic.com 4 友台半导体有限公司 UMW R SA555

VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) NA555 SE555 NE555TESTPARAMETER UNITSA555CONDITIONS(1) MIN TYP MAX MIN TYP MAX Each timer, monostable(3) TA = 25°C 0.5 1.5(4) 1 3Initial error of timing %interval(2) Each timer, astable(5) 1.5 2.25 Each timer, monostable(3) TA = MIN to MAX 30 100(4) 50Temperature coefficient of ppm/ timing interval °CEach timer, astable(5) 90 150 CL = 15 pF,Output-pulse rise time 100 200(4) 100 300 nsTA = 25°C CL = 15 pF,Output-pulse fall time 100 200(4) 100 300 nsTA = 25°C (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. (2) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. (3) Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ, C = 0.1 μF. (4) On products compliant to MIL-PRF-38535, this parameter is not production tested. (5) Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ, C = 0.1 μF.w ww.umw-ic.com 5 友台半导体有限公司 UMW R SA555

S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Detailed Description Overview The xx555 timer is a popular and easy to use for general purpose timing applications from 10 µs to hours or from < 1mHz to 100 kHz. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. Maximum output sink and discharge sink current is greater for higher VCC and less for lower VCC. Functional Block Diagram A. Pin numbers shown are for the D, JG, P, PS, and PW packages. B. RESET can override TRIG, which can override THRES. Feature Description Mono-stable Operation For mono-stable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.w ww.umw-ic.com 8 友台半导体有限公司 UMW R SA555

VCC (5 V to 15 V) DISCH OUT VCCRESET R L R A A5T3644 C THRES GND CONT TRIG Input 0.01 µF ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Output 4 8 Pin numbers shown are shown for the D, JG, P, PS, and PW packages.

Application Information

The xx555 timer devices use resistor and capacitor charging delay to provide a programmable time delay or operating frequency. This section presents a simplified discussion of the design process. Typical Applications Missing-Pulse Detector The circuit shown in Figure 16 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is re-triggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure 17. Figure 16. Circuit for Missing-Pulse Detector

Figure 19. Pulse-Width-Modulation Waveforms

Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 20. Circuit for Pulse-Position Modulation capacitor. Both frequency and duty cycle will vary with the modulation voltage.

The timing resistors and capacitors can be chosen using this formula. tw = 1.1 × R × C. Figure 23. Sequential Timer Waveforms

www.umw-ic.com 18 友台半导体有限公司 UMW R SA555 SOP-8 Min Max Min Max A 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 D 4.700 5.100 0.185 0.200 E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 e L 0.400 1.270 0.016 0.050 θ 0 °8 °0 °8 ° Dimensions In Millimeters Dimensions In InchesSymbol 1.270(BSC) 0.050(BSC) PACKAGE OUTLINE DIMENSIONS

Ordering information

Order code Package Baseqty Deliverymode UMW NA555DR SOP-8 2500 Tape and reel UMW NE555DR SOP-8 2500 Tape and reel UMW SA555DR SOP-8 2500 Tape and reel UMW SE555DR SOP-8 2500 Tape and reel