N84C161_18 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Watchdog Monitors SDA Signal (N84C161)
  • 400 kHz I2C Bus Compatible
  • 2.7 V to 6 V Operation
  • Low Power CMOS Technology
  • 16−Byte Page Write Buffer
  • Built−in Inadvertent Write Protection ♦ VCC Lock Out ♦ Write Protection Pin, WP
  • Active High or Low Reset ♦ Precision Power Supply V oltage Monitor ♦ 5 V , 3.3 V and 3 V Systems ♦ Five Threshold V oltage Options
  • 1,000,000 Program/Erase Cycles
  • Manual Reset
  • 100 Year Data Retention
  • 8−Pin SOIC
  • Commercial and Industrial Temperature Ranges
  • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

ORDERING INFORMATION

www.onsemi.com SOIC−8 CASE 751BD For Ordering Information details, see page 11. DC RESET WP GND VCC RESET SCL SDA N84C161 N84C162 PIN CONFIGURATION PIN FUNCTIONS Pin Name Function DC Do Not Connect RESET Active Low Reset I/O WP Write Protect GND Ground SDA Serial Data/Address SCL Clock Input RESET Active High Reset I/O VCC Power Supply

Table 1. RESET THRESHOLD OPTION

Table 2. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected. CC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.

  1. Output shorted for no more than one second. No more than one output shorted at a time.

Table 3. RELIABILITY CHARACTERISTICS

  1. This parameter is tested initially and after a design or process change that affects the parameter.
  2. Latch −up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V.

Table 4. D.C. OPERATING CHARACTERISTICS VCC = 2.7 V to 6 V, unless otherwise specified. performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 5. CAPACITANCE

Table 6. AC CHARACTERISTICS VCC = 2.7 V to 6.0 V unless otherwise specified. Output Load is TTL Gate and 100 pF.

  1. This parameter is tested initially and after a design or process change that affects the parameter.

Table 7. WRITE CYCLE LIMITS cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Table 8. RESET CIRCUIT CHARACTERISTICS

pin must be connected through a pull−up resistor. 1.6 seconds, the watchdog timer times out. cleared by any transition on SDA. will not count and will stay cleared. The N84C162 does not have a Watchdog. Figure 1. RESET Output Timing

Selective/Random READ and Sequential READ. an acknowledge, then transmits the 8 −bit byte requested. Figure 9. Immediate Address Read Timing address and byte addresses of the location it wishes to read. but will generate a STOP condition. thus sending the STOP condition. the entire memory array can be read during one operation. if RESET is used as a manual reset input.

N84C161, N84C162 www.onsemi.com Figure 10. Selective Read Timing Figure 11. Sequential Read Timing Orderable Part Numbers − N84C161/2 Series (See Notes 1 − 4) Device Reset Threshold Voltage Package−Pins Shipping† N84C161WD45TG 4.50 V − 4.75 V SOIC−8

3000 Tape & Reel

N84C161WD42TG 4.25 V − 4.50 V N84C161WD30TG 3.00 V − 3.15 V N84C161WD28TG 2.85 V − 3.00 V N84C161WD25TG 2.55 V − 2.70 V N84C162WD45TG 4.50 V − 4.75 V SOIC−8 N84C162WD42TG 4.25 V − 4.50 V N84C162WD30TG 3.00 V − 3.15 V N84C162WD28TG 2.85 V − 3.00 V N84C162WD25TG 2.55 V − 2.70 V †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1. All packages are RoHS −compliant (Lead−free, Halogen−free). 2. The standard lead finish is NiPdAu. 3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 4. TDFN not available in NiPdAu (–G) version. 5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol.

SOIC 8, 150 mils CASE 751BD−01 ISSUE O DATE 19 DEC 2008 E1 E A h θ L c e b D PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. SYMBOL MIN NOM MAX θ A b c D E e h 0º 8º 0.10 0.33 0.19 0.25 4.80 5.80 3.80

1.27 BSC

1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 L 0.40 1.27 1.35 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS http://onsemi.com © Semiconductor Components Industries, LLC, 2002 October, 2002 − Rev. 0 Case Outline Number: XXX DOCUMENT NUMBER: STATUS: REFERENCE: DESCRIPTION: 98AON34272E ON SEMICONDUCTOR STANDARD SOIC 8, 150 MILS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2

DOCUMENT NUMBER: 98AON34272E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #SOIC8−002−01 TO ON SEMICONDUCTOR. REQ. BY B. BERGMAN.

19 DEC 2008

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