N54HCT08

SN54HCT08 TI | Alldatasheet

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SN54HCT08, SN74HCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Operating Voltage Range of 4.5 V to 5.5 V /C0068 Outputs Can Drive Up To 10 LSTTL Loads /C0068 Low Power Consumption, 20-µA Max ICC /C0068 Typical tpd = 13 ns /C0068 ±4-mA Output Drive at 5 V /C0068 Low Input Current of 1 µA Max /C0068 Inputs Are TTL-Voltage Compatible GND V CC SN54HCT08 ...J O R W PACKAGE SN74HCT08 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 321 2 0 1 9 91 01 11 21 3 NC NC NC NC NC V GND NC SN54HCT08 . . . FK PACKAGE (TOP VIEW) CC NC – No internal connection description/ordering information These devices contain four independent 2-input AND gates. They perform the Boolean function Y /C0043 A • Bo rY /C0043 A /C0041 B in positive logic.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING –40 C to 85C PDIP – N Tube of 25 SN74HCT08N SN74HCT08N –40 C to 85C SOIC – D Tube of 50 SN74HCT08D HCT08 –40 C to 85C SOIC – D Reel of 2500 SN74HCT08DR HCT08 –40 C to 85C Reel of 250 SN74HCT08DT –40°C to 85°C SOP – NS Reel of 2000 SN74HCT08NSR HCT08 SSOP – DB Reel of 2000 SN74HCT08DBR HT08 TSSOP – PW Tube of 90 SN74HCT08PW HT08TSSOP – PW Reel of 2000 SN74HCT08PWR HT08 Reel of 250 SN74HCT08PWT –55 C to 125C CDIP – J Tube of 25 SNJ54HCT08J SNJ54HCT08J –55°C to 125°C CFP – W Tube of 150 SNJ54HCT08W SNJ54HCT08W LCCC – FK Tube of 55 SNJ54HCT08FK SNJ54HCT08FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments IncorporatedUNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SN54HCT08, SN74HCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(each gate) INPUTS OUTPUT A B OUTPUT Y H H H L XL X L L logic diagram (positive logic) A B Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HCT08 SN74HCT08 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V ∆t/∆v Input transition rise/fall time 500 500 ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

SN54HCT08, SN74HCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HCT08 SN74HCT08 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT VOH VI = VIH or VIL IOH = –20 µA 4.5 V 4.4 4.499 4.4 4.4 VVOH VI = VIH or VIL IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84 V VOL VI = VIH or VIL IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 VVOL VI = VIH or VIL IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 V II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 5.5 V 2 40 20 µA ∆ICC † One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA C i 4.5 V to 5.5 V 3 10 10 10 pF † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC . switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HCT08 SN74HCT08 UNITPARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT tpd A or B Y

4.5 V 15 24 35 30

5.5 V 13 22 32 27

4.5 V 9 15 22 19

5.5 V 8 14 20 17

operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per gate No load 20 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. PLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74HCT08D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI SN74HCT08DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08DTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HCT08NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HCT08NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI SN74HCT08PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT08PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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