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Technical content
Features
- JEDEC TSE2004av Compliant Temperature Sensor
- DDR4 DIMM Compliant SPD EEPROM
- Temperature Range: −20°C to +125°C
- Supply Range: 1.7 V − 5.5 V (SPD EEPROM) and 2.2 V − 5.5 V (TS)
- I2C / SMBus Interface
- Schmitt Triggers and Noise Suppression Filters on SCL and SDA Inputs
- 16−Byte Page Write Buffer
- Low Power CMOS Technology
- 2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package
- These Devices are Pb−Free and are RoHS Compliant
Figure 1. Functional Symbol dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
TDFN (MT), UDFN (MU) Device Address InputA0, A1, A2 Serial Data Input/OutputSDA Serial Clock InputSCL Open−drain Event OutputEVENT Power SupplyVCC GroundVSS FunctionPin Name PIN FUNCTIONS For the location of Pin 1, please consult the corresponding package drawing. TDFN8 MT SUFFIX CASE 511AK Backside Exposed DAP at VSSDAP MARKING DIAGRAMS T34 AZZ YM T34, U34 = Specific Device Code A = Assembly Location Code ZZ = Assembly Lot Number (Last Two Digits) Y = Production Year (Last Digit) M = Production Month (1 − 9, O, N, D) /C0071 = Pb−Free Package = Pin 1 Indicator /C0071 UDFN8 MU SUFFIX CASE 517AZ TDFN8 UDFN8 (Top View) U34 AZZ YM /C0071 1 1
Table 1. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- The DC input voltage on any pin should not be lower than −0.5 V or higher than V
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC. Table 2. RELIABILITY CHARACTERISTICS Table 3. TEMPERATURE CHARACTERISTICS (VCC = 2.2 V to 3.6 V, TA = −20°C to +125°C, unless otherwise specified)
- Power Dissipation is defined as P J = (TJ − TA)//C0113JA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB. performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- The device is able to handle R
L values corresponding to the specified rise time (see Figure 2).
- Test conditions according to AC Test Conditions table. Bus loading must be such as to allow meeting the VIL and VOL as well as all other
required by the 1 MHz Fast Plus protocol.
- For the N34TS04, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out
count takes place when SCL is low in the time interval between START and STOP.
- In a “Wired−OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
or a larger bus pull−up resistor.
- The first valid temperature recording can be expected after t PU at nominal supply voltage.
Table 6. PIN CAPACITANCE (TA = 25°C, VCC = 3.6 V, f = 1 MHz) Figure 2. Pull−up Resistance vs. Load Capacitance
generated by the Master (Host). edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. These pins have on−chip pull−down resistors. to signal over/under temperature limit conditions. address inputs A0, A1, and A2. connect to the bus via their respective SCL and SDA pins. ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. busy (see A.C. Characteristics). of a HIGH to LOW transition on SDA while SCL is HIGH. START, a Slave will not respond to commands. of a LOW to HIGH transition on SDA while SCL is HIGH. bits, A2, A1 and A0, select one of 8 possible Slave devices. operation is being performed. Figure 3. Start/Stop Timing
Only one SPD page is visible (active) at any given time. The lower SPD page is automatically selected at power−up. re−activate the lower SPD page without powering down. presented in Table 9c, Table 9d, Figure 13 and Figure 14. for the (non−volatile) EEPROM data (Figure 8). Write cycle then starts following the STOP. memory is erased, i.e. all bytes are 0xFF. followed by a STOP (Figures 10a, 10b). Immediate Read sequence (Figures 11a, 11b). case the starting address is intentionally updated. Figure 6. EEPROM Byte Write
0 ACK Dummy (NoACK) Dummy (NoACK)
1 NoACK Dummy (NoACK) Dummy (NoACK)
- The Master can terminate the sequence by issuing a STOP once the N34TS04 responds with NoACK
12.The Master can terminate the sequence by responding with (NoACK) followed by STOP after any dummy data byte. 13.Setting the SPD Page Address to ‘0’ selects the lower 2−Kb EEPROM bank, setting it to ‘1’ selects the upper 2−Kb EEPROM bank. 14.The lower 2−Kb EEPROM bank (corresponding to SPD page address ‘0’) is active (visible) immediately following power−up. Figure 13. SWP & SPA Timing Figure 14. RPS & RPA Timing
www.onsemi.com Temperature Sensor Operation The TS component in the N34TS04 combines a Proportional to Absolute Temperature (PTAT) sensor with a /C0083−/C0068 modulator, yielding a 12 bit plus sign digital temperature representation. The TS runs on an internal clock, and starts a new conversion cycle at least every 100 ms. The result of the most recent conversion is stored in the Temperature Data Register (TDR) , and remains there following a TS Shut−Down. Reading from the TDR does not interfere with the conversion cycle. The value stored in the TDR is compared against limits stored in the High Limit Register (HLR), the Low Limit Register (LLR) and/or Critical Temperature Register (CTR). If the measured value is outside the alarm limits or above the critical limit, then the EVENT pin may be asserted. The EVENT output function is programmable, via the Configuration Register for interrupt mode, comparator mode and polarity. The temperature limit registers can be Read or Written by the host, via the serial interface. At power−on, all the (writable) internal registers default to 0x0000, and should therefore be initialized by the host to the desired values. The EVENT output starts out disabled (corresponding to polarity active low); thus preventing irrelevant event bus activity before the limit registers are initialized. While the TS is enabled (not shut−down), event conditions are normally generated by a change in measured temperature as recorded in the TDR, but limit changes can also trigger events as soon as the new limit creates an event condition, i.e. asynchronously with the temperature sampling activity. In order to minimize the thermal resistance between sensor and PCB, it is recommended that the exposed backside die attach pad (DAP) be soldered to the PCB ground plane. Registers The N34TS04 contains eight 16−bit wide registers allocated to TS functions, as shown in Table 10. Upon power−up, the internal address counter points to the capability register. Capability Register (User Read Only) This register lists the capabilities of the TS, as detailed in the corresponding bit map. Configuration Register (Read/Write) This register controls the various operating modes of the TS, as detailed in the corresponding bit map. Temperature Trip Point Registers (Read/Write) The N34TS04 features 3 temperature limit registers, the HLR, LLR and CLR mentioned earlier. The temperature value recorded in the TDR is compared to the various limit values, and the result is used to activate the EVENT pin. To avoid undesirable EVENT pin activity, this pin is automatically disabled at power−up to allow the host to initialize the limit registers and the converter to complete the first conversion cycle under nominal supply conditions. Data format is two’s complement with the LSB representing 0.25°C, as detailed in the corresponding bit maps. Temperature Data Register (User Read Only) This register stores the measured temperature, as well as trip status information. B15, B14, and B13 are the trip status bits, representing the relationship between measured temperature and the 3 limit values; these bits are not affected by EVENT status or by Configuration register settings regarding EVENT pin. Measured temperature is represented by bits B12 to B0. Data format is two’s complement, where B12 represents the sign, B11 represents 128°C, etc. and B0 represents 0.0625°C. Manufacturer ID Register (Read Only) The manufacturer ID assigned by the PCI−SIG trade organization to the N34TS04 device is fixed at 0x1B09. Device ID and Revision Register (Read Only) This register contains manufacturer specific device ID and device revision information.
Table 10. THE TS REGISTERS Table 11. CAPABILITY REGISTER
Table 12. CONFIGURATION REGISTER 18.Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.
- Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 15).
21.Cleared at power−on reset (POR). Once set, this bit can only be cleared by a POR condition. of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time. “wired−or” operation on the EVENT bus. 24.Can not be set as long as lock bit B6 is set.
Table 13. HIGH LIMIT REGISTER Table 14. LOW LIMIT REGISTER Table 15. TCRIT LIMIT REGISTER Table 16. TEMPERATURE DATA REGISTER
Note that trailing ‘0’ bits, are ‘0’ irrespective of polarity. resolution temperature limit registers, are always ‘0’. Table 17. 12−BIT TEMPERATURE DATA FORMAT defined by the Configuration register. temperature drops below the critical limit. settings and the hysteresis offsets, as illustrated in Figure 16. perhaps changing the EVENT output polarity. updated. This feature may be useful during testing.
www.onsemi.com PACKAGE DIMENSIONS TDFN8, 2x3, 0.5P CASE 511AK ISSUE B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP . 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ AD E B C0.10 PIN ONE REFERENCE TOP VIEW SIDE VIEW BOTTOM VIEW LD2 C C0.10 C0.08 A1 SEATING PLANE NOTE 3 b8X 0.10 C 0.05 C A B DIM MIN MAX MILLIMETERS A 0.70 0.80 A1 0.00 0.05 b 0.20 0.30 D 2.00 BSC D2 1.30 1.50 E 3.00 BSC E2 1.20 1.40 e 0.50 BSC L 0.20 0.40 1 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.50 PITCH 1.45 3.40 DIMENSIONS: MILLIMETERS NOTE 4 0.30 DETAIL A A3 0.20 REF ADETAIL B DETAIL A L ALTERNATE CONSTRUCTIONS L ÇÇÉÉ ÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTION L1 −−− 0.15 e RECOMMENDED 1.56 M M 0.68 C0.10
www.onsemi.com PACKAGE DIMENSIONS UDFN8, 2x3 EXTENDED PAD CASE 517AZ ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP . 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÇÇ ÇÇ ÇÇ ÇÇ AD E B C0.10 PIN ONE REFERENCE TOP VIEW SIDE VIEW BOTTOM VIEW LD2 C C0.10 C0.08 A1 SEATING PLANE NOTE 3 b8X 0.10 C 0.05 C A B DIM MIN MAX MILLIMETERS A 0.45 0.55 A1 0.00 0.05 b 0.20 0.30 D 2.00 BSC D2 1.35 1.45 E 3.00 BSC E2 1.25 1.35 e 0.50 BSC L 0.25 0.35 1 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.50 PITCH 1.45 3.40 DIMENSIONS: MILLIMETERS NOTE 4 0.30 DETAIL A A3 0.13 REF A DETAIL B DETAIL A L ALTERNATE CONSTRUCTIONS L L1 −−− 0.15 e RECOMMENDED 1.56 M M 0.68 C0.10 ÉÉ ÉÉÇÇ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTIONS ÉÉ ÉÉÇÇ
www.onsemi.com Example of Ordering Information Device Order Number Specific Device Marking Package Type Lead Finish Shipping Device Revision N34TS04MT3ETG T34 TDFN8 NiPdAu Tape & Reel, 4,000 Units / Reel A N34TS04MU3ETG U34 UDFN8 NiPdAu Tape & Reel, 4,000 Units / Reel A 26.All packages are RoHS−compliant (Lead−free, Halogen−free) 27.The standard lead finish is NiPdAu. 28.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Ree l Packaging Specifications Brochure, BRD8011/D. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 N34TS04/D ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . A listing of ON Semiconductor’s product/patent ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the right s of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.