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Technical content
Features
- JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD) Compliant
- Temperature Range: −40°C to +125°C
- Supply Range: 1.7 V − 3.6 V
- I2C / SMBus Interface
- Schmitt Triggers and Noise Suppression Filters on SCL and SDA Inputs
- 16−Byte Page Write Buffer
- Hardware Write Protection for Entire Memory
- Low Power CMOS Technology
- 2 x 3 x 0.5 mm UDFN Package
- These Devices are Pb−Free and are RoHS Compliant
Figure 1. Functional Symbol dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
UDFN (HU4) Device Address InputA0, A1, A2 Serial Data Input/OutputSDA Serial Clock InputSCL Write Protect InputWP Power SupplyVCC GroundVSS FunctionPin Name PIN FUNCTIONS For the location of Pin 1, please consult the corresponding package drawing. Backside Exposed DAP at VSSDAP MARKING DIAGRAM D2U = Specific Device Code A = Assembly Location Code ZZ = Assembly Lot Number (Last Two Digits) Y = Production Year (Last Digit) M = Production Month (1 − 9, O, N, D) /C0071 = Pb−Free Package UDFN8 MU3 SUFFIX CASE 517AZ D2U AZZ YM /C0071 UDFN8 (Top View)
Table 1. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- The DC input voltage on any pin should not be lower than −0.5 V or higher than V
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC. Table 2. RELIABILITY CHARACTERISTICS Table 3. THERMAL CHARACTERISTICS (Note 3)
- Power Dissipation is defined as P J = (TJ − TA)//C0113JA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
- Tested initially and after a design or process change that affects this parameter
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency is limited only by the SMBus
- Test conditions according to “A.C. Test Conditions” table.
- Tested initially and after a design or process change that affects this parameter.
INIT is the delay between the Power−On Reset threshold (VPOR+) and the device is ready to accept commands.
- Power−Off delay to ensure a proper Reset when the V CC drops below VPOR−
Table 6. A.C. TEST CONDITIONS Table 7. PIN CAPACITANCE (TA = 25°C, VCC = 3.6 V, f = 1 MHz)
Table 8. INPUT IMPEDANCE generated by the Master (Host). on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. These pins have on−chip pull−down resistors. directly either to Vcc or GND. address inputs A0, A1, and A2. connect to the bus via their respective SCL and SDA pins. ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. busy (see A.C. Characteristics). of a HIGH to LOW transition on SDA while SCL is HIGH. START, a Slave will not respond to commands. of a LOW to HIGH transition on SDA while SCL is HIGH. whether a Read (1) or Write (0) operation is being performed.
Only one SPD page is visible (active) at any given time. The lower SPD page is automatically selected at power−up. re−activate the lower SPD page without powering down. presented in Table 11c, Table 11d, Figure 12 and Figure 13. followed by a starting data byte address, followed by data. (non−volatile) EEPROM data (Figure 6). Write cycle then starts following the STOP. the Write request will be rejected. memory is erased, i.e. all bytes are 0xFF. case the starting address is intentionally updated. Figure 5. EEPROM Byte Write
0 ACK Dummy (NoACK) Dummy (NoACK)
1 NoACK Dummy (NoACK) Dummy (NoACK)
14.The Master can terminate the sequence by responding with (NoACK) followed by STOP after any dummy data byte. 15.Setting the SPD Page Address to ‘0’ selects the lower 2−Kb EEPROM bank, setting it to ‘1’ selects the upper 2−Kb EEPROM bank. 16.The lower 2−Kb EEPROM bank (corresponding to SPD page address ‘0’) is active (visible) immediately following power−up. Figure 12. SWP & SPA Timing Figure 13. RPS & RPA Timing
www.onsemi.com PACKAGE DIMENSIONS UDFN8, 2x3 EXTENDED PAD CASE 517AZ ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP . 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÇÇÇ ÇÇÇ ÇÇÇ AD E B C0.10 PIN ONE REFERENCE TOP VIEW SIDE VIEW BOTTOM VIEW LD2 C C0.10 C0.08 A1 SEATING PLANE NOTE 3 b8X 0.10 C 0.05 C A B DIM MIN MAX MILLIMETERS A 0.45 0.55 A1 0.00 0.05 b 0.20 0.30 D 2.00 BSC D2 1.35 1.45 E 3.00 BSC E2 1.25 1.35 e 0.50 BSC L 0.25 0.35 1 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.50 PITCH 1.45 3.40 DIMENSIONS: MILLIMETERS NOTE 4 0.30 DETAIL A A3 0.13 REF A DETAIL B DETAIL A L ALTERNATE CONSTRUCTIONS L L1 −−− 0.15 e RECOMMENDED 1.56 M M 0.68 C0.10 ÉÉ ÇÇ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTIONS ÉÉÇÇ ÇÇ
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