NCP3488 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Thermal Shutdown for System Protection
  • Internal Pulldown Resistor Suppresses Transient Turn On of Either MOSFET
  • Anti Cross−Conduction Protection Circuitry
  • Floating Top Driver Accommodates Boost V oltages of up to 30 V
  • One Input Signal Controls Both the Upper and Lower Gate Outputs
  • Output Disable Control Turns Off Both MOSFETs
  • Complies with VRM10.x and VRM11.x Specifications
  • Undervoltage Lockout
  • Thermal Shutdown
  • Thermally Enhanced Package Available
  • This is a Pb−Free Device Device Package Shipping †

ORDERING INFORMATION

SO−8 (Pb−Free)

2500 Tape & ReelNCP3488DR2G

A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071= Pb−Free Package MARKING DIAGRAMS PIN CONNECTIONS SO−8 D SUFFIX CASE 7511 DRVLVCC PGNDOD SWNIN DRVHBST http://onsemi.com †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. N3488 ALYW /C0071

Figure 1. Block Diagram 100 nF and 1.0 /C0109F. An external diode is required with the NCP3488. 2 IN Logic−Level Input. This pin has primary control of the drive outputs. 3 OD Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low. 4 VCC Input Supply. A 1.0 /C0109F ceramic capacitor should be connected from this pin to PGND. 5 DRVL Output drive for the lower MOSFET. 6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET. 7 SWN Switch Node. Connect to the source of the upper MOSFET. 8 DRVH Output drive for the upper MOSFET.

http://onsemi.com MAXIMUM RATINGS Rating Value Unit Operating Ambient Temperature, TA 0 to 85 °C Operating Junction Temperature, TJ (Note 1) 0 to 150 °C Package Thermal Resistance: SO−8 Junction−to−Case, R/C0113JC Junction−to−Ambient, R/C0113JA (2−Layer Board) 123 °C/W °C/W Storage Temperature Range, TS −65 to 150 °C Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb −Free (Note 3) 260 peak °C JEDEC Moisture Sensitivity Level (260 peak profile) 1 − Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above t he Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Internally limited by thermal shutdown, 150 °C min. 2. 2 layer board, 1 in 2 Cu, 1 oz thickness. 3. 60 −180 seconds minimum above 237°C. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. MAXIMUM RATINGS Pin Symbol Pin Name VMAX VMIN VCC Main Supply Voltage Input 15 V −0.3 V BST Bootstrap Supply Voltage Input 30 V wrt/PGND

35 V /C0118 50 ns wrt/PGND

15 V wrt/SW

−0.3 V wrt/SW SW Switching Node (Bootstrap Supply Return) 30 V −1.0 V DC −10 V< 200 ns DRVH High−Side Driver Output BST + 0.3 V −0.3 V wrt/SW DRVL Low−Side Driver Output VCC + 0.3 V −0.3 V DC −2.0 V < 200 ns IN DRVH and DRVL Control Input VCC + 0.3 V −0.3 V OD Output Disable VCC + 0.3 V −0.3 V PGND Ground 0 V 0 V NOTE: All voltages are with respect to PGND except where noted.

http://onsemi.com ELECTRICAL CHARACTERISTICS (Note 4) (VCC = 12 V, TA = 0°C to +85°C, TJ = 0°C to +125°C unless otherwise noted.) Characteristic Symbol Condition Min Typ Max Unit Supply Supply Voltage Range VCC − 4.6 − 13.2 V Supply Current ISYS BST = 12 V, IN = 0 V − 2.0 6.0 mA OD Input Input Voltage High − − 2.0 − − V Input Voltage Low − − − − 0.8 V Hysteresis − − − 500 − mV Input Current − No internal pull−up or pull−down resistors −1.0 − +1.0 /C0109A Propagation Delay Time (Note 5) tpdlOD tpdhOD − 30 ns ns PWM Input Input Voltage High − − 2.0 − − V Input Voltage Low − − − − 0.8 V Hysteresis − − − 500 − mV Input Current − No internal pull−up or pull−down resistors −1.0 − +1.0 /C0109A High−Side Driver Output Resistance, Sourcing Current − VBST − VSW = 12 V (Note 7) − 1.8 − /C0087 Output Resistance, Sinking Current − VBST − VSW = 12 V (Note 7) − 1.0 − /C0087 Transition Times (Note 5) trDRVH tfDRVH VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) ns ns Propagation Delay (Notes 5 & 6) tpdhDRVH tpdlDRVH VBST − VSW = 12 V − ns ns Low−Side Driver Output Resistance, Sourcing Current − VCC = 12 V (Note 7) − 1.8 − /C0087 Output Resistance, Sinking Current − VCC − VSW = 12 V (Note 7) − 1.0 − /C0087 Timeout Delay − DRVH−SW = 0 − 85 − ns Transition Times trDRVL tfDRVL CLOAD = 3.0 nF (See Figure 3) ns ns Propagation Delay tpdhDRVL tpdlDRVL (See Figure 3) − ns ns Undervoltage Lockout UVLO Startup − − 3.7 3.9 4.4 V UVLO Shutdown − − 3.2 3.5 3.9 V Hysteresis − − 0.3 0.4 0.7 V Thermal Shutdown Over Temperature Protection − (Note 7) 150 170 − °C Hysteresis (Note 7) − 20 − °C 4. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 5. AC specifications are guaranteed by characterization, but not production tested. 6. For propagation delays, “t pdh’’ refers to the specified signal going high; “tpdl’’ refers to it going low. 7. GBD: Guaranteed by design; not tested in production. Specifications subject to change without notice.

Figure 2. Output Disable Timing Diagram Figure 3. Nonoverlap Timing Diagram

12 V , but it has been optimized for high current multi−phase

3.3 nF load at frequencies up to 500 kHz. bootstrap capacitor (approaching 24 volts). node goes low during the next cycle.

will cause a decrease in the power conversion efficiency. internal pull−down resistor on the drive−on output pin. supply voltage. A minimum 50 V rating is recommended. good quality ceramic capacitor should be used. of the 12 V supply and the ESR of CBST. Figure 4. NCP3488 Example Circuit

http://onsemi.com PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AH 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751 −01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A B S DH C 0.10 (0.004) DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 NCP3488/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative